JP5659416B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
- Publication number
- JP5659416B2 JP5659416B2 JP2010280532A JP2010280532A JP5659416B2 JP 5659416 B2 JP5659416 B2 JP 5659416B2 JP 2010280532 A JP2010280532 A JP 2010280532A JP 2010280532 A JP2010280532 A JP 2010280532A JP 5659416 B2 JP5659416 B2 JP 5659416B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- forming
- etching
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having non-planar bodies, e.g. having recessed gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0402—Apparatus for fluid treatment
- H10P72/0418—Apparatus for fluid treatment for etching
- H10P72/0422—Apparatus for fluid treatment for etching for wet etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/60—Wet etching
- H10P50/64—Wet etching of semiconductor materials
- H10P50/642—Chemical etching
- H10P50/644—Anisotropic liquid etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
- H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
- H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/938—Lattice strain control or utilization
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2010-0013123 | 2010-02-12 | ||
| KR1020100013123A KR101576529B1 (ko) | 2010-02-12 | 2010-02-12 | 습식 식각을 이용한 실리콘 파셋트를 갖는 반도체 장치 및 제조방법 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011166119A JP2011166119A (ja) | 2011-08-25 |
| JP2011166119A5 JP2011166119A5 (https=) | 2013-11-28 |
| JP5659416B2 true JP5659416B2 (ja) | 2015-01-28 |
Family
ID=44369924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010280532A Active JP5659416B2 (ja) | 2010-02-12 | 2010-12-16 | 半導体素子の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8207040B2 (https=) |
| JP (1) | JP5659416B2 (https=) |
| KR (1) | KR101576529B1 (https=) |
| CN (1) | CN102157380B (https=) |
| TW (1) | TWI505349B (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102487015A (zh) * | 2010-12-03 | 2012-06-06 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
| US8383485B2 (en) * | 2011-07-13 | 2013-02-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial process for forming semiconductor devices |
| KR20140038826A (ko) | 2012-09-21 | 2014-03-31 | 삼성전자주식회사 | 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법 |
| CN104217956B (zh) * | 2013-06-05 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Pmos晶体管及其制作方法 |
| US9209175B2 (en) | 2013-07-17 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices having epitaxy regions with reduced facets |
| US9202916B2 (en) * | 2013-12-27 | 2015-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure |
| US9613974B2 (en) | 2015-03-13 | 2017-04-04 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| CN106558499B (zh) * | 2015-09-30 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管的形成方法 |
| CN106887408B (zh) | 2015-12-15 | 2019-12-17 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
| US10319832B2 (en) | 2017-04-28 | 2019-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of forming same |
| KR102365109B1 (ko) | 2017-08-22 | 2022-02-18 | 삼성전자주식회사 | 집적회로 장치 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2964925B2 (ja) | 1994-10-12 | 1999-10-18 | 日本電気株式会社 | 相補型mis型fetの製造方法 |
| TW497120B (en) * | 2000-03-06 | 2002-08-01 | Toshiba Corp | Transistor, semiconductor device and manufacturing method of semiconductor device |
| TWI225715B (en) * | 2001-09-11 | 2004-12-21 | Asia Pacific Microsystems Inc | Manufacturing method of film bulk acoustic device |
| US7303949B2 (en) * | 2003-10-20 | 2007-12-04 | International Business Machines Corporation | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture |
| JP4837902B2 (ja) * | 2004-06-24 | 2011-12-14 | 富士通セミコンダクター株式会社 | 半導体装置 |
| US7288448B2 (en) * | 2004-08-24 | 2007-10-30 | Orlowski Marius K | Method and apparatus for mobility enhancement in a semiconductor device |
| US7485941B2 (en) * | 2004-12-15 | 2009-02-03 | Tower Semiconductor Ltd. | Cobalt silicide schottky diode on isolated well |
| KR100882930B1 (ko) * | 2004-12-17 | 2009-02-10 | 삼성전자주식회사 | 소오스 및 드레인 영역들을 갖는 씨모스 반도체 소자들 및 그 제조방법들 |
| JP4369359B2 (ja) * | 2004-12-28 | 2009-11-18 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
| US7195985B2 (en) | 2005-01-04 | 2007-03-27 | Intel Corporation | CMOS transistor junction regions formed by a CVD etching and deposition sequence |
| US7629273B2 (en) * | 2006-09-19 | 2009-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for modulating stresses of a contact etch stop layer |
| US20090166625A1 (en) | 2007-12-28 | 2009-07-02 | United Microelectronics Corp. | Mos device structure |
-
2010
- 2010-02-12 KR KR1020100013123A patent/KR101576529B1/ko active Active
- 2010-12-16 JP JP2010280532A patent/JP5659416B2/ja active Active
- 2010-12-31 CN CN201010623025.9A patent/CN102157380B/zh active Active
- 2010-12-31 TW TW099147377A patent/TWI505349B/zh active
-
2011
- 2011-02-04 US US13/021,029 patent/US8207040B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR101576529B1 (ko) | 2015-12-11 |
| CN102157380B (zh) | 2015-02-04 |
| CN102157380A (zh) | 2011-08-17 |
| TW201135830A (en) | 2011-10-16 |
| KR20110093217A (ko) | 2011-08-18 |
| US20110201166A1 (en) | 2011-08-18 |
| TWI505349B (zh) | 2015-10-21 |
| JP2011166119A (ja) | 2011-08-25 |
| US8207040B2 (en) | 2012-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5659416B2 (ja) | 半導体素子の製造方法 | |
| US12342615B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN110957275B (zh) | 集成电路及其制造方法 | |
| CN109841680B (zh) | 半导体装置 | |
| US7332439B2 (en) | Metal gate transistors with epitaxial source and drain regions | |
| US7714394B2 (en) | CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same | |
| US9466697B2 (en) | Semiconductor devices and methods of manufacturing the same | |
| US7880228B2 (en) | Semiconductor device including MISFET | |
| US7372099B2 (en) | Semiconductor device and its manufacturing method | |
| US20230326799A1 (en) | Wavy-shaped epitaxial source/drain structures | |
| US7772676B2 (en) | Strained semiconductor device and method of making same | |
| TW202533691A (zh) | 半導體裝置及其製造方法 | |
| CN112750826A (zh) | 半导体器件和方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131015 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20131015 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131121 |
|
| TRDD | Decision of grant or rejection written | ||
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140918 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140930 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141003 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141111 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5659416 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |