TWI500078B - 切割具有矽穿通道之半導體晶圓之方法及其所形成之結構 - Google Patents

切割具有矽穿通道之半導體晶圓之方法及其所形成之結構 Download PDF

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TWI500078B
TWI500078B TW102132517A TW102132517A TWI500078B TW I500078 B TWI500078 B TW I500078B TW 102132517 A TW102132517 A TW 102132517A TW 102132517 A TW102132517 A TW 102132517A TW I500078 B TWI500078 B TW I500078B
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surface roughness
passivation layer
semiconductor
layer
semiconductor wafer
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TW102132517A
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English (en)
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TW201419393A (zh
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Pei Hsing Hua
Hui Shan Chang
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Advanced Semiconductor Eng
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Description

切割具有矽穿通道之半導體晶圓之方法及其所形成之結構
本發明係關於一種半導體晶圓製程。詳言之，係關於一種利用雷射技術以切割半導體晶圓之方法。
習知半導體製程中，大量的半導體元件形成於一矽晶圓上。該等半導體元件係利用形成半導體薄層、絕緣層及圖案化金屬材料以形成電性元件及積體電路所製得。在該等半導體元件形成於該晶圓上之後，每一元件(晶粒)必須分隔開。將該等個別晶粒分隔開之過程被稱做"切割(Dicing)"該晶圓。
傳統上，切割刀具(Dicing Saw)被用來切割一半導體晶圓。然而，在該半導體晶圓之厚度非常薄的地方，以切割刀具執行切割步驟時會導致該半導體晶圓崩壞(Collapse)。此外，傳統之切割刀具亦不再適用於非常窄之切割道。雖然，以雷射為主之技術已被使用以克服切割時部份問題，使用習知雷射來切割不平均表面之晶圓時之良率仍然偏低。
本揭露之一方面係關於一種半導體元件。在一實施例中，該半導體元件包括：一晶粒；至少一導電通道(Conductive Via)，形成於該晶粒中；一鈍化層(Passivation Layer)，位於該晶粒之一背面之一 部分，其中該導電通道凸出於該鈍化層；及一保護蓋(Protection Cap)，位於該導電通道之凸出端；其中該鈍化層具有一側面，該側面與該晶粒之該背面未被該鈍化層所覆蓋之一部份間之夾角大於90度。該晶粒之該背面之該未被該鈍化層所覆蓋之部份係位於沿著該晶粒之該背面之周圍之位置，且具有一第一表面粗糙度。該鈍化層之一上表面具有一第二表面粗糙度，該第一表面粗糙度實質上小於該第二表面粗糙度。該第一表面粗糙度係為雷射燒結製程之結果。此外，該晶粒之一側面具有一第一部份、一第二部份及一第三部份，該第一部份具有一第三表面粗糙度，該第二部份具有一第四表面粗糙度，且該第三部份具有一第五表面粗糙度；其中該第三表面粗糙度、該第四表面粗糙度及該第五表面粗糙度實質上不同。該第四表面粗糙度係為隱形雷射切割(Laser Stealth Dicing)之結果。在一實施例中，該第四表面粗糙度係大於該第一表面粗糙度至少50倍。此外，該第三表面粗糙度及該第五表面粗糙度個別係大於該第一表面粗糙度。
本揭露之另一方面係關於一種半導體封裝結構。在一實施例中，該半導體封裝結構包括：一第一基板；一半導體元件位於該第一基板上，且包括：一晶粒；至少一導電通道(Conductive Via)，形成於該晶粒中；一鈍化層(Passivation Layer)，位於該晶粒之一背面之一部分，其中該導電通道凸出於該鈍化層；及一保護蓋(Protection Cap)，位於該導電通道之凸出端；其中該鈍化層具有一側面，其與該晶粒之該背面未被該鈍化層所覆蓋之部份形成一鈍角；一第二半導體元件位於該半導體元件上且電性連接至該導電通道；及一封膠材料包覆該第一基板、該半導體元件及該第二半導體元件。該鈍化層具有一缺口部份，沿著該鈍化層之周圍，且該鈍化層之一側面與該晶粒之該背面形成之夾角係為90度至115度。在一實施例中，該保護蓋包括一晶種層、位於該晶種層上之一銅層、位於該銅層上之一鎳層、位於該 鎳層上之一鈀層及位於該鈀層上之一金層。在另一實施例中，該保護蓋包括一晶種層、位於該晶種層上之一銅層、位於該銅層上之一鎳層及位於該鎳層上之一錫/銀合金或一金層。該晶粒之該背面之該未被該鈍化層所覆蓋之部份係位於沿著該晶粒之該背面之周圍之位置，且具有一第一表面粗糙度。該鈍化層之一上表面具有一第二表面粗糙度，該第一表面粗糙度實質上小於該第二表面粗糙度。該第一表面粗糙度係為雷射燒結製程之結果。此外，該晶粒之一側面具有一第一部份、一第二部份及一第三部份，該第一部份具有一第三表面粗糙度，該第二部份具有一第四表面粗糙度，且該第三部份具有一第五表面粗糙度，其中該第三表面粗糙度、該第四表面粗糙度及該第五表面粗糙度實質上不同。該第四表面粗糙度係為隱形雷射切割(Laser Stealth Dicing)之結果。此外，該第三表面粗糙度及該第五表面粗糙度個別係大於該第一表面粗糙度。
本揭露之另一方面係關於一種切割半導體晶圓之方法。在一實施例中，該製造方法包括提供一半導體晶圓，該半導體晶圓具有一第一表面、一第二表面及一鈍化層，其中該鈍化層係位於該第二表面；施加一第一雷射於該鈍化層以移除該鈍化層之一部分且顯露該半導體晶圓之一部分；施加一第二雷射，其中該第二雷射穿過該半導體晶圓之該第二表面且聚焦於該半導體晶圓之一內部分；及施加一橫向力(Lateral Force)於該半導體晶圓。該方法可以更包括形成一保護蓋至每一末端。提供該半導體晶圓之步驟包括：提供該半導體晶圓，該半導體晶圓具有該第一表面、該第二表面及至少一導電通道，其中該導電通道係位於該半導體晶圓中；附著一第一載體至該半導體晶圓之該第一表面；從該第二表面移除部份該半導體晶圓，以顯露該至少一導電通道之末端；以該鈍化層覆蓋該等顯露之末端：及薄化該鈍化層使得該等末端凸出於該鈍化層。
1‧‧‧本發明之一實施例之半導體元件
2‧‧‧本發明之另一實施例之半導體封裝結構
3‧‧‧複合元件
10‧‧‧基板
11‧‧‧半導體晶圓
12‧‧‧鈍化層
14‧‧‧導電通道
16‧‧‧保護蓋
18‧‧‧主動面
20‧‧‧晶粒接墊
22‧‧‧連接元件
24‧‧‧襯層
26‧‧‧晶種層
30‧‧‧第一黏膠
31‧‧‧第一載體
32‧‧‧第一隔離塗層
34‧‧‧光阻層
36‧‧‧第二載體
38‧‧‧紫外光
40‧‧‧切割膠帶
42‧‧‧第一雷射
44‧‧‧第二雷射
45‧‧‧橫向拉力
46‧‧‧下基板
48‧‧‧上半導體元件
50‧‧‧封膠材料
52‧‧‧底膠
54‧‧‧非導電膠
56‧‧‧銲球
58‧‧‧第三載體
60‧‧‧黏膠層
101‧‧‧第一表面
102‧‧‧第二表面
103‧‧‧第三表面
103a‧‧‧第一部份
103b‧‧‧第二部份
103c‧‧‧第三部份
111‧‧‧凹痕
120‧‧‧鈍化層之上表面
121‧‧‧鈍化層之側面
122‧‧‧鈍化層之缺口部份
123‧‧‧溝槽
281‧‧‧第一導電層
282‧‧‧第二導電層
283‧‧‧第三導電層
284‧‧‧第四導電層
311‧‧‧第一載體之表面
341‧‧‧開口
361‧‧‧第二載體之第一表面
362‧‧‧第二載體之第二表面
481‧‧‧上外部連接元件
圖1顯示本發明之一實施例之半導體元件之剖視示意圖。
圖2顯示圖1之局部放大示意圖。
圖3至圖21顯示本發明之一實施例之製造該半導體元件之半導體製程之示意圖。
圖22顯示本發明之另一實施例之半導體封裝結構之剖視示意圖。
圖23至圖26顯示本發明之另一實施例之製造該半導體封裝結構之半導體製程之示意圖。
圖27至圖31顯示本發明之另一實施例之製造該半導體元件1之半導體製程之示意圖。
圖32至圖37顯示本發明之另一實施例之製造該半導體封裝結構2之半導體製程之示意圖。
參考圖1，顯示本發明之一實施例之半導體元件1之剖視示意圖。該半導體元件1包括一基板10、位於該基板10之一第一(下)表面101之一主動面18、形成於該主動面18之一積體電路(圖中未示)、位於該基板10之一第二(上)表面102之一鈍化層(Passivation Layer)12。該第二(上)表面102係為背面。該基板10更具有第三(側)表面103、形成於該基板10中之至少一導電通道(Conductive Via)14，其中一保護蓋(Protection Cap)16係形成於該導電通道14之凸出端、位於該主動面18之至少一晶粒接墊20以及分別位於每一接墊20之連接元件22。該連接元件22可以是一銅金屬柱(Copper Pillar)、銲料(Solder)或一銲料凸塊(Solder Bump)、一結線凸塊(Stud Bump)或上述任一組合。
該基板10可以由矽、鍺、砷化鎵、或其他半導體材料所製成。 該積體電路係由本領域具有通常知識者所知晶圓製造技術所形成。該主動面18具有接墊20，該接墊20電性連接至該積體電路。在本實施例中，該基板10係為一晶粒；然而，可以理解的是，該基板10可以是中介板(Interposer)，其不具有積體電路。
該鈍化層12係位於該基板10之第二表面102。該鈍化層12可以是非導電聚合物，例如聚醯亞胺(Polyimide,PI)、環氧樹脂(Epoxy)、聚苯噁唑(Polybenzoxazole,PBO)或苯環丁烯(Benzocyclobutene,BCB)；或者，無機鈍化層，例如二氧化矽(SiO2 )也可以使用。在本實施例中，該鈍化層12係為一光敏感聚合物，例如苯環丁烯(Benzocyclobutene,BCB)。
該導電通道14係位於於該基板10中且被一非導電襯層24所圍繞。該導電通道14可以由一適當導電材質(例如銅)所製成。該襯層24係為一絕緣材質(例如：非導電聚合物(包含聚醯亞胺(Polyimide,PI)、環氧樹脂(Epoxy)、聚苯噁唑(Polybenzoxazole,PBO)或苯環丁烯(Benzocyclobutene,BCB))，或無機材料(例如二氧化矽(SiO2 ))。該導電通道14貫穿該基板10及該鈍化層12，且該導電通道14及該襯層24之一端凸出於該鈍化層12。在本實施例中，該導電通道14之凸出端之上表面實質上與該襯層24之上表面共平面。
該保護蓋16係位於該導電通道14及該襯層24之凸出端。在本實施例中，該保護蓋16覆蓋該導電通道14之上表面及該襯層24之凸出部份。
參考圖2，顯示圖1之局部放大示意圖。該保護蓋16具有一晶種層26、一第一導電層281、一第二導電層282、一第三導電層283及一第四導電層284，如圖所示。在該半導體元件1之周圍，該鈍化層12之側面具有一錐形(Tapered Shaped)，其具有一角度θ。該角度θ係為下述之二階段雷射切割製程所形成之結果。
該鈍化層12具有一上表面120、一側面121及一缺口部份122。該缺口部份122圍繞該鈍化層12(亦即，該缺口部份122沿著該鈍化層12之周圍)，使得該基板10之該第二表面102之一部分被顯露。在該上表面120與該基板10之該第二表面102之間有一階梯；亦即，該鈍化層12之該側面121與該基板10之該側表面103不共平面，且該鈍化層12之該側面121與該基板10之該第二表面102之間形成一夾角θ。
該基板10之該第二表面102具有一第一表面粗糙度R1，且該鈍化層120之該上表面120具有一第二表面粗糙度R2。如下所述，該第一表面粗糙度R1係由第一階段雷射製程所導致。該第二表面粗糙度R2係大於該第一表面粗糙度R1。亦即，該第一表面粗糙度R1實質上小於該第二表面粗糙度R2。
該基板10之該側表面103具有一第一部份103a、一第二部份103b及一第三部份103c，該第一部份103a具有一第三表面粗糙度R3，該第二部份103b具有一第四表面粗糙度R4，且該第三部份103c具有一第五表面粗糙度R5。如下所述，該第四表面粗糙度R4係由第二階段雷射製程所導致。該第三表面粗糙度R3及該第五表面粗糙度R5係由橫向拉力所導致。該第三表面粗糙度R3、該第四表面粗糙度R4及該第五表面粗糙度R5實質上不同。此外，該第一表面粗糙度R1係與該第三表面粗糙度R3、該第四表面粗糙度R4及該第五表面粗糙度R5不同。
根據實驗數據，由第二雷射製程所導致之該第四表面粗糙度R4係大於由第一雷射製程所導致之該第一表面粗糙度R1。詳言之，該第四表面粗糙度R4係大於該第一表面粗糙度R1至少50倍，較佳地，至少80倍。由橫向拉力所導致之該第三表面粗糙度R3及該第五表面粗糙度R5係大於該第一表面粗糙度R1。詳言之，該第三表面粗糙度R3及該第五表面粗糙度R5係大於該第一表面粗糙度R1至少50倍。
表1顯示上述表面粗糙度之實驗數據。該實驗數據係使用白光干 涉儀所獲得，係為本技術領域所習知之非接觸方式以測量表面粗糙度("粗糙度")。如表中所示，每一表面粗糙度R1至R5使用三個樣本，且計算其平均值。舉例而言，R1(由第一雷射製程所導致)之平均粗糙度係為0.0026μm的垂線偏差(Vertical Deviation)，其與大於100倍以上之R4(由第二雷射製程所導致)之0.290μm平均粗糙度相比之下較為"平坦"(Smooth)。
參考圖3至圖21，顯示本發明之一實施例之製造該半導體元件1之半導體製程之示意圖。參考圖3，提供一半導體晶圓11。該半導體晶圓11具有一第一表面101、一第二表面102、該至少一導電通道14及複數個切割線(圖中未示)。該等切割線係標示該半導體晶圓11切割成單獨晶粒之位置。該導電通道14係位於該半導體晶圓11中。一第一黏膠30係被施加至該半導體晶圓11之第一表面101。在本實施例中，該第一黏膠30係為一可溶劑溶解的黏膠(Solvent-dissolving Adhesive)，例如住友化學公司(SUMITOMO CHEMICAL)所生產的X5000及X5300黏膠產品其中之一。
此外，提供一第一載體31，其可以是金屬、半導體材料或絕緣材料(例如玻璃)。該第一載體31具有一第一隔離塗層(Isolation Coating)32，位於其一表面311。在本實施例中，該第一隔離塗層32係為一疏水性塗層。
參考圖4，利用該第一黏膠30附著該第一載體31至該半導體晶圓11之該第一表面101。在本實施例中，該等連接元件22係埋置於該第一黏膠30中，且該第一黏膠30之厚度係大於該等連接元件22之高度。
該第一隔離塗層32之特性係為該第一隔離塗層32與該第一黏膠30間之黏著力相較於該第一黏膠30與該半導體晶圓11間之黏著力較弱。再者，該第一隔離塗層32之面積係略小於該第一黏膠30之面積，以確保該半導體晶圓11可以利用該第一黏膠30附著至該第一載體31。
當該第一載體31及該第一黏膠30浸於一溶劑(圖中未示)中，部份該第一黏膠30會被溶解，以顯露該第一隔離塗層32。接著，由於該第一黏膠30與該第一隔離塗層32間之弱黏著力，該第一載體31連同該第一隔離塗層32可以輕易地卸載(Detached)。
參考圖5，於該半導體晶圓11之第二表面102進行表面處理。以研磨及/或蝕刻方式薄化該半導體晶圓11之第二表面102，以從該第二表面102移除部份該半導體晶圓11，且該等導電通道14凸出於該半導體晶圓11之第二表面102。因此，該導電通道14之端部或末端，其可以包含該襯層24，係被顯露。
參考圖6，以例如積層製程(Laminating Process)或旋轉塗佈製程(Spin Coating Process)形成一鈍化層12於該第二表面102，以覆蓋該等導電通道14之末端。該鈍化層12可以是非導電聚合物，例如聚醯亞胺(Polyimide,PI)、環氧樹脂(Epoxy)、聚苯噁唑(Polybenzoxazole,PBO)或苯環丁烯(Benzocyclobutene,BCB)；或者，無機鈍化層，例如二氧化矽(SiO2 )也可以使用。在本實施例中，該鈍化層12可以 為一光敏感聚合物，例如苯環丁烯(Benzocyclobutene,BCB)，且可以利用旋轉塗佈或噴射塗佈(Spray Coating)而形成。
參考圖7，以研磨及/或蝕刻方式薄化該鈍化層12以使得該等導電通道14之末端凸出於該鈍化層12之外。亦即，部分該鈍化層12仍留在該半導體晶圓11之第二表面102上，且填滿該等導電通道14之末端間之區域或在該等導電通道14之末端間之區域交錯。
參考圖8，形成一保護蓋16於該導電通道14之末端及該襯層24之凸出部份。
參考圖9，其係為圖7之局部放大圖，且顯示包含該襯層24之凸出導電通道14及該鈍化層12之留存部份。該鈍化層12之留存部份係位於該等導電通道14之末端間，且低於該等導電通道14之頂端。
參考圖10，利用本領域通常知識者所知之濺鍍或其他方式形成一晶種層26，例如鈦/銅層或鈦/鎢層，於該鈍化層12、該等導電通道14及該等襯層24上。該晶種層26符合該等不同元件(包含該等導電通道14及該鈍化層12)之上表面之外形。
參考圖11，形成一光阻層34於該晶種層26上，且圖案化該光阻層34以形成複數個開口341。該等開口341之位置係對應該等導電通道14，且具有一錐狀外形，使得每一該等開口341之頂部係寬於每一該等開口341之底部。
參考圖12，形成一第一導電層281、一第二導電層282、一第三導電層283及一第四導電層284於該等開口341中且位於該等導電通道14之末端上。在本實施例中，該第一導電層281係為銅，該第二導電層282係為鎳，該第三導電層283係為鈀，且該第四導電層284係為金。然而，在其他實施例中，位於該晶種層26上之多層結構包括一第一導電層281(銅)、一第二導電層282(鎳)、一第三導電層283(錫/銀合金或金)。接著，利用光阻剝除器(Photo-resist Stripper)移除該 光阻層34，且利用蝕刻製程移除位於該第一導電層281外之部份該晶種層26，以形成該等保護蓋16。
參考圖13，提供一第二載體36。在本實施例中，該第二載體36係為一處理帶(Handling Tape)，其具有一第一表面361、一第二表面362及一位於該第二表面362之黏膠層(圖中未示)。該處理帶36之第二表面362係利用該黏膠層(圖中未示)附著至該半導體晶圓11之第二表面102上，且該等保護蓋16係埋置於該黏膠層(圖中未示)中。
參考圖14，該第一載體31及該第一黏膠30更浸於一溶劑(圖中未示)(例如：加馬丁內酯(Gamma-Butyrolactone,GBL)或丙二醇甲醚醋酸酯(Propylene glycol methyl ether acetate,PGMEA))中，部份該第一黏膠30被溶解，且顯露出該第一隔離塗層32。接著，由於該第一黏膠30與該第一隔離塗層32間之弱黏著力，該第一載體31連同該第一隔離塗層32輕易地卸載。因此，該第一載體31從該半導體晶圓11卸載。然而，在其他實施例中，可導入該半導體晶圓11之切割製程，以卸載該第一載體31。
參考圖15，利用一紫外光(UV light)(如箭頭38所示)照射該處理帶36之第一表面361以降低該處理帶36之黏著力。接著，附著一切割膠帶40，例如UV膠帶，至該半導體晶圓11之第一或下表面101。
參考圖16，將該處理帶36從該半導體晶圓11卸載，且該晶圓11之上表面(包含該等保護蓋16)係顯露。
參考圖17，施加一第一雷射42，例如一雷射燒結機器(例如迪思科公司(DISCO corporation)型號DFL7160)。該第一雷射42聚焦於該鈍化層12以移除部份該鈍化層12，且形成複數個溝槽123於該等晶圓切割線之附近。此一製程係為一雷射燒結製程(Laser Sintering Process)或一雷射刻槽製程(Laser Grooving Process)，且進一步討論如下。來自該第一雷射42融化(Melt)且揮發(Evaporate)部份該 鈍化層12，以在其頂面形成一電漿。隨著該電漿延伸至該該鈍化層12內，越來越多材料被移除，且形成該溝槽123。在本實施例中，該等溝槽123係對應該等切割線(圖中未示)，且每一該等溝槽123之寬度小於每一該等切割線之寬度。
參考圖18，其顯示圖17之局部放大圖。如圖所示，該溝槽123顯露該半導體晶圓11之第二表面102之一部分。該鈍化層12之側面121與該半導體晶圓11之第二表面102之間形成一夾角θ。該第一雷射42係用以移除部份該鈍化層12，以確保該半導體晶圓11之第二表面102之平坦性。在本實施例中，該第一雷射42係固定在特定波長，且不論較短或較長之脈衝寬度，該溝槽123皆會形成大於90度且小於115度之夾角θ。參考圖19，其顯示該鈍化層12之溝槽123之另一實施例。如圖所示，該第一雷射42更移除該半導體晶圓11而形成一凹痕111，以確保位於該切割線之表面上之鈍化層12實質上全部被移除。
參考圖20，施加一第二雷射44，例如一隱形雷射切割機器(Laser Stealth Dicing Machine)(例如迪思科公司(DISCO corporation)型號DFL7360)。該第二雷射44之雷射態樣(Type of Laser)係不同於該第一雷射42，且穿過該半導體晶圓11之顯露第二表面102。該第二雷射44聚焦於該半導體晶圓11之一內部分，以破壞該半導體晶圓11之材料之結晶結構。
具有可穿過該半導體晶圓11之波長之該第二雷射44被一物鏡聚集而聚焦於該半導體晶圓11內之一點。該第二雷射44使用短脈衝在高重複率(Repetition Rate)振盪，且可高度聚集至衍射臨限值(Diffraction Threshold Level)。該第二雷射44不論在時間上或是空間上被壓縮在光線聚焦點附近皆形成一超高尖峰功率密度(Peak Power Density)。當穿過該半導體晶圓11之該第二雷射44在聚集過程中超過一尖峰功率密度，非線性吸收效應(Nonlinear Absorption Effect)會 導致在局部點上發生超高吸收之現象。藉由最佳化該第二雷射44及光學系統特性以使該非線性吸收效應僅發生在該半導體晶圓11內之焦點附近，只有該半導體晶圓11內之局部點可以被選擇性地雷射加工而不傷害該半導體晶圓11內之前面及背面。亦即，此處所描述之隱形雷射切割係使用可穿過欲切割之單晶矽半導體晶圓之波長，使得該雷射光線可以被導引至該半導體晶圓11內雷射加工焦點附近。因此，在切割線上具有高密度錯位(High Density Dislocation)之多晶矽狀態之退化層(Degeneration Layer)會產生壓應力。
參考圖21，施加一橫向拉力(Lateral Tensile Force)(如箭頭45所示)於該半導體晶圓11，例如利用該切割膠帶40之手段，以將該晶圓11分割成複數個如圖1所示之半導體元件1。該半導體晶圓11被放在一放大裝置(圖中未示)。一橫向拉力作用在附著於該放大裝置之該半導體晶圓11。該半導體晶圓11沿著該等切割線被單體化(Singulated)，因而被分割成該等個別半導體元件1。
為了使該等個別半導體元件1達到最佳良率，該隱形雷射切割必須聚焦在該半導體晶圓11之結晶結構之正中央。因此，該半導體晶圓11之顯露第二表面102之平坦度係為重要的。然而，在本實施例中，該鈍化層12係位於具有該至少一導電通道14之該半導體晶圓11之第二表面102，該第一雷射42係用以移除部份該鈍化層12以增加該半導體晶圓11之顯露第二表面102之平坦度。再者，本實施例之切割製程係使用雷射而不使用刀具，因此不會導致該半導體晶圓11之崩壞，且適用於狹窄之切割道。
參考圖22，顯示本發明之另一實施例之半導體封裝結構2之剖視示意圖。該半導體封裝結構2包括一下基板46、該半導體元件1、一上半導體元件48及一封膠材料50。該下基板46係例如一有機基板。該半導體元件1係與圖1所示之該半導體元件1相同，且位於該下基板46 上。
該上半導體元件48係位於該半導體元件1上，且其一表面上具有至少一上外部連接元件481。該保護蓋16接觸該上外部連接元件481，使得該上半導體元件48電性連接至該導電通道14。
該封膠材料50包覆該下基板46、該半導體元件1及該上半導體元件48。在本實施例中，該半導體封裝結構2更包括一底膠52、一非導電膠54及複數個銲球56。該底膠52係位於該半導體元件1及該下基板46之間，以保護該等外部連接元件22。該非導電膠54係位於該上半導體元件48及該半導體元件1之間。該等銲球56係位於該下基板46之下表面。
參考圖23至圖26，顯示本發明之另一實施例之製造該半導體封裝結構之半導體製程之示意圖。參考圖23，提供一第三載體58及一下基板46。該下基板46係利用一黏膠層60附著至該第三載體58。
參考圖24，選取該半導體元件1，且利用一接合頭(Bonding Head)(圖中未示)將該半導體元件1接合至該下基板46。形成一底膠52於該半導體元件1及該下基板46之間，以保護該等外部連接元件22。
參考圖25，形成一非導電膠54於該鈍化層12上，且堆疊該上半導體元件48於該半導體元件1上。此時，該保護蓋16接觸該上半導體元件48之一上外部連接元件481(例如銲球)。
參考圖26，形成一封膠材料50以包覆該下基板46、該半導體元件1及該上半導體元件48。接著，移除該第三載體58及該黏膠層60，且形成複數個銲球56於該下基板46之下表面。因此，製得如圖22所示之該半導體封裝結構2。
參考圖27至圖31，顯示本發明之另一實施例之製造該半導體元件1之半導體製程之示意圖。以下所述之簡化製程之每小時產量 (Unit Per Hour,UPH)會高於上述之製程，且藉由省略於該切割膠帶40之再次設置步驟(Re-mount Step)，良率可提高。本實施例係接續圖8之步驟。
參考圖27，施加一第一雷射42，該第一雷射42聚焦於該鈍化層12以移除部份該鈍化層12，且形成複數個溝槽123。在本實施例中，該等溝槽123係對應該等切割線(圖中未示)，且每一該等溝槽123之寬度小於每一該等切割線之寬度。
參考圖28，提供一第二載體。在本實施例中，該第二載體係為一處理帶36，其具有一第一表面361、一第二表面362及一位於該第二表面362之黏膠層(圖中未示)。該處理帶36之第二表面362係利用該黏膠層(圖中未示)附著至該半導體晶圓11之第二表面102上，且該等保護蓋16係埋置於該黏膠層(圖中未示)中。
參考圖29，該第一載體31及該第一黏膠30更浸於一溶劑(圖中未示)(例如：加馬丁內酯(Gamma-Butyrolactone,GBL)或丙二醇甲醚醋酸酯(Propylene glycol methyl ether acetate,PGMEA))中，部份該第一黏膠30被溶解，且顯露出該第一隔離塗層32。接著，由於該第一黏膠30與該第一隔離塗層32間之弱黏著力，該第一載體31連同該第一隔離塗層32被卸載。因此，該第一載體31從該半導體晶圓11卸載。然而，在其他實施例中，可導入該半導體晶圓11之切割製程，以卸載該第一載體31。
參考圖30，沿著該溝槽123施加一第二雷射44。該第二雷射44係不同於該第一雷射42，且穿過該處理帶36及該半導體晶圓11之顯露第二表面102。該第二雷射44聚焦於該半導體晶圓11之一內部分，以破壞該半導體晶圓11之材料之結晶結構。在本實施例中，位於該溝槽123內之該半導體晶圓11之第二表面102在經過第一雷射42處理後會較為平坦，因此，可確保該第二雷射44之切割品質。
參考圖31，施加一橫向拉力45於該半導體晶圓11，以形成複數個如圖1所示之半導體元件1。
參考圖32至圖37，顯示本發明之另一實施例之製造該半導體封裝結構2之半導體製程之示意圖。本實施例係接續圖27之步驟。參考圖32，形成一非導電膠54於該鈍化層12上，且堆疊複數個上半導體元件48於該半導體元件1上。此時，該保護蓋16接觸該上半導體元件48之一上外部連接元件481(例如銲球)。
參考圖33，提供一第二載體。在本實施例中，該第二載體係為一處理帶36，其具有一第一表面361、一第二表面362及一位於該第二表面362之黏膠層(圖中未示)。該處理帶36之第二表面362係利用該黏膠層(圖中未示)附著至該半導體晶圓11之第二表面102上，且部份該等上半導體元件48係埋置於該黏膠層(圖中未示)中。
參考圖34，該第一載體31及該第一黏膠30更浸於一溶劑(圖中未示)(例如：加馬丁內酯(Gamma-Butyrolactone,GBL)或丙二醇甲醚醋酸酯(Propylene glycol methyl ether acetate,PGMEA))中，部份該第一黏膠30被溶解，且顯露出該第一隔離塗層32。接著，由於該第一黏膠30與該第一隔離塗層32間之弱黏著力，該第一載體31連同該第一隔離塗層32被卸載。因此，該第一載體31從該半導體晶圓11卸載。然而，在其他實施例中，可導入該半導體晶圓11之切割製程，以卸載該第一載體31。
參考圖35，沿著該溝槽123施加一第二雷射44。該第二雷射44係不同於該第一雷射42，且穿過該處理帶36及該半導體晶圓11之顯露第二表面102。該第二雷射44聚焦於該半導體晶圓11之一內部分，以破壞該半導體晶圓11之材料之結晶結構。
然而，在其他實施例中，可附著一切割膠帶(圖中未示)至該半導體晶圓11之第一表面101。接著，將該處理帶36從該半導體晶圓 11卸載，使得該第二雷射44直接穿過該半導體晶圓11之顯露第二表面102，且聚焦於該半導體晶圓11之一內部分。在本實施例中，該半導體晶圓11之顯露第二表面102在經過該第一雷射42處理後會較為平坦，以確保良好的切割品質及高良率。
參考圖36，施加一橫向拉力(如箭頭45所示)於該半導體晶圓11，以形成複數個如圖37所示之複合元件3。接著，選取該複合元件3，且利用一接合頭(圖中未示)將該複合元件3接合至該第三載體58上之該下基板46。形成一底膠52於該半導體元件1及該下基板46之間，以保護該等外部連接元件22。接著，形成一封膠材料50以包覆該下基板46及該複合元件3。接著，移除該第三載體58，且形成複數個銲球56於該下基板46之下表面。因此，製得如圖22所示之該半導體封裝結構2。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1‧‧‧本發明之一實施例之半導體元件
10‧‧‧基板
12‧‧‧鈍化層
14‧‧‧導電通道
16‧‧‧保護蓋
18‧‧‧主動面
20‧‧‧晶粒接墊
22‧‧‧連接元件
24‧‧‧襯層
101‧‧‧基板之一第一表面
102‧‧‧基板之第二表面
103‧‧‧基板之第三表面
120‧‧‧鈍化層之上表面

Claims (20)

  1. 一種半導體元件，包括：一晶粒；至少一導電通道(Conductive Via)，形成於該晶粒中；一鈍化層(Passivation Layer)，位於該晶粒之一背面之一部分，其中該導電通道凸出於該鈍化層；及一保護蓋(Protection Cap)，位於該導電通道之凸出端；其中該鈍化層具有一側面，該側面與該晶粒之該背面之一顯露部份間之夾角大於90度，該顯露部份係未被該鈍化層所覆蓋。
  2. 如請求項1之半導體元件，其中該晶粒之該背面之該顯露部份係位於沿著該晶粒之該背面之周圍之位置。
  3. 如請求項1之半導體元件，其中該晶粒之該背面之該顯露部份具有一第一表面粗糙度，該鈍化層之一上表面具有一第二表面粗糙度，該第一表面粗糙度實質上小於該第二表面粗糙度。
  4. 如請求項3之半導體元件，其中該第一表面粗糙度係為雷射燒結之結果。
  5. 如請求項1之半導體元件，其中該晶粒之一側面具有一第一部份、一第二部份及一第三部份，該第一部份具有一第三表面粗糙度，該第二部份具有一第四表面粗糙度，且該第三部份具有一第五表面粗糙度；其中該第三表面粗糙度、該第四表面粗糙度及該第五表面粗糙度實質上不同。
  6. 如請求項5之半導體元件，其中該第四表面粗糙度係為隱形雷射切割(Laser Stealth Dicing)之結果。
  7. 如請求項5之半導體元件，其中該第四表面粗糙度係大於該第一 表面粗糙度至少50倍。
  8. 如請求項5之半導體元件，其中該第三表面粗糙度及該第五表面粗糙度個別係大於該第一表面粗糙度。
  9. 一種半導體封裝結構，包括：一基板；一第一半導體元件，位於該基板上，且包括：一晶粒；至少一導電通道(Conductive Via)，形成於該晶粒中；一鈍化層(Passivation Layer)，位於該晶粒之一背面之一部分，其中該導電通道凸出於該鈍化層；及一保護蓋(Protection Cap)，位於該導電通道之凸出端；其中該鈍化層具有一缺口部份，沿著該鈍化層之周圍，且該鈍化層之一側面與該晶粒之該背面形成之夾角係為90度至115度；一第二半導體元件，位於該第一半導體元件上且電性連接至該導電通道；及一封膠材料，包覆該基板、該第一半導體元件及該第二半導體元件。
  10. 如請求項9之半導體封裝結構，其中該保護蓋包括一晶種層、位於該晶種層上之一銅層、位於該銅層上之一鎳層、位於該鎳層上之一鈀層及位於該鈀層上之一金層。
  11. 如請求項9之半導體封裝結構，其中該保護蓋包括一晶種層、位於該晶種層上之一銅層、位於該銅層上之一鎳層及位於該鎳層上之一錫/銀合金或一金層。
  12. 如請求項9之半導體封裝結構，其中該晶粒之該背面之未被該鈍化層所覆蓋之一部份具有一第一表面粗糙度，且該鈍化層之一 上表面具有一第二表面粗糙度，該第一表面粗糙度實質上小於該第二表面粗糙度。
  13. 如請求項12之之半導體封裝結構，其中該第一表面粗糙度係為雷射燒結之結果。
  14. 如請求項9之半導體封裝結構，其中該晶粒之一側面具有一第一部份、一第二部份及一第三部份，該第一部份具有一第三表面粗糙度，該第二部份具有一第四表面粗糙度，且該第三部份具有一第五表面粗糙度，其中該第三表面粗糙度、該第四表面粗糙度及該第五表面粗糙度實質上不同。
  15. 如請求項14之半導體封裝結構，其中該第四表面粗糙度係為隱形雷射切割(Laser Stealth Dicing)之結果。
  16. 如請求項14之半導體封裝結構，其中該第四表面粗糙度係大於該第一表面粗糙度至少50倍。
  17. 一種切割半導體晶圓之方法，包括：提供一半導體晶圓，該半導體晶圓具有一第一表面、一第二表面及一鈍化層，其中該鈍化層係位於該第二表面；施加一第一雷射於該鈍化層以移除該鈍化層之一部分且顯露該半導體晶圓之一部分，其中該鈍化層具有一側面，該側面與該半導體晶圓之第二表面之一顯露部份間之夾角大於90度，該顯露部份係未被該鈍化層所覆蓋；施加一第二雷射，其中該第二雷射穿過該半導體晶圓之該第二表面且聚焦於該半導體晶圓之一內部分；及施加一橫向力(Lateral Force)於該半導體晶圓。
  18. 如請求項17之方法，其中提供該半導體晶圓之步驟包括：提供該半導體晶圓，該半導體晶圓具有該第一表面、該第二表面及至少一導電通道，其中該導電通道係位於該半導體晶圓 中；附著一第一載體至該半導體晶圓之該第一表面；從該第二表面移除部份該半導體晶圓，以顯露該至少一導電通道之末端；以該鈍化層覆蓋該等顯露之末端：及薄化該鈍化層使得該等末端凸出於該鈍化層。
  19. 如請求項18之方法，更包括形成一保護蓋至每一末端。
  20. 如請求項18之方法，其中該第一雷射之雷射態樣(Type of Laser)係不同於該第二雷射。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8952544B2 (en) * 2013-07-03 2015-02-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9437575B1 (en) * 2014-01-20 2016-09-06 Amkor Technology, Inc. Semiconductor device package formed in a chip-on-wafer last process using thin film adhesives
US9633930B2 (en) * 2014-11-26 2017-04-25 Kookmin University Industry Academy Cooperation Foundation Method of forming through-hole in silicon substrate, method of forming electrical connection element penetrating silicon substrate and semiconductor device manufactured thereby
CN105895582A (zh) * 2015-01-26 2016-08-24 中芯国际集成电路制造(上海)有限公司 芯片切割方法
TWI683407B (zh) * 2017-05-23 2020-01-21 矽品精密工業股份有限公司 基板結構及其製法
DE112020000275B4 (de) 2019-06-17 2024-07-11 Rohm Co., Ltd. SiC-HALBLEITERBAUTEIL UND VERFAHREN ZUMHERSTELLEN DESSELBEN

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020084513A1 (en) * 1996-10-29 2002-07-04 Oleg Siniaguine Integrated circuits and methods for their fabrication
US20040188822A1 (en) * 2003-01-15 2004-09-30 Kazumi Hara Semiconductor chip, semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US20040238927A1 (en) * 2003-03-17 2004-12-02 Ikuya Miyazawa Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus
US20060148250A1 (en) * 2004-12-30 2006-07-06 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods

Family Cites Families (117)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761782A (en) 1971-05-19 1973-09-25 Signetics Corp Semiconductor structure, assembly and method
US4394712A (en) 1981-03-18 1983-07-19 General Electric Company Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers
US4499655A (en) 1981-03-18 1985-02-19 General Electric Company Method for making alignment-enhancing feed-through conductors for stackable silicon-on-sapphire
US4807021A (en) 1986-03-10 1989-02-21 Kabushiki Kaisha Toshiba Semiconductor device having stacking structure
US4897708A (en) 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
US4842699A (en) 1988-05-10 1989-06-27 Avantek, Inc. Method of selective via-hole and heat sink plating using a metal mask
US5191405A (en) 1988-12-23 1993-03-02 Matsushita Electric Industrial Co., Ltd. Three-dimensional stacked lsi
US5160779A (en) 1989-11-30 1992-11-03 Hoya Corporation Microprobe provided circuit substrate and method for producing the same
US5166097A (en) 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5239448A (en) 1991-10-28 1993-08-24 International Business Machines Corporation Formulation of multichip modules
US5404044A (en) 1992-09-29 1995-04-04 International Business Machines Corporation Parallel process interposer (PPI)
US5643831A (en) 1994-01-20 1997-07-01 Fujitsu Limited Process for forming solder balls on a plate having apertures using solder paste and transferring the solder balls to semiconductor device
AU3415095A (en) 1994-09-06 1996-03-27 Sheldahl, Inc. Printed circuit substrate having unpackaged integrated circuit chips directly mounted thereto and method of manufacture
US6962829B2 (en) 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP4255161B2 (ja) 1998-04-10 2009-04-15 株式会社野田スクリーン 半田バンプ形成装置
JP3447961B2 (ja) 1998-08-26 2003-09-16 富士通株式会社 半導体装置の製造方法及び半導体製造装置
US20020017855A1 (en) 1998-10-01 2002-02-14 Complete Substrate Solutions Limited Visual display
US6295730B1 (en) 1999-09-02 2001-10-02 Micron Technology, Inc. Method and apparatus for forming metal contacts on a substrate
US6329631B1 (en) 1999-09-07 2001-12-11 Ray Yueh Solder strip exclusively for semiconductor packaging
TW434854B (en) 1999-11-09 2001-05-16 Advanced Semiconductor Eng Manufacturing method for stacked chip package
TW569424B (en) 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
JP4023076B2 (ja) 2000-07-27 2007-12-19 富士通株式会社 表裏導通基板及びその製造方法
US6406934B1 (en) 2000-09-05 2002-06-18 Amkor Technology, Inc. Wafer level production of chip size semiconductor packages
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6448506B1 (en) 2000-12-28 2002-09-10 Amkor Technology, Inc. Semiconductor package and circuit board for making the package
US6740950B2 (en) 2001-01-15 2004-05-25 Amkor Technology, Inc. Optical device packages having improved conductor efficiency, optical coupling and thermal transfer
JP4113679B2 (ja) 2001-02-14 2008-07-09 イビデン株式会社 三次元実装パッケージの製造方法
JP2002270718A (ja) 2001-03-07 2002-09-20 Seiko Epson Corp 配線基板及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
JP2002373957A (ja) 2001-06-14 2002-12-26 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US7334326B1 (en) 2001-06-19 2008-02-26 Amkor Technology, Inc. Method for making an integrated circuit substrate having embedded passive components
JP3875867B2 (ja) 2001-10-15 2007-01-31 新光電気工業株式会社 シリコン基板の穴形成方法
JP4110390B2 (ja) * 2002-03-19 2008-07-02 セイコーエプソン株式会社 半導体装置の製造方法
JP3904484B2 (ja) 2002-06-19 2007-04-11 新光電気工業株式会社 シリコン基板のスルーホールプラギング方法
KR20050074961A (ko) 2002-10-08 2005-07-19 치팩, 인코포레이티드 역전된 제 2 패키지를 구비한 반도체 적층형 멀티-패키지모듈
JP2004228135A (ja) 2003-01-20 2004-08-12 Mitsubishi Electric Corp 微細孔への金属埋め込み方法
JP2004228392A (ja) * 2003-01-24 2004-08-12 Seiko Epson Corp 半導体装置の製造方法および半導体モジュールの製造方法
JP2004273563A (ja) 2003-03-05 2004-09-30 Shinko Electric Ind Co Ltd 基板の製造方法及び基板
US6908856B2 (en) 2003-04-03 2005-06-21 Interuniversitair Microelektronica Centrum (Imec) Method for producing electrical through hole interconnects and devices made thereof
WO2005031863A1 (en) 2003-09-26 2005-04-07 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
US7276787B2 (en) 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US20050189635A1 (en) 2004-03-01 2005-09-01 Tessera, Inc. Packaged acoustic and electromagnetic transducer chips
US20050258545A1 (en) 2004-05-24 2005-11-24 Chippac, Inc. Multiple die package with adhesive/spacer structure and insulated die surface
JP4343044B2 (ja) 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
TWI242869B (en) 2004-10-15 2005-11-01 Advanced Semiconductor Eng High density substrate for multi-chip package
TWI254425B (en) 2004-10-26 2006-05-01 Advanced Semiconductor Eng Chip package structure, chip packaging process, chip carrier and manufacturing process thereof
JP3987521B2 (ja) 2004-11-08 2007-10-10 新光電気工業株式会社 基板の製造方法
JP4369348B2 (ja) 2004-11-08 2009-11-18 新光電気工業株式会社 基板及びその製造方法
KR100687069B1 (ko) 2005-01-07 2007-02-27 삼성전자주식회사 보호판이 부착된 이미지 센서 칩과 그의 제조 방법
TWI244186B (en) 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
TWI264807B (en) 2005-03-02 2006-10-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
US7285434B2 (en) 2005-03-09 2007-10-23 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same
TWI261325B (en) 2005-03-25 2006-09-01 Advanced Semiconductor Eng Package structure of semiconductor and wafer-level formation thereof
US7215032B2 (en) 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7989958B2 (en) 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
JP2007027451A (ja) 2005-07-19 2007-02-01 Shinko Electric Ind Co Ltd 回路基板及びその製造方法
JP4889974B2 (ja) 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
JP4716819B2 (ja) 2005-08-22 2011-07-06 新光電気工業株式会社 インターポーザの製造方法
US7488680B2 (en) 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers
TWI311356B (en) 2006-01-02 2009-06-21 Advanced Semiconductor Eng Package structure and fabricating method thereof
TWI303105B (en) 2006-01-11 2008-11-11 Advanced Semiconductor Eng Wafer level package for image sensor components and its fabricating method
TWI293499B (en) 2006-01-25 2008-02-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
TWI287274B (en) 2006-01-25 2007-09-21 Advanced Semiconductor Eng Three dimensional package and method of making the same
TWI287273B (en) 2006-01-25 2007-09-21 Advanced Semiconductor Eng Three dimensional package and method of making the same
US7304859B2 (en) 2006-03-30 2007-12-04 Stats Chippac Ltd. Chip carrier and fabrication method
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
JP5026038B2 (ja) 2006-09-22 2012-09-12 新光電気工業株式会社 電子部品装置
TWI315295B (en) 2006-12-29 2009-10-01 Advanced Semiconductor Eng Mems microphone module and method thereof
US7598163B2 (en) 2007-02-15 2009-10-06 John Callahan Post-seed deposition process
TW200839903A (en) 2007-03-21 2008-10-01 Advanced Semiconductor Eng Method for manufacturing electrical connections in wafer
JP5078687B2 (ja) * 2007-03-22 2012-11-21 日本特殊陶業株式会社 多層配線基板の製造方法
TWI335654B (en) 2007-05-04 2011-01-01 Advanced Semiconductor Eng Package for reducing stress
US7553752B2 (en) 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
TWI335059B (en) 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
TWI357118B (en) 2007-08-02 2012-01-21 Advanced Semiconductor Eng Method for forming vias in a substrate
TWI387019B (zh) 2007-08-02 2013-02-21 Advanced Semiconductor Eng 在基材上形成穿導孔之方法
TWI344694B (en) 2007-08-06 2011-07-01 Siliconware Precision Industries Co Ltd Sensor-type package and method for fabricating the same
TWI345296B (en) 2007-08-07 2011-07-11 Advanced Semiconductor Eng Package having a self-aligned die and the method for making the same, and a stacked package and the method for making the same
JP5536322B2 (ja) 2007-10-09 2014-07-02 新光電気工業株式会社 基板の製造方法
US7691747B2 (en) 2007-11-29 2010-04-06 STATS ChipPAC, Ltd Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
TWI365483B (en) 2007-12-04 2012-06-01 Advanced Semiconductor Eng Method for forming a via in a substrate
US7838395B2 (en) 2007-12-06 2010-11-23 Stats Chippac, Ltd. Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same
US7851246B2 (en) 2007-12-27 2010-12-14 Stats Chippac, Ltd. Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device
US8072079B2 (en) 2008-03-27 2011-12-06 Stats Chippac, Ltd. Through hole vias at saw streets including protrusions or recesses for interconnection
US7666711B2 (en) 2008-05-27 2010-02-23 Stats Chippac, Ltd. Semiconductor device and method of forming double-sided through vias in saw streets
US7741156B2 (en) 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
TWI420640B (zh) 2008-05-28 2013-12-21 矽品精密工業股份有限公司 半導體封裝裝置、半導體封裝結構及其製法
US8101460B2 (en) 2008-06-04 2012-01-24 Stats Chippac, Ltd. Semiconductor device and method of shielding semiconductor die from inter-device interference
US7851893B2 (en) 2008-06-10 2010-12-14 Stats Chippac, Ltd. Semiconductor device and method of connecting a shielding layer to ground through conductive vias
US7863721B2 (en) 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
TWI365528B (en) 2008-06-27 2012-06-01 Advanced Semiconductor Eng Semiconductor structure and method for manufacturing the same
US8183087B2 (en) 2008-09-09 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component
US9559046B2 (en) 2008-09-12 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-in package-on-package structure using through silicon vias
US7772081B2 (en) 2008-09-17 2010-08-10 Stats Chippac, Ltd. Semiconductor device and method of forming high-frequency circuit structure and method thereof
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US7741148B1 (en) 2008-12-10 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support
US8283250B2 (en) 2008-12-10 2012-10-09 Stats Chippac, Ltd. Semiconductor device and method of forming a conductive via-in-via structure
US8017515B2 (en) 2008-12-10 2011-09-13 Stats Chippac, Ltd. Semiconductor device and method of forming compliant polymer layer between UBM and conformal dielectric layer/RDL for stress relief
US8900921B2 (en) 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
US7786008B2 (en) 2008-12-12 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof
TWI387084B (zh) 2009-01-23 2013-02-21 Advanced Semiconductor Eng 具有穿導孔之基板及具有穿導孔之基板之封裝結構
TWI470766B (zh) 2009-03-10 2015-01-21 Advanced Semiconductor Eng 晶片結構、晶圓結構以及晶片製程
TWI380421B (en) 2009-03-13 2012-12-21 Advanced Semiconductor Eng Method for making silicon wafer having through via
TW201034150A (en) 2009-03-13 2010-09-16 Advanced Semiconductor Eng Silicon wafer having interconnection metal
TWI394253B (zh) 2009-03-25 2013-04-21 Advanced Semiconductor Eng 具有凸塊之晶片及具有凸塊之晶片之封裝結構
TWI394221B (zh) 2009-04-30 2013-04-21 Advanced Semiconductor Eng 具有測試銲墊之矽晶圓及其測試方法
US20100327465A1 (en) 2009-06-25 2010-12-30 Advanced Semiconductor Engineering, Inc. Package process and package structure
US8471156B2 (en) 2009-08-28 2013-06-25 Advanced Semiconductor Engineering, Inc. Method for forming a via in a substrate and substrate with a via
TWI406380B (zh) 2009-09-23 2013-08-21 Advanced Semiconductor Eng 具有穿導孔之半導體元件及其製造方法及具有穿導孔之半導體元件之封裝結構
US8399987B2 (en) * 2009-12-04 2013-03-19 Samsung Electronics Co., Ltd. Microelectronic devices including conductive vias, conductive caps and variable thickness insulating layers
KR101692434B1 (ko) * 2010-06-28 2017-01-18 삼성전자주식회사 반도체 소자 및 그 제조 방법
TWI434387B (zh) * 2010-10-11 2014-04-11 Advanced Semiconductor Eng 具有穿導孔之半導體裝置及具有穿導孔之半導體裝置之封裝結構及其製造方法
KR101739939B1 (ko) * 2011-03-16 2017-05-26 삼성전자주식회사 반도체 장치의 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020084513A1 (en) * 1996-10-29 2002-07-04 Oleg Siniaguine Integrated circuits and methods for their fabrication
US20040188822A1 (en) * 2003-01-15 2004-09-30 Kazumi Hara Semiconductor chip, semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US20040238927A1 (en) * 2003-03-17 2004-12-02 Ikuya Miyazawa Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus
US20060148250A1 (en) * 2004-12-30 2006-07-06 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods

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