CN103811458B - 切割具有硅穿通道的半导体晶圆的方法及其所形成的结构 - Google Patents

切割具有硅穿通道的半导体晶圆的方法及其所形成的结构 Download PDF

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CN103811458B
CN103811458B CN201310452834.1A CN201310452834A CN103811458B CN 103811458 B CN103811458 B CN 103811458B CN 201310452834 A CN201310452834 A CN 201310452834A CN 103811458 B CN103811458 B CN 103811458B
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surface roughness
semiconductor
passivation layer
laser
crystal wafer
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CN103811458A (zh
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花霈馨
张惠珊
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明提供一种半导体元件、一种半导体封装结构及一种半导体工艺。该半导体工艺包含以下步骤：(a)提供一半导体晶圆，该半导体晶圆具有一第一表面、一第二表面及一钝化层；(b)施加一第一激光于该钝化层以移除该钝化层的一部分且显露该半导体晶圆的一部分；(c)施加一第二激光，其中该第二激光穿过该半导体晶圆的该第二表面且聚焦于该半导体晶圆的一内部分；及(d)施加一横向力于该半导体晶圆。藉此，可确保切割品质。

Description

切割具有硅穿通道的半导体晶圆的方法及其所形成的结构
技术领域
本发明是关于一种半导体晶圆工艺。详言之，是关于一种利用激光技术以切割半导体晶圆的方法。
背景技术
已知半导体工艺中，大量的半导体元件形成于一硅晶圆上。该等半导体元件是利用形成半导体薄层、绝缘层及图案化金属材料以形成电性元件及集成电路所制得。在该等半导体元件形成于该晶圆上之后，每一元件（晶粒）必须分隔开。将该等个别晶粒分隔开的过程被称做"切割（Dicing）"该晶圆。
传统上，切割刀具（Dicing Saw）被用来切割一半导体晶圆。然而，在该半导体晶圆的厚度非常薄的地方，以切割刀具执行切割步骤时会导致该半导体晶圆崩坏（Collapse）。此外，传统的切割刀具亦不再适用于非常窄的切割道。虽然，以激光为主的技术已被使用以克服切割时部份问题，使用已知激光来切割不平均表面的晶圆时的良率仍然偏低。
发明内容
本揭露的一方面是关于一种半导体元件。在一实施例中，该半导体元件包括：一晶粒；至少一导电通道（Conductive Via），形成于该晶粒中；一钝化层（PassivationLayer），位于该晶粒的一背面的一部分，其中该导电通道凸出于该钝化层；及一保护盖（Protection Cap），位于该导电通道的凸出端；其中该钝化层具有一侧面，该侧面与该晶粒的该背面未被该钝化层所覆盖的一部份间的夹角大于90度。该晶粒的该背面的该未被该钝化层所覆盖的部份是位于沿着该晶粒的该背面的周围的位置，且具有一第一表面粗糙度。该钝化层的一上表面具有一第二表面粗糙度，该第一表面粗糙度实质上小于该第二表面粗糙度。该第一表面粗糙度为激光烧结工艺的结果。此外，该晶粒的一侧面具有一第一部份、一第二部份及一第三部份，该第一部份具有一第三表面粗糙度，该第二部份具有一第四表面粗糙度，且该第三部份具有一第五表面粗糙度；其中该第三表面粗糙度、该第四表面粗糙度及该第五表面粗糙度实质上不同。该第四表面粗糙度为隐形激光切割（Laser Stealth Dicing）的结果。在一实施例中，该第四表面粗糙度是大于该第一表面粗糙度至少50倍。此外，该第三表面粗糙度及该第五表面粗糙度个别是大于该第一表面粗糙度。
本揭露的另一方面是关于一种半导体封装结构。在一实施例中，该半导体封装结构包括：一第一基板；一半导体元件位于该第一基板上，且包括：一晶粒；至少一导电通道（Conductive Via），形成于该晶粒中；一钝化层（Passivation Layer），位于该晶粒的一背面的一部分，其中该导电通道凸出于该钝化层；及一保护盖（Protection Cap），位于该导电通道的凸出端；其中该钝化层具有一侧面，其与该晶粒的该背面未被该钝化层所覆盖的部份形成一钝角；一第二半导体元件位于该半导体元件上且电性连接至该导电通道；及一封胶材料包覆该第一基板、该半导体元件及该第二半导体元件。该钝化层具有一缺口部份，沿着该钝化层的周围，且该钝化层的一侧面与该晶粒的该背面形成的夹角为90度至115度。在一实施例中，该保护盖包括一晶种层、位于该晶种层上的一铜层、位于该铜层上的一镍层、位于该镍层上的一钯层及位于该钯层上的一金层。在另一实施例中，该保护盖包括一晶种层、位于该晶种层上的一铜层、位于该铜层上的一镍层及位于该镍层上的一锡/银合金或一金层。该晶粒的该背面的该未被该钝化层所覆盖的部份是位于沿着该晶粒的该背面的周围的位置，且具有一第一表面粗糙度。该钝化层的一上表面具有一第二表面粗糙度，该第一表面粗糙度实质上小于该第二表面粗糙度。该第一表面粗糙度为激光烧结工艺的结果。此外，该晶粒的一侧面具有一第一部份、一第二部份及一第三部份，该第一部份具有一第三表面粗糙度，该第二部份具有一第四表面粗糙度，且该第三部份具有一第五表面粗糙度，其中该第三表面粗糙度、该第四表面粗糙度及该第五表面粗糙度实质上不同。该第四表面粗糙度为隐形激光切割（Laser StealthDicing）的结果。此外，该第三表面粗糙度及该第五表面粗糙度个别是大于该第一表面粗糙度。
本揭露的另一方面是关于一种切割半导体晶圆的方法。在一实施例中，该制造方法包括提供一半导体晶圆，该半导体晶圆具有一第一表面、一第二表面及一钝化层，其中该钝化层是位于该第二表面；施加一第一激光于该钝化层以移除该钝化层的一部分且显露该半导体晶圆的一部分；施加一第二激光，其中该第二激光穿过该半导体晶圆的该第二表面且聚焦于该半导体晶圆的一内部分；及施加一横向力（Lateral Force）于该半导体晶圆。该方法可以更包括形成一保护盖至每一末端。提供该半导体晶圆的步骤包括：提供该半导体晶圆，该半导体晶圆具有该第一表面、该第二表面及至少一导电通道，其中该导电通道是位于该半导体晶圆中；附着一第一载体至该半导体晶圆的该第一表面；从该第二表面移除部份该半导体晶圆，以显露该至少一导电通道的末端；以该钝化层覆盖该等显露的末端：及薄化该钝化层使得该等末端凸出于该钝化层。
附图说明
图1显示本发明的一实施例的半导体元件的剖视示意图。
图2显示图1的局部放大示意图。
图3至图21显示本发明的一实施例的制造该半导体元件的半导体工艺的示意图。
图22显示本发明的另一实施例的半导体封装结构的剖视示意图。
图23至图26显示本发明的另一实施例的制造该半导体封装结构的半导体工艺的示意图。
图27至图31显示本发明的另一实施例的制造该半导体元件1的半导体工艺的示意图。
图32至图37显示本发明的另一实施例的制造该半导体封装结构2的半导体工艺的示意图。
具体实施方式
参考图1，显示本发明的一实施例的半导体元件1的剖视示意图。该半导体元件1包括一基板10、位于该基板10的一第一（下）表面101的一主动面18、形成于该主动面18的一集成电路（图中未示）、位于该基板10的一第二（上）表面102的一钝化层（Passivation Layer）12。该第二（上）表面102为背面。该基板10更具有第三（侧）表面103、形成于该基板10中的至少一导电通道（Conductive Via）14，其中一保护盖（Protection Cap）16是形成于该导电通道14的凸出端、位于该主动面18的至少一晶粒接垫20以及分别位于每一接垫20的连接元件22。该连接元件22可以是一铜金属柱（Copper Pillar）、焊料（Solder）或一焊料凸块（Solder Bump）、一结线凸块（Stud Bump）或上述任一组合。
该基板10可以由硅、锗、砷化镓、或其他半导体材料所制成。该集成电路是由本领域具有通常知识者所知晶圆制造技术所形成。该主动面18具有接垫20，该接垫20电性连接至该集成电路。在本实施例中，该基板10为一晶粒；然而，可以理解的是，该基板10可以是中介板（Interposer），其不具有集成电路。
该钝化层12是位于该基板10的第二表面102。该钝化层12可以是非导电聚合物，例如聚酰亚胺（Polyimide,PI）、环氧树脂（Epoxy）、聚苯恶唑（Polybenzoxazole,PBO）或苯环丁烯（Benzocyclobutene,BCB）；或者，无机钝化层，例如二氧化硅（SiO2）也可以使用。在本实施例中，该钝化层12为一光敏感聚合物，例如苯环丁烯（Benzocyclobutene,BCB）。
该导电通道14是位于于该基板10中且被一非导电衬层24所围绕。该导电通道14可以由一适当导电材质（例如铜）所制成。该衬层24为一绝缘材质（例如：非导电聚合物（包含聚酰亚胺(Polyimide,PI)、环氧树脂(Epoxy)、聚苯恶唑(Polybenzoxazole,PBO)或苯环丁烯(Benzocyclobutene,BCB)），或无机材料（例如二氧化硅(SiO2)）。该导电通道14贯穿该基板10及该钝化层12，且该导电通道14及该衬层24的一端凸出于该钝化层12。在本实施例中，该导电通道14的凸出端的上表面实质上与该衬层24的上表面共平面。
该保护盖16是位于该导电通道14及该衬层24的凸出端。在本实施例中，该保护盖16覆盖该导电通道14的上表面及该衬层24的凸出部份。
参考图2，显示图1的局部放大示意图。该保护盖16具有一晶种层26、一第一导电层281、一第二导电层282、一第三导电层283及一第四导电层284，如图所示。在该半导体元件1的周围，该钝化层12的侧面具有一锥形（Tapered Shaped），其具有一角度θ。该角度θ为下述的二阶段激光切割工艺所形成的结果。
该钝化层12具有一上表面120、一侧面121及一缺口部份122。该缺口部份122围绕该钝化层12（亦即，该缺口部份122沿着该钝化层12的周围），使得该基板10的该第二表面102的一部分被显露。在该上表面120与该基板10的该第二表面102之间有一阶梯；亦即，该钝化层12的该侧面121与该基板10的该侧表面103不共平面，且该钝化层12的该侧面121与该基板10的该第二表面102之间形成一夹角θ。
该基板10的该第二表面102具有一第一表面粗糙度R1，且该钝化层120的该上表面120具有一第二表面粗糙度R2。如下所述，该第一表面粗糙度R1是由第一阶段激光工艺所导致。该第二表面粗糙度R2是大于该第一表面粗糙度R1。亦即，该第一表面粗糙度R1实质上小于该第二表面粗糙度R2。
该基板10的该侧表面103具有一第一部份103a、一第二部份103b及一第三部份103c，该第一部份103a具有一第三表面粗糙度R3，该第二部份103b具有一第四表面粗糙度R4，且该第三部份103c具有一第五表面粗糙度R5。如下所述，该第四表面粗糙度R4是由第二阶段激光工艺所导致。该第三表面粗糙度R3及该第五表面粗糙度R5是由横向拉力所导致。该第三表面粗糙度R3、该第四表面粗糙度R4及该第五表面粗糙度R5实质上不同。此外，该第一表面粗糙度R1是与该第三表面粗糙度R3、该第四表面粗糙度R4及该第五表面粗糙度R5不同。
根据实验数据，由第二激光工艺所导致的该第四表面粗糙度R4是大于由第一激光工艺所导致的该第一表面粗糙度R1。详言之，该第四表面粗糙度R4是大于该第一表面粗糙度R1至少50倍，较佳地，至少80倍。由横向拉力所导致的该第三表面粗糙度R3及该第五表面粗糙度R5是大于该第一表面粗糙度R1。详言之，该第三表面粗糙度R3及该第五表面粗糙度R5是大于该第一表面粗糙度R1至少50倍。
表1显示上述表面粗糙度的实验数据。该实验数据是使用白光干涉仪所获得，为本技术领域所已知的非接触方式以测量表面粗糙度（"粗糙度"）。如表中所示，每一表面粗糙度R1至R5使用三个样本，且计算其平均值。举例而言，R1（由第一激光工艺所导致）的平均粗糙度为0.0026μm的垂线偏差（Vertical Deviation），其与大于100倍以上的R4（由第二激光工艺所导致）的0.290μm平均粗糙度相比的下较为"平坦"（Smooth）。
表1
参考图3至图21，显示本发明的一实施例的制造该半导体元件1的半导体工艺的示意图。参考图3，提供一半导体晶圆11。该半导体晶圆11具有一第一表面101、一第二表面102、该至少一导电通道14及数个切割线（图中未示）。该等切割线是标示该半导体晶圆11切割成单独晶粒的位置。该导电通道14是位于该半导体晶圆11中。一第一黏胶30是被施加至该半导体晶圆11的第一表面101。在本实施例中，该第一黏胶30为一可溶剂溶解的黏胶(Solvent-dissolving Adhesive)，例如住友化学公司(SUMITOMO CHEMICAL)所生产的X5000及X5300黏胶产品其中之一。
此外，提供一第一载体31，其可以是金属、半导体材料或绝缘材料（例如玻璃）。该第一载体31具有一第一隔离涂层(Isolation Coating)32，位于其一表面311。在本实施例中，该第一隔离涂层32为一疏水性涂层。
参考图4，利用该第一黏胶30附着该第一载体31至该半导体晶圆11的该第一表面101。在本实施例中，该等连接元件22是埋置于该第一黏胶30中，且该第一黏胶30的厚度是大于该等连接元件22的高度。
该第一隔离涂层32的特性为该第一隔离涂层32与该第一黏胶30间的黏着力相较于该第一黏胶30与该半导体晶圆11间的黏着力较弱。再者，该第一隔离涂层32的面积是略小于该第一黏胶30的面积，以确保该半导体晶圆11可以利用该第一黏胶30附着至该第一载体31。
当该第一载体31及该第一黏胶30浸于一溶剂（图中未示）中，部份该第一黏胶30会被溶解，以显露该第一隔离涂层32。接着，由于该第一黏胶30与该第一隔离涂层32间的弱黏着力，该第一载体31连同该第一隔离涂层32可以轻易地卸载（Detached）。
参考图5，于该半导体晶圆11的第二表面102进行表面处理。以研磨及/或蚀刻方式薄化该半导体晶圆11的第二表面102，以从该第二表面102移除部份该半导体晶圆11，且该等导电通道14凸出于该半导体晶圆11的第二表面102。因此，该导电通道14的端部或末端，其可以包含该衬层24，是被显露。
参考图6，以例如积层工艺(Laminating Process)或旋转涂布工艺(Spin CoatingProcess)形成一钝化层12于该第二表面102，以覆盖该等导电通道14的末端。该钝化层12可以是非导电聚合物，例如聚酰亚胺（Polyimide,PI）、环氧树脂（Epoxy）、聚苯恶唑（Polybenzoxazole,PBO）或苯环丁烯（Benzocyclobutene,BCB）；或者，无机钝化层，例如二氧化硅（SiO2）也可以使用。在本实施例中，该钝化层12可以为一光敏感聚合物，例如苯环丁烯（Benzocyclobutene,BCB），且可以利用旋转涂布或喷射涂布(Spray Coating)而形成。
参考图7，以研磨及/或蚀刻方式薄化该钝化层12以使得该等导电通道14的末端凸出于该钝化层12之外。亦即，部分该钝化层12仍留在该半导体晶圆11的第二表面102上，且填满该等导电通道14的末端间的区域或在该等导电通道14的末端间的区域交错。
参考图8，形成一保护盖16于该导电通道14的末端及该衬层24的凸出部份。
参考图9，其为图7的局部放大图，且显示包含该衬层24的凸出导电通道14及该钝化层12的留存部份。该钝化层12的留存部份是位于该等导电通道14的末端间，且低于该等导电通道14的顶端。
参考图10，利用本领域通常知识者所知的溅镀或其他方式形成一晶种层26，例如钛/铜层或钛/钨层，于该钝化层12、该等导电通道14及该等衬层24上。该晶种层26符合该等不同元件（包含该等导电通道14及该钝化层12）的上表面的外形。
参考图11，形成一光阻层34于该晶种层26上，且图案化该光阻层34以形成数个开口341。该等开口341的位置是对应该等导电通道14，且具有一锥状外形，使得每一该等开口341的顶部是宽于每一该等开口341的底部。
参考图12，形成一第一导电层281、一第二导电层282、一第三导电层283及一第四导电层284于该等开口341中且位于该等导电通道14的末端上。在本实施例中，该第一导电层281为铜，该第二导电层282为镍，该第三导电层283为钯，且该第四导电层284为金。然而，在其他实施例中，位于该晶种层26上的多层结构包括一第一导电层281（铜）、一第二导电层282（镍）、一第三导电层283（锡/银合金或金）。接着，利用光阻剥除器（Photo-resist Stripper）移除该光阻层34，且利用蚀刻工艺移除位于该第一导电层281外的部份该晶种层26，以形成该等保护盖16。
参考图13，提供一第二载体36。在本实施例中，该第二载体36为一处理带（Handling Tape），其具有一第一表面361、一第二表面362及一位于该第二表面362的黏胶层（图中未示）。该处理带36的第二表面362是利用该黏胶层（图中未示）附着至该半导体晶圆11的第二表面102上，且该等保护盖16是埋置于该黏胶层（图中未示）中。
参考图14，该第一载体31及该第一黏胶30更浸于一溶剂（图中未示）（例如：加马丁内酯(Gamma-Butyrolactone,GBL)或丙二醇甲醚醋酸酯(Propylene glycolmethyl ether acetate,PGMEA)）中，部份该第一黏胶30被溶解，且显露出该第一隔离涂层32。接着，由于该第一黏胶30与该第一隔离涂层32间的弱黏着力，该第一载体31连同该第一隔离涂层32轻易地卸载。因此，该第一载体31从该半导体晶圆11卸载。然而，在其他实施例中，可导入该半导体晶圆11的切割工艺，以卸载该第一载体31。
参考图15，利用一紫外光（UV light）（如箭头38所示）照射该处理带36的第一表面361以降低该处理带36的黏着力。接着，附着一切割胶带40，例如UV胶带，至该半导体晶圆11的第一或下表面101。
参考图16，将该处理带36从该半导体晶圆11卸载，且该晶圆11的上表面（包含该等保护盖16）是显露。
参考图17，施加一第一激光42，例如一激光烧结机器（例如迪思科公司(DISCOcorporation)型号DFL7160）。该第一激光42聚焦于该钝化层12以移除部份该钝化层12，且形成数个沟槽123于该等晶圆切割线的附近。此一工艺为一激光烧结工艺（Laser Sintering Process）或一激光刻槽工艺（Laser Grooving Process），且进一步讨论如下。来自该第一激光42融化（Melt）且挥发（Evaporate）部份该钝化层12，以在其顶面形成一等离子体。随着该等离子体延伸至该该钝化层12内，越来越多材料被移除，且形成该沟槽123。在本实施例中，该等沟槽123是对应该等切割线（图中未示），且每一该等沟槽123的宽度小于每一该等切割线的宽度。
参考图18，其显示图17的局部放大图。如图所示，该沟槽123显露该半导体晶圆11的第二表面102的一部分。该钝化层12的侧面121与该半导体晶圆11的第二表面102之间形成一夹角θ。该第一激光42是用以移除部份该钝化层12，以确保该半导体晶圆11的第二表面102的平坦性。在本实施例中，该第一激光42是固定在特定波长，且不论较短或较长的脉冲宽度，该沟槽123皆会形成大于90度且小于115度的夹角θ。参考图19，其显示该钝化层12的沟槽123的另一实施例。如图所示，该第一激光42更移除该半导体晶圆11而形成一凹痕111，以确保位于该切割线的表面上的钝化层12实质上全部被移除。
参考图20，施加一第二激光44，例如一隐形激光切割机器（Laser Stealth DicingMachine）（例如迪思科公司(DISCO corporation)型号DFL7360）。该第二激光44的激光态样（Type of Laser）是不同于该第一激光42，且穿过该半导体晶圆11的显露第二表面102。该第二激光44聚焦于该半导体晶圆11的一内部分，以破坏该半导体晶圆11的材料的结晶结构。
具有可穿过该半导体晶圆11的波长的该第二激光44被一物镜聚集而聚焦于该半导体晶圆11内的一点。该第二激光44使用短脉冲在高重复率（Repetition Rate）振荡，且可高度聚集至衍射临限值（Diffraction Threshold Level）。该第二激光44不论在时间上或是空间上被压缩在光线聚焦点附近皆形成一超高尖峰功率密度（Peak Power Density）。当穿过该半导体晶圆11的该第二激光44在聚集过程中超过一尖峰功率密度，非线性吸收效应（Nonlinear Absorption Effect）会导致在局部点上发生超高吸收的现象。经由最佳化该第二激光44及光学系统特性以使该非线性吸收效应仅发生在该半导体晶圆11内的焦点附近，只有该半导体晶圆11内的局部点可以被选择性地激光加工而不伤害该半导体晶圆11内之前面及背面。亦即，此处所描述的隐形激光切割是使用可穿过欲切割的单晶硅半导体晶圆的波长，使得该激光光线可以被导引至该半导体晶圆11内激光加工焦点附近。因此，在切割线上具有高密度错位（High Density Dislocation）的多晶硅状态的退化层（Degeneration Layer）会产生压应力。
参考图21，施加一横向拉力（Lateral Tensile Force）（如箭头45所示）于该半导体晶圆11，例如利用该切割胶带40的手段，以将该晶圆11分割成数个如图1所示的半导体元件1。该半导体晶圆11被放在一放大装置（图中未示）。一横向拉力作用在附着于该放大装置的该半导体晶圆11。该半导体晶圆11沿着该等切割线被单体化（Singulated），因而被分割成该等个别半导体元件1。
为了使该等个别半导体元件1达到最佳良率，该隐形激光切割必须聚焦在该半导体晶圆11的结晶结构的正中央。因此，该半导体晶圆11的显露第二表面102的平坦度为重要的。然而，在本实施例中，该钝化层12是位于具有该至少一导电通道14的该半导体晶圆11的第二表面102，该第一激光42是用以移除部份该钝化层12以增加该半导体晶圆11的显露第二表面102的平坦度。再者，本实施例的切割工艺是使用激光而不使用刀具，因此不会导致该半导体晶圆11的崩坏，且适用于狭窄的切割道。
参考图22，显示本发明的另一实施例的半导体封装结构2的剖视示意图。该半导体封装结构2包括一下基板46、该半导体元件1、一上半导体元件48及一封胶材料50。该下基板46是例如一有机基板。该半导体元件1是与图1所示的该半导体元件1相同，且位于该下基板46上。
该上半导体元件48是位于该半导体元件1上，且其一表面上具有至少一上外部连接元件481。该保护盖16接触该上外部连接元件481，使得该上半导体元件48电性连接至该导电通道14。
该封胶材料50包覆该下基板46、该半导体元件1及该上半导体元件48。在本实施例中，该半导体封装结构2更包括一底胶52、一非导电胶54及数个焊球56。该底胶52是位于该半导体元件1及该下基板46之间，以保护该等外部连接元件22。该非导电胶54是位于该上半导体元件48及该半导体元件1之间。该等焊球56是位于该下基板46的下表面。
参考图23至图26，显示本发明的另一实施例的制造该半导体封装结构的半导体工艺的示意图。参考图23，提供一第三载体58及一下基板46。该下基板46是利用一黏胶层60附着至该第三载体58。
参考图24，选取该半导体元件1，且利用一接合头（Bonding Head）（图中未示）将该半导体元件1接合至该下基板46。形成一底胶52于该半导体元件1及该下基板46之间，以保护该等外部连接元件22。
参考图25，形成一非导电胶54于该钝化层12上，且堆迭该上半导体元件48于该半导体元件1上。此时，该保护盖16接触该上半导体元件48的一上外部连接元件481（例如焊球）。
参考图26，形成一封胶材料50以包覆该下基板46、该半导体元件1及该上半导体元件48。接着，移除该第三载体58及该黏胶层60，且形成数个焊球56于该下基板46的下表面。因此，制得如图22所示的该半导体封装结构2。
参考图27至图31，显示本发明的另一实施例的制造该半导体元件1的半导体工艺的示意图。以下所述的简化工艺的每小时产量（Unit Per Hour,UPH）会高于上述的工艺，且经由省略于该切割胶带40的再次设置步骤（Re-mount Step），良率可提高。本实施例是接续图8的步骤。
参考图27，施加一第一激光42，该第一激光42聚焦于该钝化层12以移除部份该钝化层12，且形成数个沟槽123。在本实施例中，该等沟槽123是对应该等切割线（图中未示），且每一该等沟槽123的宽度小于每一该等切割线的宽度。
参考图28，提供一第二载体。在本实施例中，该第二载体为一处理带36，其具有一第一表面361、一第二表面362及一位于该第二表面362的黏胶层（图中未示）。该处理带36的第二表面362是利用该黏胶层（图中未示）附着至该半导体晶圆11的第二表面102上，且该等保护盖16是埋置于该黏胶层（图中未示）中。
参考图29，该第一载体31及该第一黏胶30更浸于一溶剂（图中未示）（例如：加马丁内酯(Gamma-Butyrolactone,GBL)或丙二醇甲醚醋酸酯(Propylene glycolmethyl ether acetate,PGMEA)）中，部份该第一黏胶30被溶解，且显露出该第一隔离涂层32。接着，由于该第一黏胶30与该第一隔离涂层32间的弱黏着力，该第一载体31连同该第一隔离涂层32被卸载。因此，该第一载体31从该半导体晶圆11卸载。然而，在其他实施例中，可导入该半导体晶圆11的切割工艺，以卸载该第一载体31。
参考图30，沿着该沟槽123施加一第二激光44。该第二激光44是不同于该第一激光42，且穿过该处理带36及该半导体晶圆11的显露第二表面102。该第二激光44聚焦于该半导体晶圆11的一内部分，以破坏该半导体晶圆11的材料的结晶结构。在本实施例中，位于该沟槽123内的该半导体晶圆11的第二表面102在经过第一激光42处理后会较为平坦，因此，可确保该第二激光44的切割品质。
参考图31，施加一横向拉力45于该半导体晶圆11，以形成数个如图1所示的半导体元件1。
参考图32至图37，显示本发明的另一实施例的制造该半导体封装结构2的半导体工艺的示意图。本实施例是接续图27的步骤。参考图32，形成一非导电胶54于该钝化层12上，且堆迭数个上半导体元件48于该半导体元件1上。此时，该保护盖16接触该上半导体元件48的一上外部连接元件481（例如焊球）。
参考图33，提供一第二载体。在本实施例中，该第二载体为一处理带36，其具有一第一表面361、一第二表面362及一位于该第二表面362的黏胶层（图中未示）。该处理带36的第二表面362是利用该黏胶层（图中未示）附着至该半导体晶圆11的第二表面102上，且部份该等上半导体元件48是埋置于该黏胶层（图中未示）中。
参考图34，该第一载体31及该第一黏胶30更浸于一溶剂（图中未示）（例如：加马丁内酯(Gamma-Butyrolactone,GBL)或丙二醇甲醚醋酸酯(Propylene glycolmethyl ether acetate,PGMEA)）中，部份该第一黏胶30被溶解，且显露出该第一隔离涂层32。接着，由于该第一黏胶30与该第一隔离涂层32间的弱黏着力，该第一载体31连同该第一隔离涂层32被卸载。因此，该第一载体31从该半导体晶圆11卸载。然而，在其他实施例中，可导入该半导体晶圆11的切割工艺，以卸载该第一载体31。
参考图35，沿着该沟槽123施加一第二激光44。该第二激光44是不同于该第一激光42，且穿过该处理带36及该半导体晶圆11的显露第二表面102。该第二激光44聚焦于该半导体晶圆11的一内部分，以破坏该半导体晶圆11的材料的结晶结构。
然而，在其他实施例中，可附着一切割胶带（图中未示）至该半导体晶圆11的第一表面101。接着，将该处理带36从该半导体晶圆11卸载，使得该第二激光44直接穿过该半导体晶圆11的显露第二表面102，且聚焦于该半导体晶圆11的一内部分。在本实施例中，该半导体晶圆11的显露第二表面102在经过该第一激光42处理后会较为平坦，以确保良好的切割品质及高良率。
参考图36，施加一横向拉力（如箭头45所示）于该半导体晶圆11，以形成数个如图37所示的复合元件3。接着，选取该复合元件3，且利用一接合头（图中未示）将该复合元件3接合至该第三载体58上的该下基板46。形成一底胶52于该半导体元件1及该下基板46之间，以保护该等外部连接元件22。接着，形成一封胶材料50以包覆该下基板46及该复合元件3。接着，移除该第三载体58，且形成数个焊球56于该下基板46的下表面。因此，制得如图22所示的该半导体封装结构2。
惟上述实施例仅为说明本发明的原理及其功效，而非用以限制本发明。因此，习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如权利要求书所列。

Claims (20)

1.一种半导体元件，其特征在于，包括：
一晶粒；
至少一导电通道，形成于该晶粒中；
一钝化层，位于该晶粒的一背面的一部分，其中该导电通道凸出于该钝化层而形成一凸出端；及
一保护盖，位于该导电通道的该凸出端；
其中该钝化层具有一侧面，该侧面与该晶粒的该背面的一显露部份间的夹角大于90度，该显露部份是未被该钝化层所覆盖。
2.如权利要求1的半导体元件，其特征在于，该晶粒的该背面的该显露部份是位于沿着该晶粒的该背面的周围的位置。
3.如权利要求1的半导体元件，其特征在于，该晶粒的该背面的该显露部份具有一第一表面粗糙度，该钝化层的一上表面具有一第二表面粗糙度，该第一表面粗糙度实质上小于该第二表面粗糙度。
4.如权利要求3的半导体元件，其特征在于，该第一表面粗糙度为激光烧结的结果。
5.如权利要求3的半导体元件，其特征在于，该晶粒的一侧面具有一第一部份、一第二部份及一第三部份，该第一部份具有一第三表面粗糙度，该第二部份具有一第四表面粗糙度，且该第三部份具有一第五表面粗糙度；其中该第三表面粗糙度、该第四表面粗糙度及该第五表面粗糙度实质上不同。
6.如权利要求5的半导体元件，其特征在于，该第四表面粗糙度为隐形激光切割的结果。
7.如权利要求5的半导体元件，其特征在于，该第四表面粗糙度是大于该第一表面粗糙度至少50倍。
8.如权利要求5的半导体元件，其特征在于，该第三表面粗糙度大于该第一表面粗糙度，且该第五表面粗糙度大于该第一表面粗糙度。
9.一种半导体封装结构，其特征在于，包括：
一基板；
一第一半导体元件，位于该基板上，且包括：
一晶粒；
至少一导电通道，形成于该晶粒中；
一钝化层，位于该晶粒的一背面的一部分，其中该导电通道凸出于该钝化层而形成一凸出端；及
一保护盖，位于该导电通道的该凸出端；
其中该钝化层具有一缺口部份，沿着该钝化层的周围，且该钝化层的一侧面与该晶粒的该背面形成的夹角为90度至115度；
一第二半导体元件，位于该第一半导体元件上且电性连接至该导电通道；及
一封胶材料，包覆该基板、该第一半导体元件及该第二半导体元件。
10.如权利要求9的半导体封装结构，其特征在于，该保护盖包括一晶种层、位于该晶种层上的一铜层、位于该铜层上的一镍层、位于该镍层上的一钯层及位于该钯层上的一金层。
11.如权利要求9的半导体封装结构，其特征在于，该保护盖包括一晶种层、位于该晶种层上的一铜层、位于该铜层上的一镍层及位于该镍层上的一锡/银合金或一金层。
12.如权利要求9的半导体封装结构，其特征在于，该晶粒的该背面的未被该钝化层所覆盖的一部份具有一第一表面粗糙度，且该钝化层的一上表面具有一第二表面粗糙度，该第一表面粗糙度实质上小于该第二表面粗糙度。
13.如权利要求12的的半导体封装结构，其特征在于，该第一表面粗糙度为激光烧结的结果。
14.如权利要求12的半导体封装结构，其特征在于，该晶粒的一侧面具有一第一部份、一第二部份及一第三部份，该第一部份具有一第三表面粗糙度，该第二部份具有一第四表面粗糙度，且该第三部份具有一第五表面粗糙度，其中该第三表面粗糙度、该第四表面粗糙度及该第五表面粗糙度实质上不同。
15.如权利要求14的半导体封装结构，其特征在于，该第四表面粗糙度为隐形激光切割的结果。
16.如权利要求14的半导体封装结构，其特征在于，该第四表面粗糙度是大于该第一表面粗糙度至少50倍。
17.一种切割半导体晶圆的方法，其特征在于，包括：
提供一半导体晶圆，该半导体晶圆具有一第一表面、一第二表面及一钝化层，其中该钝化层是位于该第二表面；
施加一第一激光于该钝化层以移除该钝化层的一部分且显露该半导体晶圆的一部分；
施加一第二激光，其中该第二激光穿过该半导体晶圆的该第二表面且聚焦于该半导体晶圆的一内部分；及
施加一横向力于该半导体晶圆。
18.如权利要求17的方法，其特征在于，提供该半导体晶圆的步骤包括：
提供该半导体晶圆，该半导体晶圆具有该第一表面、该第二表面及至少一导电通道，其中该导电通道是位于该半导体晶圆中；
附着一第一载体至该半导体晶圆的该第一表面；
从该第二表面移除部份该半导体晶圆，以显露该至少一导电通道的末端；
以该钝化层覆盖所述显露的末端：及
薄化该钝化层使得所述末端凸出于该钝化层。
19.如权利要求18的方法，其特征在于，更包括形成一保护盖至每一末端。
20.如权利要求18的方法，其特征在于，该第一激光的激光态样是不同于该第二激光。
CN201310452834.1A 2012-11-14 2013-09-27 切割具有硅穿通道的半导体晶圆的方法及其所形成的结构 Active CN103811458B (zh)

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