TWI395269B - 以ｈａｒｐii 處理固化烷氧矽烷前驅物沉積之二氧化矽薄膜的方法 - Google Patents

以ｈａｒｐii 處理固化烷氧矽烷前驅物沉積之二氧化矽薄膜的方法 Download PDF

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TWI395269B
TWI395269B TW097132417A TW97132417A TWI395269B TW I395269 B TWI395269 B TW I395269B TW 097132417 A TW097132417 A TW 097132417A TW 97132417 A TW97132417 A TW 97132417A TW I395269 B TWI395269 B TW I395269B
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oxide layer
ruthenium oxide
vapor
substrate
processing chamber
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Abhijit Basu Mallick
Srinivas D Nemani
Timothy W Weidman
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Applied Materials Inc
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Description

以HARP II處理固化烷氧矽烷前驅物沉積之二氧化矽薄膜的方法 【交互參照之相關申請案】
本申請案是關於共同讓渡之美國專利申請案：代理人文件編號A010498/T6950OY，由Ingle等人提出且名稱為「使用含矽前驅物和氧原子來化學氣相沉積高品質之流式二氧化矽(CHEMICAL VAPOR DEPOSITION OF HIGH QUALITY FLOW－LIKE SILICON DIOXIDE USING A SILICON CONTAINING PRECURSOR AND ATOMIC OXYGEN)」，於西元2006年5月30日申請。本申請案亦有關於共同讓渡之美國專利申請案：代理人文件編號為A11125/T79600，由Munro等人提出且名稱為「化學處理以改善氧化物膜的品質(CHEMICAL TREATMENTS FOR IMPROVEMENT OF OXIDE FILM QUALITY)」。本申請案另關於共同讓渡之美國專利申請案：代理人文件編號A11161/T78800，由Mallick等人提出且名稱為「利用遠端電漿化學氣相沉積二矽烷前驅物以得高品質之二氧化矽膜(HIGH QUALITY SILICON OXIDE FILMS BY REMOTE PLASMA CVD FROM DISILANE PRECURSORS)」。這些相關申請案將一併引用供作參考。
本發明有關於利用HARP II來固化以烷氧矽烷前驅物所沉積之二氧化矽膜的方法。
諸如淺溝槽隔離結構(STI)等間隙和溝槽常用來電性隔離半導體裝置上的元件。STI可能包含形成在半導體基材的隔離區中溝槽或間隙，並且在溝槽或間隙中填入介電材料，以防止電性耦接至附近的裝置結構，如電晶體、二極體等。隨著積體電路上的裝置密度持續增加，裝置結構的尺寸和間距亦不斷縮小。然STI的縱向高度一般不會像橫向寬度般地縮減那麼快，以致於間隙和溝槽之高度對寬度的比例變大(即深寬比變大)。
雖然提高裝置結構的深寬比可在半導體晶片基材的相同表面積上設置更多的結構(如電晶體、電容器、二極體等)，但會帶來製造上的問題。問題之一在於，進行填充時難以完全填滿這些結構中的間隙和溝槽，又不產生空隙或裂縫。必須使用如二氧化矽等介電材料來填充間隙和溝槽，將相鄰的裝置結構彼此電性隔離開來，以減少電氣干擾和漏電電流。然隨著深寬比增加，要填充既深又窄的溝槽，又不會在填充溝槽的介電材料中產生空隙或裂縫的工作變得越來越困難。
介電層中的空隙和裂縫會對半導體裝置製造期間及所完成裝置造成問題。空隙和裂縫是隨機形成在介電層中的，並且具有無法預測的尺寸、形狀、位置和密度。此將導致無法預期且不一致的沉積後(post－deposition)處理結果，例如不均勻的蝕刻、研磨、退火等。所完成裝置內的空隙與裂縫也會使裝置結構中之間隙和溝槽的介電品質變 異。使得裝置內產生電氣相互干擾、漏電、甚至短路，導致裝置性能不穩定且較差，或引起其他問題。
已開發多種技術來減少沉積介電材料於高深寬比結構中時所形成的空隙和裂縫。包括減慢介電材料的沉積速率，使介電材料更共形地停留在溝槽的側壁與底面。更共形地沉積可減少材料累積在溝槽的頂部，以減少介電材料過早封住溝槽頂部而形成空隙(此問題有時稱為「麵包塊現象(breadloafing)」)的機率。然而減慢沉積速率代表沉積時間增長，因而降低處理效率和生產速率。
另一控制空隙形成的技術是增進沉積之介電材料的流動性。流動性較佳的材料可較快填入空隙或裂縫中，避免空隙或裂縫變成填充空間中的永久性缺陷。例如，高流動性旋塗玻璃(SOG)前驅物，如聚矽氮烷(polysilazanes，PSZ)、氫化聚倍半矽氧烷(hydrosisesquioxanes，HSQ)等等，通常用來填充溝槽且具有良好共形性。然而利用傳統SOG膜來提高氧化矽介電材料的流動性常會因為殘留有碳與矽醇基(silanol groups)，使得剛沉積的膜層具有低密度。增加膜密度的其中一種方法為，進行高溫退火將SOG膜固化成氧化矽膜。然而使用高溫退火來移除殘留碳與OH基亦可能會縮小一定程度的膜體積。對STI的窄溝槽應用來說，剛沉積膜的已受限制且不能再縮小，因而易形成具有多孔或含空隙之結構的低密度膜。
因此，仍然需要一種可提升高深寬比之溝槽、間隙和其他裝置結構中之介電膜品質、同時達到無空隙填充的方 法。本發明將提出這些與其他介電膜沉積態樣。
本發明之實施例包括固化基材上之氧化矽層的方法。該方法包括提供半導體處理室和基材，以及形成氧化矽層於至少一部分的基材上。氧化矽層可能包括形成膜層時產生的碳物種副產物。該方法還包括引入一酸性蒸氣至半導體處理室中，酸性蒸氣與氧化矽層反應而從氧化矽層移除碳物種。該方法亦包括移除半導體處理室內的酸性蒸氣。
本發明實施例還包括形成氧化矽層於基材上的方法。該方法包括提供半導體處理室和基材，以及在基材內形成溝槽。該方法還包括沉積第一氧化矽層來部分填充溝槽，以及藉由引入酸性蒸氣至半導體處理室中來固化第一氧化矽層，酸性蒸氣與第一氧化矽層反應而從第一氧化矽層移除碳物種。另外，該方法還包括沉積第二氧化矽層於第一氧化矽層上，第二氧化矽層實質填充溝槽，以及退火處理第一和第二氧化矽層。
本發明實施例更包括形成氧化矽層於基材上的方法。該方法包括(a)提供基材和半導體處理室，以及(b)在基材內形成溝槽。該方法還包括(c)沉積氧化矽層於溝槽中，以及(d)藉由引入酸性蒸氣至半導體處理室來固化氧化矽層，酸性蒸氣與氧化矽層反應而從氧化矽層移除碳物種。該方法尚包括(e)反覆進行步驟(c)及(d)，直到溝槽內形成期望厚度的氧化矽層，以及(f)退火處理氧化矽層。
其他實施例和特徵將部分說明於下，且在熟請此技藝者檢閱說明書或實踐本發明後將更顯得清楚易懂。藉由說明書所述之手段、組合和方法可理解及達到本發明的特徵與優點。
本文描述利用酸性催化劑(acidic catalyst)來固化高流動性矽層使剛沉積的膜層完成反應的系統和方法。以酸性催化劑來固化剛沉積之矽層，可移除矽層中不想要的殘留物種，例如矽層沉積製程中未反應的碳基副產物。催化劑可幫助剛沉積的膜層完全反應，而有助於移除未反應的碳基。固化製程可密實(densify)氧化矽膜，而改善濕蝕刻比及間隙填充高深寬比溝槽的能力。
本發明之方法包括產生酸性催化劑使其成為酸性水蒸氣。酸性催化劑可以氣體形態(如氯化氫(HCl)直接引入半導體處理室中，或者利用如氯矽氧烷(chloro－siloxane)或乙醯氧矽氧烷(acetoxy－siloxane)等不同前驅物於原位產生酸性催化劑。半導體處理室內添加酸可於低溫下催化沉積層中任何未反應的有機基團(organic moieties)進行反應，進而在膜層完全固化之前密實該膜層。隨後可進行高溫退火製程來完全密實膜層。
第1A至1B圖為根據本發明一實施例之用於間隙填充沉積製程的簡化截面示範圖。例如，第1A至1B圖可配合參照第2圖，第2圖為根據本發明一實施例之固化處理氧 化矽的方法流程圖。方法200包括首先在步驟202中提供半導體處理室(未繪示)和基材100。基材100可為半導體晶圓，如200毫米(mm)、300mm、400mm等矽晶圓，且可包括先前製程形成的結構、裝置部件等。此外，基材可包括具有高深寬比之間隙、溝槽等，例如深寬比為5：1或以上、6：1或以上、7：1或以上、8：1或以上、9：1或以上、10：1或以上、11：1或以上、12：1或以上等。例如，基材100包括具有側壁106與底面108的溝槽104。
方法200還包括在步驟204中，形成氧化矽層102於至少一部分的基材100上。例如，可採取流式(flow－like)CVD法及使用有機矽酸鹽(organosilicate)前驅物110與氧原子前驅物112來沉積氧化矽層102至溝槽104，其描述於共同讓渡之美國專利申請案：Ingle等人提出、名稱為「使用含矽前驅物和氧原子來化學氣相沉積高品質之流式二氧化矽(CHEMICAL VAPOR DEPOSITION OF HIGH QUALITY FLOW－LIKE SILICON DIOXIDE USING A SILICON CONTAINING PRECURSOR AND ATOMIC OXYGEN)」申請於西元2006年5月30日。或者，可利用遠端電漿CVD製程將流動性介電層中的Si－Si鍵結轉換成Si－NH－Si鍵結，並且於沉積後的蒸氣退火處理期間發展成Si－O－Si鍵結以密實膜層，此描述於共同讓渡之美國專利申請案：Mallick等人提出、名稱為「利用遠端電漿化學氣相沉積二矽烷前驅物以得高品質之二氧化矽膜(HIGH QUALITY SILICON OXIDE FILMS BY REMOTE PLASMA CVD FROM DISILANE PRECURSORS)」。但也可採用其他傳統的氧化矽層沉積方法，例如旋塗法、次大氣壓化學氣相沉積(SACVD)和高密度電漿化學氣相沈積(HDP－CVD)。在本發明一特定實施例中，方法200可用於STI應用。例如，形成氧化矽層102實質覆蓋住溝槽104的側壁106和底面108，並且可持續以部分填充溝槽104或直到到完全填滿及超過溝槽104。因此，氧化矽層102覆蓋至少一部分的基材100。
在該形成步驟204中，氧化矽層102完全填充至少一部分的溝槽104且沒有形成空隙或裂縫。然而採用流動性沉積步驟204會產生過度孔化(too porous)的膜層，因而未達適當的機械強度。故在步驟206中，需加入酸性蒸氣至處理室來處理氧化矽層102。
在一特定實施例中，引用酸性水蒸氣的方法有二種：一是將含有矽氧烷前驅物(siloxane precursor)的稀釋氯化氫(HCl)氣體直接引進腔室內，或者分別使用氯矽氧烷或乙醯氧矽氧烷原位生成HCl或乙酸(CH3 COOH)。可用於產生HCl的氯矽氧烷包括二氯二乙氧基矽氧烷(dichlorodiethoxysilane，DCDES)和氯三乙氧基矽氧烷(chlorotriethoxysilane，CTES)。CH3 COOH可由例如二乙醯氧二叔丁基矽烷等乙醯氧矽氧烷產生。當然，熟諳此技藝者也可採行其他方法來引入酸性蒸氣或使用不同的前驅物或酸。可用來控制化學反應的各種製程變數包括水：酸的比例、壓力、溫度以及酸性蒸氣接觸氧化矽層的時間。 例如，使用酸與水組成之蒸氣比使用純酸組成的蒸氣更有效。另外，水：酸的比例可為100：1至1：100，壓力可為10毫托耳至大氣壓。酸處理製程的溫度可為20℃至600℃。接觸時間可從短到1秒至24小時。
引入半導體處理室後，在步驟208中，酸性蒸氣與氧化矽層102反應。儘管不欲結合特定理論，但相信添加酸有助於催化該些在沉積時未反應的有機基團進行反應。例如，酸性環境可催化從氧化矽層102中移除有機物種(CH)。例如，第3圖繪示根據本發明一實施例從剛沉積之介電層中移除碳基物種的酸催化作用。圖式僅為舉例說明，而非用來限定所欲保護之範圍。該領域中具有通常知識者將可理解其他的變化、潤飾和替換實例。若處理過程加入酸性蒸氣，則未反應之羥基(hydroxyl group)將遭受酸的親電攻擊，也就是來自酸的H＋ 離子藉著取走氧原子的一個電子給氫原子而將未反應之CH3 O基轉換成反應性CH3 OH基。此繪示於第3圖的步驟310。如步驟320所示，水蒸氣接著與反應性CH3 OH基反應。在步驟330中，該反應產生矽醇基(Si－OH)並釋出醇分子(CH3 OH)。在步驟340中，矽醇基(Si－OH)進行縮合反應(也就是二個矽醇基(Si－OH)結合而釋出水)而於氧化矽膜中形成網絡。在一實施例中，酸處理有助於移除碳物種而提高膜密度，並且降低因失去羥基而形成空隙的可能性。當然，還有其他變化、潤飾和替換實例。
如第1B圖所示，當完成氧化矽層內未完成的化學反 應且膜層緻密化之後，經過處理的氧化矽層102會稍微收縮。在步驟210中，自半導體處理室中移除酸性蒸氣114。可利用與半導體處理室整合在一起或獨立的幫浦機制移除蒸氣。處理後的膜層是非多孔性的、密實且機械強度比剛沉積的膜層要佳。如此可得高品質的氧化矽層，同時保有持用來填充高深寬比間隙所需的流動性。
第4圖為根據本發明一實施例，使用酸性催化劑對水解速率之影響的曲線圖。儘管不欲結合特定理論，咸信添加酸性催化劑至氧化矽層能加快水解速率，進而增加Si－O－Si的聯結量及改善膜層品質。
第5圖為根據本發明一實施例之用於間隙填充沉積的方法流程圖。方法400包括前述第2圖中類似的步驟，此部分不再贅述。在步驟402中，提供半導體處理室和基材。基材可為半導體晶圓(如200mm、300mm、400mm等矽晶圓)，且可包括較早製程所形成的結構、裝置部件等。在步驟404中，利用傳統製程於基材內形成溝槽。例如，形成的溝槽可用於淺溝槽隔離或熟諳此技藝者所知的其他製程。在步驟406中，沉積第一氧化矽層至溝槽內以部分填充溝槽。第一氧化矽層可利用前述流動性沉積製程或傳統製程沉積而得。沉積後，在步驟408中，引導酸性水蒸氣至半導體處理室中，藉以固化第一氧化矽層。蒸氣與氧化矽層反應，而催化在沉積時未反應之有機基團進行反應。在步驟410中，沉積第二氧化矽層於第一氧化矽層上。例如，利用流動性沉積製程以第二氧化矽層來實質填滿該被 第一氧化矽層部分填充的溝槽。第6圖為根據本發明一示範實施例完成間隙填充沉積的截面示意圖。在第6圖中，進行一次或多次沉積及處理後，氧化矽層422完全填滿溝槽416。
流動性沉積製程可沉積無定形層，因其分子骨架中存有羥基，故其具有流動特性。在一實施例中，方法400更包括在步驟412中，於氧化環境下退火該些沉積層，以形成密實的氧化矽層。一旦經高溫退火，沉積層中含有殘餘碳之羥基和OH基將反應而分解成水及/或醇蒸氣，且立刻抽出水和/或醇蒸氣，因而有效收縮及密實膜層。在一特定實施例中，退火步驟412是在水蒸氣(steam，water vaper)氛圍之氧化環境下進行的熱退火製程。例如，可在約200℃至約1050℃的基材溫度且下進行水蒸氣退火處理，且蒸氣壓為約1托耳至約760托耳。在另一實施例中，退火步驟412為臭氧處理，且基材溫度從室溫至600℃。臭氧處理更可配合紫外光(UV)照射。在又一實施例中，退火步驟412為膜固化製程，其涉及從室溫至900℃的氧分子處理，或從室溫至600℃的氧原子處理。當然，熟諳此技藝者可理解其他變化、潤飾和替換實例。
第7圖為根據本發明一實施例，沉積層在酸處理前、酸處理後和退火處理後的FTIR比較圖。縱軸表示光吸收(吸收度)的對數，橫軸為光通過樣品材料的波數(1/波長)。例如，吸收光譜500、502、504分別對應處理前的剛沉積矽層、處理後的沉積矽層和退火後的沉積矽層。對於剛沉 積之膜層的吸收光譜500中，於3400和2900附近出現二個吸收度尖峰，表示沉積層內仍存有SiOH和CHx 分子。如吸收光譜502所示，添加酸來催化，可有效移除2900附近的有機物種。處理後的沉積矽層內仍存有SiOH，但接著經退火處理之後，可有效移除吸收光譜中在3400附近的尖峰，此形成具有Si－O－Si聯結的高品質氧化矽層。
第8圖為根據本發明另一實施例之用於間隙填充沉積的方法流程圖。方法600包括前述第2及5圖中類似的步驟，此部分不再贅述。在步驟602中，提供半導體處理室和基材。基材可為半導體晶圓(如200mm、300mm、400mm等矽晶圓)，且可包括先前製程形成的結構、裝置部件等。在步驟604中，利用傳統製程於基材內形成溝槽。例如，所形成之溝槽可用於淺溝槽隔離或熟諳此技藝者所知的其他製程。在步驟606中，沉積氧化矽層至溝槽內以部分填充溝槽。例如，氧化矽層的厚度為5至500埃()。該氧化矽層可利用前述流動性沉積製程或傳統製程沉積而得。沉積後，在步驟608中，將酸性水蒸氣引入半導體處理室，藉以固化氧化矽層。蒸氣與氧化矽層反應而催化該些在沉積時未反應的有機基團進行反應。固化後，在步驟610中，測定氧化矽層是否達到預定厚度。若否，則反覆進行沉積和處理循環，直到達到目標厚度。隨後在步驟612中，退火處理氧化矽層以密實膜層。
應理解的是，第1至5圖繪示與說明的示範方法僅為根據本發明來固化基材上之氧化矽層的其中一部分實施 例。其他實施例可包括額外步驟和不同的步驟順序來處理或沉積氧化物層。在本發明一特定實施例中，半導體處理室可由不同途徑輸送不同的液態前驅物。如此允許在沉積氧化矽層後，緊接著在單一處理室內進行處理製程。用於施行方法200的處理室實例將配合第9及10圖說明於下。
示例之基材處理系統
可用於本發明實施例的沉積系統包括高密度電漿化學氣相沉積(HDP－CVD)系統、電漿增強化學氣相沉積(PECVD)系統、次大氣壓化學氣相沉積(SACVD)系統、熱化學氣相沉積系統，和其他類型的系統等。可用於本發明實施例的CVD系統實例包括CENTURA ULTIMATM HDP－CVD室/系統和PRODUCERTM PECVD室/系統，其皆可取自美國加州聖克拉拉市之應用材料公司(Applied Materials,Inc.)。
經修改並適用於本發明實施例的基材處理系統描述於共同讓渡之美國專利證書號6,387,207與6,830,624，其均一併引用供作參考。第9圖繪示CVD系統10的垂直剖面，包括具有腔室壁面15a和腔室蓋組件15b的真空室或處理室15。
CVD系統10包含氣體分配歧管11，用以將製程氣體分散至放置在處理室15中央處之加熱基座12上的基材(未繪示)。氣體分配歧管11可由導電材料組成，以做為形成電容電漿的電極。處理時，基材(如半導體晶圓)置於基座12的平坦(或些微凸起)表面12a上。可控制基座12而在較低的裝載/卸載位置(如第9圖所示)與鄰近歧管11的較高 處理位置(以第9圖的虛線14表示)之間移動。中央板(未繪示)包括感測器，用以提供晶圓位置的資訊。
沉積氣體和載氣通過傳統平面圓形氣體分配面板13a的穿孔13b引入處理室15中。特別是，沉積製程氣體經由入口歧管11、傳統穿孔阻隔板42和氣體分配面板13a的穿孔13b流入反應室。
到達歧管11之前，沉積氣體與載氣自氣源7經由氣體供應管線8輸入到混合系統9中，沉積氣體與載氣在此處混合後再輸送到歧管11。各製程氣體的供應管線一般包括(i)數個安全關閉閥(未繪示)，其可用來自動或手動停止製程氣體流入反應室，及(ii)流量控制器(亦未繪示)，用以測量氣體流經供應管線的流量。若製程使用有毒氣體，則按傳統配置將數個安全關閉閥設在各氣體供應管線上。
CVD系統10執行的沉積製程可為熱製程或電漿增強製程。就電漿增強製程而言，RF功率供應器44施加電力於氣體分配面板13a與基座12之間，藉以激發製程混合氣體，而在面板13a與基座12之間的圓柱形區域中形成電漿。此區域在此亦指「反應區域」。電漿的組成物會反應，而基座12上的半導體晶圓表面沉積一期望膜層。RF功率供應器44為混頻射頻(RF)功率供應器，其一般以13.56MHz之RF高頻(RF1)與360kHz之RF低頻(RF2)供電，來促進引入真空室15中的反應種類分解。就熱製程而言，則不採用RF功率供應器44，且製程氣體混合物將進行熱反應而在基座12上的半導體晶圓表面沉積期望膜 層，基座12為阻抗式加熱來提供反應熱能。
電漿增強沉積製程期間，電漿加熱整個處理室15，包括圍住排氣通道23與關閉閥24的腔室主體壁面15a。當電漿未開啟或進行熱沉積製程時，熱液體循環遍及處理室15的壁面15a，以保持腔室的升溫狀態。壁面15a中的其他通道則未繪示。用來加熱腔室壁面15a的流體包括典型的流體類型，也就是水系的乙二醇，或以油系的熱傳流體。此加熱方式(指藉由「熱交換」加熱)可大幅減少或消除不當的反應產物凝結，並有助於減少製程氣體與其他污染物的揮發性產物，倘若這些產物凝結在冷的真空通道壁面且在沒有氣流時流回處理室中，可能會污染製程。
其餘未沉積成膜層的氣體混合物(包括反應副產物)由真空幫浦(未繪示)排出處理室15。特別是，氣體經由圍繞反應區域的環狀狹長孔16排放到環狀排放氣室17。環狀狹長孔16和氣室17由圓柱形壁面15a頂部(包括壁面上的上介電內襯19)與圓形腔室蓋20底部之間的間隙所定義而成。360度環行對稱且均勻配置的狹長孔16和氣室17可讓製程氣體均勻流到晶圓上方，而於晶圓上沉積出均勻的膜層。
離開排放氣室17後，氣體流經排放氣室17的側向延伸部21下方、經過視窗口(未繪示)，並流過向下延伸的氣體通道23、通過真空關閉閥24(其主體與下腔室壁面15a整合)，而流入透過前置管線(foreline，未繪示)連接外部真空幫浦(未繪示)的排放出口25。
基座12的晶圓支撐盤(較佳為鋁、陶瓷或其組合物)利用埋設型加熱元件的單一迴圈來進行阻抗式加熱，其以平行同心圓形式排列成完整兩圈。加熱元件的外部毗鄰支撐盤周圍延伸，加熱元件的內部則沿著半徑較小的同心圓延伸。加熱元件的接線通過基座12的主幹(stem)。
一般來說，任一或所有的腔室內襯、氣體入口歧管面板，和各種反應器硬體是由諸如鋁、陽極鋁(或稱電鍍鋁，anodized aluminum)或陶瓷構成。此類CVD設備的例子描述於共同讓渡之美國專利證書號5,558,717、名稱為「CVD處理室(CVD PROCESSING CHAMBER)」、且授予Zhao等人的專利中，其全文一併引用供作參考。
當機械手刀刃(未繪示)經由系統10側邊的插入/移出開口26傳送晶圓進出腔室15的主體時，升降機構與馬達32(第9圖)會抬高及降低加熱基座12和其晶圓舉升銷12b。馬達32在處理位置14與較低的晶圓裝載位置之間抬起及降下基座12。馬達、連接供應管線8的閥或流量控制器、氣體輸送系統、節流閥、RF功率供應器44、和腔室與基材加熱系統全透過控制線路36而受控於系統控制器，圖中僅顯示部分。控制器34依據光學感測器的反饋訊號判別可動式機械組件的位置，例如節流閥和基座(susceptor)，在控制器34的控制下利用適當的馬達移動這些機械組件。
在此實施例中，系統控制器包括硬碟機(記憶體38)、軟碟機和處理器37。處理器含有單板電腦(SBC)、類比與 數位輸入/輸出板、介面板和步進馬達控制板。CVD系統10的各種零件皆符合用來規範板、卡籠和連接器尺寸與種類的Versa Modular European(VME)標準。VME標準尚訂定具有16位元資料匯流排與24位元位址匯流排的匯流排結構。
系統控制器34控制CVD機器的所有動作。系統控制器執行系統控制軟體，其為儲存於電腦可讀取媒體(如記憶體38)中的電腦程式。較佳地，記憶體38為硬碟機，但記憶體38也可為其他類型的記憶體。電腦程式包括用來指示特定製程之時序、混合氣體、腔室壓力、腔室溫度、RF功率大小、基座位置和其他參數的指令集。其他儲存於它種記憶體裝置(例如包括軟碟或其他適合的驅動器)上的電腦程式亦可用來操作控制器34。
用來在基材上沉積膜層的製程或用來清潔腔室15的製程，可實施成由控制器34執行的電腦程式產品。可以任一傳統電腦可讀取程式語言編寫電腦程式碼，例如68000組合語言、C、C＋＋、Pascal、Fortran或其他語言。適當的程式碼乃利用傳統文字編輯器輸入單一檔案或多個檔案，並儲存或收錄在電腦可用媒體中，如電腦的記憶系統。若輸入的編碼文字為高階語言，該些編碼則需進行編譯，產生的編譯程序碼接著連結預先編譯之WindowsTM 書庫例行程序的目的碼。為執行該些已連結且已編譯之目的碼，系統使用者利用目的碼，使電腦系統載入記憶體中的編碼。隨後CPU讀取並執行該些編碼，以執行在程式中識別的任 務。
如第10圖所示，使用者與控制器34之間的介面為CRT螢幕50a和光筆50b；第10圖為基材處理系統之系統監視器和CVD系統10的簡化示意圖，其可包括一個或多個腔室。在一較佳實施例中採用兩個螢幕50a，其中一個放置於無塵室壁面供操作員使用，另一個放置於壁面後方供維修技師使用。該些螢幕50a同時顯示相同的資訊，但只有一個光筆50b。光筆50b利用筆尖的感光器偵測CRT顯示器發射的光線。為選擇特定畫面或功能，操作員觸碰顯示畫面的指定區域，並按壓光筆50b上的按鈕。觸碰區域改變其亮度、或顯示新的選單或畫面，以確定光筆與顯示畫面的溝通無礙。亦可額外使用或代替光筆50b使用其他諸如鍵盤、滑鼠或其他點擊或通信裝置等輸入裝置來聯繫使用者與處理器34。
第9圖顯示裝設於處理室15之蓋組件15b上的遠端電漿產生器60，處理室15包括氣體分配面板13a和氣體分配歧管11。最佳如第9圖所示，架設轉接器64將遠端電漿產生器60裝設在蓋組件15b上。轉接器64通常由金屬構成。混合裝置70耦接於氣體分配歧管11的上游處(第9圖)。混合裝置70包括位於混合塊件之狹縫74內的混合插入件72，用以混合製程氣體。陶瓷隔絕件66放置在架設轉接器64與混合裝置70之間(第9圖)。陶瓷隔絕件66可由陶瓷材料組成，例如氧化鋁(Al2 O3 )(純度99%)、Teflon等。安裝時，混合裝置70和陶瓷隔絕件66可構成部分的 蓋組件15b。隔絕件66隔開金屬轉接器64和混合裝置70與氣體分配歧管11，以減少蓋組件15b中形成二次電漿，此將進一步詳述於下。三向閥77控制製程氣體直接或經由遠端電漿產生器60流入處理室15。
遠端電漿產生器60較佳為精巧、獨立的單元，其便於裝設在蓋組件15b上，又不費時費工即可更新安裝至現有腔室。適合的單元之一為ASTRON產生器，其可取自美國麻薩諸塞州Woburn的應用科技公司(Applied Science and Technology,Inc.)。ASTRON產生器利用低場超環面電漿來解離製程氣體。在一實施例中，電漿解離製程氣體(包括如NF3 等含氟氣體)和如氬氣等載氣，以產生自由氟離子來清潔處理室15的沉積物。
根據上述數個實施例，熟諳此技藝者將可理解，各種潤飾、更動和均等物皆不脫離本發明之精神與範圍。例如，另行處理沉積介電層(如氧化矽層)的方法可配合(或代替)酸性蒸氣處理。這些方法包括熱退火、UV固化、以水蒸氣進行UV固化、電漿固化(如感應耦合電漿固化)、電子束固化或其他技術。此外，未提及一些熟知的製程和元件，是為了避免不必要的模糊掉本發明。因此，以上說明不應用來限制本發明之保護範圍。
應理解除非內文特別指明，否則文中所提供之數值範圍，亦明確揭露出介於該範圍上限與下限之間的各個中間值，到下限單位的十分之一。論述範圍內介於任一論述值或中間值與其他論述值或中間值之間的較小範圍也包含在 內。較小範圍的上限與下限可各自涵蓋在此範圍內或排除在外，且本發明亦包含每一種含較小範圍之上限及/或下限的範圍，取決於論述範圍中是否有特別排除的限值。當論述範圍包括上下限值其中一個或二者時，排除這些上下限值的範圍亦包含在本發明中。
除非內文另清楚指明，否則文中和後附申請專利範圍使用的單數形式(「一」與「該」)包括複數意涵。例如，指稱之「一製程」包括複數個此類製程，「該前驅物」包括一或多個前驅物和熟諳此技藝者所知的均等物等。
再者，本說明書和以下申請專利範圍採用的「包含」與「包括」等字詞意指存有所述之特徵、整體、元件或步驟，但並不排除另有一個或多個其他特徵、整體、元件、步驟、動作或群組。
7‧‧‧氣源
8‧‧‧管線
9‧‧‧混合系統
10‧‧‧系統
11‧‧‧歧管
12‧‧‧基座
12a‧‧‧表面
12b‧‧‧舉升銷
13a‧‧‧面板
13b‧‧‧穿孔
14‧‧‧虛線/處理位置
15‧‧‧真空室/處理室/腔室
15a‧‧‧壁面
15b‧‧‧蓋組件
16‧‧‧狹長孔
17‧‧‧氣室
19‧‧‧內襯
20‧‧‧腔室蓋
21‧‧‧延伸部
23‧‧‧通道
24‧‧‧關閉閥
25‧‧‧出口
26‧‧‧開口
32‧‧‧馬達
34‧‧‧控制器
36‧‧‧線路
37‧‧‧處理器
38‧‧‧記憶體
42‧‧‧阻隔板
44‧‧‧功率供應器
50a‧‧‧螢幕
50b‧‧‧光筆
60‧‧‧產生器
64‧‧‧轉接器
66‧‧‧隔絕件
70‧‧‧混合裝置
72‧‧‧插入件
74‧‧‧狹縫
77‧‧‧三向閥
100‧‧‧基材
102、422‧‧‧氧化矽層
104、416‧‧‧溝槽
106‧‧‧側壁
108‧‧‧底面
110、112‧‧‧前驅物
114‧‧‧蒸氣
200、400、600‧‧‧方法
202、204、206、208、210、310、320、330、340、402、404、406、408、410、412、602、604、606、608、610、612‧‧‧步驟
500、502、504‧‧‧光譜
本發明之本質和優點在參閱說明書其餘部分與所附圖式後將更明顯易懂，其中，各圖式中相同的元件符號表示類似的元件。在某些例子中，元件符號附帶的下標與連字號代表多個類似元件的其中一個。若文中指稱元件符號，而非特定指出現有之下標，則表示其是指所有此類的類似元件。
第1A與1B圖為根據本發明一實施例之用於間隙填充沉積的製程截面示意圖；第2圖為根據本發明一實施例之固化處理氧化矽的方 法流程圖；第3圖繪示根據本發明一實施例，用來移除剛沉積介電膜中之碳基物種的酸催化作用；第4圖為根據本發明一實施例，使用酸性催化劑對水解速率之影響的曲線圖；第5圖為根據本發明一實施例之用於間隙填充沉積的方法流程圖；第6圖為根據本發明一實施例完成間隙填充沉積的截面示意圖；第7圖為根據本發明一實施例，顯示沉積膜在酸處理前、酸處理後和退火處理後的FTIR比較圖；第8圖為根據本發明另一實施例之用於間隙填充沉積的方法流程圖；第9圖顯示可根據本發明一實施例來形成及處理氧化矽層之基材處理系統的垂直剖面圖；以及第10圖為根據本發明一實施例，基材處理系統之系統監視器/控制器部件的簡化示意圖。
200‧‧‧方法
202、204、206、208、210‧‧‧步驟

Claims (19)

  1. 一種固化一基材上之一氧化矽層的方法，該方法包含：提供一半導體處理室和一基材；形成一氧化矽層於至少一部分的該基材上，該氧化矽層包括一產生的碳物種副產物；形成該氧化矽層後，引入一酸性蒸氣至該半導體處理室中，該酸性蒸氣與該氧化矽層反應，其中該酸性蒸氣與該氧化矽層之間的該反應將該碳物種從該氧化矽層移除；以及移除該半導體處理室內的該酸性蒸氣。
  2. 如申請專利範圍第1項所述之方法，其中該氧化矽層是利用一烷氧矽烷(alkoxysilane)製程沉積而得。
  3. 如申請專利範圍第1項所述之方法，其中該氧化矽層是利用一電漿化學氣相沉積(CVD)製程沉積而得。
  4. 如申請專利範圍第1項所述之方法，其中引入一酸性蒸氣的步驟更包含流入氯化氫(HCl)氣體至該半導體處理室中。
  5. 如申請專利範圍第4項所述之方法，其中該HCl氣體伴隨著一矽氧烷前驅物流入。
  6. 如申請專利範圍第1項所述之方法，其中引入一酸性蒸氣的步驟更包含原位產生氯化氫(HCl)或乙酸(CH3 COOH)。
  7. 如申請專利範圍第6項所述之方法，其中原位產生HCl或CH3 COOH是使用氯矽氧烷(chloro-siloxane)或乙醯氧矽氧烷(acetoxy-siloxane)來執行。
  8. 如申請專利範圍第7項所述之方法，其中該氯矽氧烷選自於由二氯二乙氧基矽氧烷(dichlorodiethoxysiloxane)和氯三乙氧基矽氧烷(chlorotriethoxysiloxane)所組成之群組中。
  9. 如申請專利範圍第7項所述之方法，其中該乙醯氧矽氧烷為二乙醯氧二叔丁基矽烷(diacetoxydi-tert -butylsilane)。
  10. 如申請專利範圍第1項所述之方法，其中該酸性蒸氣催化由該氧化矽層的一有機矽化合物中移除一烷氧基，以留下一矽醇部分(silanol moiety)。
  11. 如申請專利範圍第1項所述之方法，其中該蒸氣為酸與水的混合物，該混合物具有一水：酸的比例。
  12. 如申請專利範圍第11項所述之方法，其中該水：酸的比例為約100：1至約1：100。
  13. 如申請專利範圍第1項所述之方法，其中該酸性蒸氣與該氧化矽層之間的該反應是在10毫托耳至大氣壓之間的壓力下執行。
  14. 如申請專利範圍第1項所述之方法，其中該酸性蒸氣與該氧化矽層之間的該反應是在60℃至600℃之間的溫度下執行。
  15. 如申請專利範圍第1項所述之方法，其中該氧化矽層接觸該酸性蒸氣的時間介於1秒至24小時之間。
  16. 如申請專利範圍第1項所述之方法，其中複數個結構形成在該基材的一表面上，其中該些結構包括深寬比為7：1或更高的多個間隙和多個溝槽。
  17. 如申請專利範圍第1項所述之方法，其中包含該碳物種的該最初形成的氧化矽層為一具流動性的氧化矽層。
  18. 如申請專利範圍第1項所述之方法，更包含在引入該 酸性蒸氣至該半導體處理室之後，退火該氧化矽層，以增加該氧化矽層的密度。
  19. 如申請專利範圍第10項所述之方法，其中該矽醇部分與出現在該氧化矽層中的其他矽醇部分反應，形成一氧化矽網絡。
TW097132417A 2007-08-27 2008-08-25 以ｈａｒｐii 處理固化烷氧矽烷前驅物沉積之二氧化矽薄膜的方法 TWI395269B (zh)

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