TWI359475B - Method for preventing an increase in contact hole - Google Patents
Method for preventing an increase in contact hole Download PDFInfo
- Publication number
- TWI359475B TWI359475B TW093131505A TW93131505A TWI359475B TW I359475 B TWI359475 B TW I359475B TW 093131505 A TW093131505 A TW 093131505A TW 93131505 A TW93131505 A TW 93131505A TW I359475 B TWI359475 B TW I359475B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- contact hole
- contact
- barrier layer
- oxide layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
- H10W20/034—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics bottomless barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/705,631 US7005387B2 (en) | 2003-11-08 | 2003-11-08 | Method for preventing an increase in contact hole width during contact formation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200524077A TW200524077A (en) | 2005-07-16 |
| TWI359475B true TWI359475B (en) | 2012-03-01 |
Family
ID=34552414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW093131505A TWI359475B (en) | 2003-11-08 | 2004-10-18 | Method for preventing an increase in contact hole |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7005387B2 (https=) |
| JP (1) | JP4662943B2 (https=) |
| KR (1) | KR101180977B1 (https=) |
| CN (1) | CN1883045A (https=) |
| DE (1) | DE112004002156T5 (https=) |
| GB (1) | GB2423635B (https=) |
| TW (1) | TWI359475B (https=) |
| WO (1) | WO2005048342A1 (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080038910A1 (en) * | 2006-08-10 | 2008-02-14 | Advanced Micro Devices, Inc. | Multiple lithography for reduced negative feature corner rounding |
| US20090050471A1 (en) * | 2007-08-24 | 2009-02-26 | Spansion Llc | Process of forming an electronic device including depositing layers within openings |
| US12444651B2 (en) | 2009-08-04 | 2025-10-14 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
| JP6494940B2 (ja) * | 2013-07-25 | 2019-04-03 | ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ | 異なるサイズのフィーチャへのボイドフリータングステン充填 |
| US9972504B2 (en) | 2015-08-07 | 2018-05-15 | Lam Research Corporation | Atomic layer etching of tungsten for enhanced tungsten deposition fill |
| KR102607331B1 (ko) * | 2018-07-13 | 2023-11-29 | 에스케이하이닉스 주식회사 | 고종횡비 구조를 위한 갭필 방법 및 그를 이용한 반도체장치 제조 방법 |
| CN116259575A (zh) * | 2022-09-07 | 2023-06-13 | 上海华力集成电路制造有限公司 | 钨填充工艺的改善方法 |
| CN119452753A (zh) | 2023-01-05 | 2025-02-14 | 富士电机株式会社 | 半导体装置及其制造方法 |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0513411A (ja) * | 1991-07-02 | 1993-01-22 | Nec Corp | 半導体装置の製造方法 |
| JPH0661181A (ja) | 1992-08-11 | 1994-03-04 | Sony Corp | バリアメタルの形成方法 |
| JP3237917B2 (ja) * | 1992-09-22 | 2001-12-10 | 沖電気工業株式会社 | 半導体素子の製造方法 |
| JPH06349824A (ja) * | 1993-06-10 | 1994-12-22 | Toshiba Corp | 半導体装置の製造方法 |
| JPH09116009A (ja) * | 1995-10-23 | 1997-05-02 | Sony Corp | 接続孔の形成方法 |
| JPH09139358A (ja) * | 1995-11-13 | 1997-05-27 | Sony Corp | 半導体装置の製造方法 |
| US5985762A (en) * | 1997-05-19 | 1999-11-16 | International Business Machines Corporation | Method of forming a self-aligned copper diffusion barrier in vias |
| TW388095B (en) * | 1997-05-20 | 2000-04-21 | United Microelectronics Corp | Method for improving planarization of dielectric layer in interconnect metal process |
| JP3201318B2 (ja) * | 1997-11-05 | 2001-08-20 | 日本電気株式会社 | 半導体装置の製造方法 |
| US5994211A (en) * | 1997-11-21 | 1999-11-30 | Lsi Logic Corporation | Method and composition for reducing gate oxide damage during RF sputter clean |
| US6303505B1 (en) * | 1998-07-09 | 2001-10-16 | Advanced Micro Devices, Inc. | Copper interconnect with improved electromigration resistance |
| US6511575B1 (en) * | 1998-11-12 | 2003-01-28 | Canon Kabushiki Kaisha | Treatment apparatus and method utilizing negative hydrogen ion |
| KR100277086B1 (ko) * | 1999-01-02 | 2000-12-15 | 윤종용 | 반도체 장치 및 그 제조 방법 |
| JP4221859B2 (ja) * | 1999-02-12 | 2009-02-12 | 株式会社デンソー | 半導体装置の製造方法 |
| US6348709B1 (en) * | 1999-03-15 | 2002-02-19 | Micron Technology, Inc. | Electrical contact for high dielectric constant capacitors and method for fabricating the same |
| JP2000323571A (ja) * | 1999-05-14 | 2000-11-24 | Sony Corp | 半導体装置の製造方法 |
| KR100316721B1 (ko) * | 2000-01-29 | 2001-12-12 | 윤종용 | 실리사이드막을 구비한 반도체소자의 제조방법 |
| KR20010077743A (ko) * | 2000-02-08 | 2001-08-20 | 박종섭 | 비트 라인 및 그 제조 방법 |
| US6498091B1 (en) * | 2000-11-01 | 2002-12-24 | Applied Materials, Inc. | Method of using a barrier sputter reactor to remove an underlying barrier layer |
| US6624066B2 (en) | 2001-02-14 | 2003-09-23 | Texas Instruments Incorporated | Reliable interconnects with low via/contact resistance |
| US20030073304A1 (en) * | 2001-10-16 | 2003-04-17 | Applied Materials, Inc. | Selective tungsten stud as copper diffusion barrier to silicon contact |
-
2003
- 2003-11-08 US US10/705,631 patent/US7005387B2/en not_active Expired - Fee Related
-
2004
- 2004-10-08 GB GB0608285A patent/GB2423635B/en not_active Expired - Fee Related
- 2004-10-08 WO PCT/US2004/033417 patent/WO2005048342A1/en not_active Ceased
- 2004-10-08 CN CNA2004800337772A patent/CN1883045A/zh active Pending
- 2004-10-08 DE DE112004002156T patent/DE112004002156T5/de not_active Ceased
- 2004-10-08 JP JP2006539499A patent/JP4662943B2/ja not_active Expired - Fee Related
- 2004-10-08 KR KR1020067008659A patent/KR101180977B1/ko not_active Expired - Fee Related
- 2004-10-18 TW TW093131505A patent/TWI359475B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| GB2423635A (en) | 2006-08-30 |
| US20050101148A1 (en) | 2005-05-12 |
| JP4662943B2 (ja) | 2011-03-30 |
| WO2005048342A1 (en) | 2005-05-26 |
| GB0608285D0 (en) | 2006-06-07 |
| CN1883045A (zh) | 2006-12-20 |
| DE112004002156T5 (de) | 2006-09-14 |
| KR101180977B1 (ko) | 2012-09-07 |
| JP2007511087A (ja) | 2007-04-26 |
| US7005387B2 (en) | 2006-02-28 |
| TW200524077A (en) | 2005-07-16 |
| KR20060107763A (ko) | 2006-10-16 |
| GB2423635B (en) | 2007-05-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |