TWI409882B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims abstract description 84
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 14
- 239000006227 byproduct Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 27
- 238000002844 melting Methods 0.000 claims description 22
- 230000008018 melting Effects 0.000 claims description 22
- 239000010936 titanium Substances 0.000 claims description 19
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 15
- 229910052719 titanium Inorganic materials 0.000 claims description 14
- 229910000838 Al alloy Inorganic materials 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 8
- 229910052715 tantalum Inorganic materials 0.000 claims description 8
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 3
- WIGAYVXYNSVZAV-UHFFFAOYSA-N ac1lavbc Chemical compound [W].[W] WIGAYVXYNSVZAV-UHFFFAOYSA-N 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims 1
- 229910052797 bismuth Inorganic materials 0.000 claims 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims 1
- 239000003870 refractory metal Substances 0.000 abstract 3
- 150000004767 nitrides Chemical class 0.000 description 11
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 9
- 229910052707 ruthenium Inorganic materials 0.000 description 9
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 230000007774 longterm Effects 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
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- 238000012545 processing Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 150000002291 germanium compounds Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/3105—After-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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Description
本發明係有關具有多層配線構造之半導體裝置及其製造方法，尤其有關反射防止膜。
目前為止，在鋁或鋁合金上將光阻劑圖案化之際，為了防止不良情況原因的光暈(Halation)，係形成有反射防止膜。例如專利文件1中揭示有以濺鍍堆積TiN、TaN、ZrN、HfN等高熔點金屬氮化膜的製造方法。第7圖到第11圖，係表示將此種高熔點金屬氮化膜用作反射防止膜之多層配線製造工程的一例。
但是將高熔點金屬氮化膜當作反射防止膜來適用於多層配線構造來說，不僅止於單純降低反射率就好的要求。這是因為具有多層配線構造之半導體裝置的情況下，下層金屬配線與上層金屬配線經由連接孔，以低貫通孔電阻來連接是非常重要的。
上述專利文件1所示之製造方法係難以得到充分低的電阻，故作為解決此者之手段，專利文件2揭示有在堆積高熔點金屬後，於氮環境中進行熱處理，藉此降低高熔點金屬之電阻率的製造方法；或是專利文件3揭示有層積堆積Ti與TiN的製造方法。又，使用高熔點金屬膜作為反射防止膜的重大理由是提高長期可靠度。使用鋁或鋁合金為主要配線時，會有電子遷移或應力遷移等有關配線之長期可靠度的劣化現象。此問題已知藉由使用高熔點金屬可得到配線補強效果，而對上述劣化現象可達成高耐性。
[專利文件1]日本特開平1－241162號公報[專利文件2]日本特開平5－226338號公報[專利文件3]日本特開平5－190551號公報
若依先前技術，則特徵為對具有多層配線構造之半導體裝置之反射防止膜，適用高熔點金屬氮化膜。然而將高熔點金屬氮化膜適用為反射防止膜時，在使用乾蝕刻技術開孔接觸孔之際，會如第12圖所示般沿著連接孔之側壁形成由阻劑、蝕刻氣體、基底亦即高熔點金屬氮化膜等所構成的副產生物12。上述副產生物，即使經過在一般蝕刻處理後所進行之阻劑灰化，和對有機剝除液之浸泡所形成的阻劑去除工程，也會在連接孔作為殘渣而殘留為王冠狀，因為該形狀而一般稱為隆起(Crown)。以下在本說明書中就記載為隆起。
在形成有上述隆起12之情況下，若使用濺鍍技術堆積第2配線金屬，則上述隆起會妨礙濺鍍粒子對連接孔的入射，而無法對連接孔內部堆積期望的膜厚。依此會如第13圖所示，造成配線金屬13之斷線而成為降低生產率的不良情況。又在不造成斷線之等級下作較薄堆積時，不可否定地有可能會無視於容易預測在半導體裝置之可靠度上有重大問題，就通過電氣特性評價，作為良品而流通到市面上。
專利文件2中，揭示有在高熔點金屬膜堆積後，於氮氣環境中進行熱處理的發明；但是這不只會增加工程，還必須有450℃左右之熱處理溫度，藉由以防止半導體基板與配線金屬之相互擴散為目的而廣泛使用之遮蔽金屬的劣化，會有對基板側之配線金屬電突(Spike)造成接合洩漏電流的增加等之虞，同時也可輕易想到熱處理之不一致等會造成高熔點金屬氮化膜對於高熔點金屬膜的厚度產生變化。這在形成上層配線之際，會產生於接觸孔接觸到高熔點金屬氮化膜層的情況，和接觸到高熔點金屬膜的情況，而難以得到安定的貫通電阻。
專利文件3中，揭示有以濺鍍將Ti與TiN層積構造化的發明；但是改變氣體環境，而在相同處理室內處理Ti和TiN時，每一次半導體基板處理，都必須有在濺鍍TiN之後使用Ar等惰性氣體來去除濺鍍靶表面之氮化層的步驟，故不只增加處理時間，在堆積於半導體基板之外還會造成靶消耗，故經濟性不良。將Ti與TiN分別在單獨處理室內處理時，因為TiN膜之高應力，堆積於TiN膜處理室內部的TiN會剝落並容易掉落到半導體基板，而在之後的配線形成工程中，有容易產生圖案缺陷而降低生產率之虞。
本發明之目的係針對具有多層配線構造之半導體裝置，提供一種具有多重配線構造之半導體裝置之製造方法，其中包含不會在接觸孔產生隆起(Crown)，具有較高之長期可靠度，生產性、經濟性優良，具有相當低之貫通孔(Via孔)電阻的反射防止膜形成方法。
本發明中為了解決上述課題，係作為一種半導體裝置之製造方法，其係半導體裝置之多層配線構造的製造方法；由以下工程所構成：在包含第1遮蔽金屬之配線用金屬膜上，層積高熔點金屬膜的工程；和在上述高熔點金屬膜上，堆積反射防止膜的工程；和形成由包含上述第1遮蔽金屬之配線用金屬膜，與上述高熔點金屬膜，以及上述反射防止膜所形成之配線的工程；和在上述配線上形成層間絕緣膜的工程；和在上述層間絕緣膜上，形成與上述配線最上層，亦即與上述反射防止膜之連接孔的工程；和在上述連接孔形成後，選擇性去除上述連接孔底部之上述反射防止膜的工程；和經由上述連接孔，堆積第2配線用金屬膜的工程。
上述多層配線構造之製造方法中的構成材料，就材料成本廉價的理由來看，上述第1配線用金屬膜及第2配線用金屬膜，係作為鋁或鋁合金；為了提高對應力遷移及電子遷移之耐性，上述高熔點金屬膜係鈦、鈦化鎢、鎢、鉭、鉬的任一種；而作為在連接孔開口後僅藉由一般之阻劑灰化、對有機剝除液之浸泡等就可輕易去除蝕刻副產生物，而不會產生隆起，且對半導體裝置之製造工程之親和性也高的材料，上述反射防止膜係由矽或矽化物所構成。
另外，上述多層配線構造之製造方法中，作為構成材料之製法，就生產性、經濟性來看，係藉由PVD進行上述高熔點金屬膜之堆積方法及上述反射防止膜之堆積方法。
又，是作為一種半導體裝置，係一種多層配線構造之半導體裝置，其由以下所構成；由形成於半導體基板上而包含第1遮蔽金屬之配線用金屬膜、與僅形成於包含上述第1遮蔽金屬之配線用金屬膜上之高熔點金屬膜、與上述高熔點金屬膜上之反射防止膜所構成的第1配線，和形成於上述第1配線上的連接孔，和經由上述連接孔與上述第1配線連接的第2配線；其特徵係上述反射防止膜係僅形成於上述連接孔範圍以外的上述高熔點金屬膜上，且由矽或矽化物所構成。
若依本發明，則可實現一種具有多重配線構造之半導體裝置之製造，其中不會在具有多重配線構造之半導體裝置的接觸孔產生隆起，具有較高之長期可靠度，生產性、經濟性優良，具有相當低之貫通孔電阻，且電阻不一致較小。
第1圖到第6圖係表示本發明之實施例，亦即具有多層配線構造之半導體裝置之製造方法的工程剖面圖。
首先如第1圖所示，在堆積於半導體基板1上之層間絕緣膜2上，以PVD堆積遮蔽金屬3及第1鋁合金膜4之後，以補強配線為目的，不暴露於大氣而使用PVD在上述鋁合金膜4上，於真空中將鈦膜5連續堆積為厚度10~200nm的範圍。這是為了防止上述鋁合金膜4與上述鈦膜5之間產生氧化鋁膜，這對得到較低貫通電阻來說相當重要。接著在上述鈦膜5上，作為反射防止膜，係以PVD將非晶質矽膜6之厚度任意選擇其膜厚，來成為期望的反射率，為了降低反射率，非晶質矽膜之膜厚以設定在100~200為佳。可以的話以110~150為佳。上述鈦膜5與上述非晶質矽膜6並不需要在真空中連續堆積，但是就生產性來說係在同一個裝置內連續堆積為佳。
第2圖係表示對上述膜構造所構成之配線層，使用光微影法及乾蝕刻技術形成配線圖案後的工程剖面圖。接著如第3圖所示來形成金屬層間絕緣膜。金屬層間絕緣膜為了防止配置於上層之配線的斷線、短路，係以平坦為佳；使用以SOG作為犧牲膜而藉由全面蝕刻來平坦化的技術，或CMP(化學機械研磨)法所形成的金屬層間平坦化技術，來形成平滑的金屬層間絕緣膜7。接著使用光微影技術及乾蝕刻技術，形成第4圖所示的連接孔8。另外在連接孔的乾蝕刻之際，為了不使第1圖所堆積之非晶質矽膜6於乾蝕刻時的過度蝕刻中消失，必須調整選擇比。選擇比有藉由調整例如CHF3
、CF4
等蝕刻氣體的混合比，可輕易控制對非晶質矽膜6之選擇比的優點。
接著如第5圖所示，為了得到低貫通電阻，使用乾蝕刻技術僅去除連接孔底部的非晶質矽膜6。這可以藉由CF4
電漿或CHF3
電漿，輕易實現將與下層之鈦層5之選擇比取為相當大的蝕刻條件。藉此，不會過度蝕刻下層的鈦層5，而可將膜厚保持平均。因此可降低鈦層5之膜厚所造成的電阻值不一致。非晶質矽膜6的去除，可以在進行連接孔8之蝕刻後在相同裝置(in－situ)內加以處理，但是因為連接孔側壁會產生蝕刻的副產生物，故會留下該厚度份量的非晶質矽膜6；因此在進行連接孔8之蝕刻後，再藉由灰化、對有機剝除液浸泡來進行阻劑、副產生物的去除，才開始進行非晶質矽膜6的蝕刻為佳。使用包含高熔點金屬氮化膜之高熔點金屬膜11(第12圖)作為反射防止膜時，蝕刻時的副產生物會吸收大量的鈦，而難以去除該者；但如果是本發明之構造，則可輕易去除。藉此，可充分降低貫通孔電阻。
接著，使用PVD裝置，以RF蝕刻來清潔接觸孔8底部的鈦膜表面以後，堆積遮蔽金屬膜9及第2鋁合金膜10，之後使用光微影技術及乾蝕刻技術來得到第6圖的多層配線構造。
本實施例中雖使用鈦(Ti)作為配線補強用的高熔點金屬膜，但是鈦化鎢(TiW)、鎢(W)、鉭(Ta)、鉬(Mo)膜當然也可得到相同效果。更且作為反射防止膜除了非晶質矽以外，多晶矽或氮化矽般的矽化合物也可得到相同效果。
若依本發明，則為了充分降低貫通孔電阻，減少電阻不一致，係在第1鋁合金膜4之上下層積有高熔點金屬膜，故有應力遷移或電子遷移等之可靠度也提高的優點。
1．．．半導體基板
2．．．層間絕緣膜
3．．．遮蔽金屬膜
4．．．第1鋁合金膜
5．．．鈦膜
6．．．非晶質矽膜
7．．．金屬層間絕緣膜
8．．．連接孔
9．．．遮蔽金屬膜
10．．．第2鋁合金膜
11．．．包含高熔點金屬氮化膜之高熔點金屬膜
12．．．隆起
13．．．配線金屬
[第1圖]表示本發明之第1實施例的工程剖面圖[第2圖]表示本發明之第1實施例的工程剖面圖[第3圖]表示本發明之第1實施例的工程剖面圖[第4圖]表示本發明之第1實施例的工程剖面圖[第5圖]表示本發明之第1實施例的工程剖面圖[第6圖]表示本發明之第1實施例的工程剖面圖[第7圖]表示先前例的工程剖面圖[第8圖]表示先前例的工程剖面圖[第9圖]表示先前例的工程剖面圖[第10圖]表示先前例的工程剖面圖[第11圖]表示先前例的工程剖面圖[第12圖]表示先前例中造成隆起產生的剖面圖[第13圖]表示先前例中之隆起產生，造成金屬配線之覆蓋不良例子1的剖面圖
1．．．半導體基板
2．．．層間絕緣膜
3．．．遮蔽金屬膜
4．．．第1鋁合金膜
5．．．鈦膜
6．．．非晶質矽膜
7．．．金屬層間絕緣膜
9．．．遮蔽金屬膜
10．．．第2鋁合金膜
Claims (8)
- 一種半導體裝置之製造方法，係半導體裝置之多層配線構造的製造方法；其特徵係由以下工程所構成：將第1層間絕緣膜形成於半導體基板上的工程；在前述第1層間絕緣膜上，層積具有遮蔽金屬(barrier metal)的第1配線用金屬膜以及其上之高熔點金屬膜的工程；在上述高熔點金屬膜上，堆積反射防止膜的工程；形成由上述具有遮蔽金屬的第1配線用金屬膜、上述高熔點金屬膜以及上述反射防止膜所構成之配線的工程；在上述配線上形成第2層間絕緣膜的工程；蝕刻上述第2層間絕緣膜，以上述配線最上層之上述反射防止膜露出的方式形成連接孔同時於前述連接孔的側壁產生蝕刻副產生物的工程；除去產生於上述連接孔的側壁的前述蝕刻副產生物的工程；在上述連接孔形成後，選擇性去除上述連接孔底部之上述反射防止膜，露出上述高熔點金屬膜的工程；以及經由上述連接孔，堆積第2配線用金屬膜的工程。
- 如申請專利範圍第1項所記載之半導體裝置之製造方法，其中，上述第1配線用金屬膜及第2配線用金屬膜，係由鋁或鋁合金所構成。
- 如申請專利範圍第1項所記載之半導體裝置之製造方法，其中，上述高熔點金屬膜係鈦、鈦化鎢、鎢、 鉭、鉬的任一種。
- 如申請專利範圍第1項所記載之半導體裝置之製造方法，其中，上述反射防止膜係由矽或矽化物所構成。
- 如申請專利範圍第1項所記載之半導體裝置之製造方法，其中，藉由PVD進行上述高熔點金屬膜之堆積。
- 如申請專利範圍第1項所記載之半導體裝置之製造方法，其中，藉由PVD進行上述反射防止膜之堆積。
- 如申請專利範圍第1項所記載之半導體裝置之製造方法，其中，藉由乾蝕刻進行上述反射防止膜之去除。
- 一種半導體裝置，係多層配線構造之半導體裝置，其特徵為由以下所構成：半導體基板、被設於前述半導體基板上的第1層間絕緣膜、形成於上述第1層間絕緣膜上，而由具有遮蔽金屬的第1配線用金屬膜、僅形成於上述具有遮蔽金屬的第1配線用金屬膜上之高熔點金屬膜、以及僅被形成於上述高熔點金屬膜上之反射防止膜所構成的第1配線、被形成於設在上述第1配線上的第2層間絕緣膜之到達上述高熔點金屬膜的連接孔、和經由上述連接孔與上述第1配線連接的第2配線；上述反射防止膜係僅被配置於上述連接孔範圍以外的上述高熔點金屬膜上，同時上述反射防止膜係由矽或矽化物所構成。
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