TWI339429B - Lead frame and method of manufacturing the same - Google Patents

Lead frame and method of manufacturing the same Download PDF

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Publication number
TWI339429B
TWI339429B TW093101000A TW93101000A TWI339429B TW I339429 B TWI339429 B TW I339429B TW 093101000 A TW093101000 A TW 093101000A TW 93101000 A TW93101000 A TW 93101000A TW I339429 B TWI339429 B TW I339429B
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TW
Taiwan
Prior art keywords
lead frame
conductor layer
layer
wire
conductor
Prior art date
Application number
TW093101000A
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English (en)
Other versions
TW200425445A (en
Inventor
Kobayashi Takeshi
Sugoh Hisao
Original Assignee
Panasonic Corp
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Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Publication of TW200425445A publication Critical patent/TW200425445A/zh
Application granted granted Critical
Publication of TWI339429B publication Critical patent/TWI339429B/zh

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    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16KVALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K11/00Multiple-way valves, e.g. mixing valves; Pipe fittings incorporating such valves
    • F16K11/02Multiple-way valves, e.g. mixing valves; Pipe fittings incorporating such valves with all movable sealing faces moving as one unit
    • F16K11/08Multiple-way valves, e.g. mixing valves; Pipe fittings incorporating such valves with all movable sealing faces moving as one unit comprising only taps or cocks
    • F16K11/085Multiple-way valves, e.g. mixing valves; Pipe fittings incorporating such valves with all movable sealing faces moving as one unit comprising only taps or cocks with cylindrical plug
    • HELECTRICITY
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00Electroforming
    • C25D1/0033D structures, e.g. superposed patterned layers
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16KVALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K27/00Construction of housing; Use of materials therefor
    • F16K27/06Construction of housing; Use of materials therefor of taps or cocks
    • F16K27/065Construction of housing; Use of materials therefor of taps or cocks with cylindrical plugs
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1339429 玖、發明說明: » * 【發明所屬之技術領域】 本發明係關於一種導線架、 線架之半導體裝置及半導體裝 發明係關於樹脂密封型半導體 【先前技術】 最近,例如個人電腦與行動 小。由於此種電子設備縮小的 方式組裝。因此,在半導體裝 體,為了減小組裝面積,廣泛 此種面組裝型半導體裝置中 降低製造成本,廣泛使用樹脂 料成本低且生產率高。 為了遠到縮小半導體裝置尺 出。其使用一種導線架,其中 突起:而半導體晶片係安裝於 密封完成後,從反面進行研磨 除,使得厚度減少,然後進行 半導《裝1 。 例如,提出圖1 1 A至1 1 C所 導體裝置,請參照專利文件 1 成。一半導體晶片係固定並電 從導線架的反面進行樹脂密封 定至導線架上。一導線架包含 導線架之製造方法、使用導 置之製造方法。特別地,本 裝置之外部端的形成。 電話等電子設備的尺寸已縮 趨勢,電子零件係以高密度 置領域,例如二極體與電晶 使用面組裝型半導體裝置。 ,在封裝的型式方面,為了 密封型半導體裝置,因為材 寸的目的,已有下列技術提 ,變成導線之區域形成有一 導線架上並電性連接。樹脂 ,藉以將導線架連同樹脂移 切片,以便將其分割成個別 示之半導體裝置。關於此半 。此半導體係以下列方式形 性連接至一導線架,然後, 。然後,半導體晶片72被固 有島狀物 6 1、6 1 A,其會變 3 12/發明說明扭(補件)/93-04/93丨ϋ 1000 1339429 成外邡連接用電極,並包含有複數個導線端6 2、6 3、6 2 A、 6 3 A,其會變成鄗接島狀物所固定之半導體晶片7 2的其他 外部連接用電極,導線架係固定至半導體晶片72,半導體 ώ片72附接於複數個導線架之島狀物上的導電膏,複數個 碎線架係藉由導電棒而以列方向配置,並電性連接至鄰接 導線端。一樹脂層係形成於導線架上,使得半導體晶片和 導線端可被覆蓋,且島狀物之反面及導線端可暴露出。在 一環繞電性連接導線端之區域中,半導體晶片所固定之島 狀物與半導體晶片係個別地分割成個別件。 [專利文件]] 未審查日本專利公開第H e i - 1 0 - 3 1 3 0 8 2號 根據此技術,可縮小半導體裝置之尺寸。然而,在樹脂 密封型半導體裝置與印刷電路板的接觸面上,亦即,在半 办《褚體電路裝置的反面上,由於樹脂面與成為外部端之 存線端係位於相同平面上,因此,即使只產生很小的尺寸 誤差,也不可能確實地連接到印刷電路板上的電路圖索, 而可能導致不完全接觸。 為了使導線端突出,必須提供一電鍍製程,其中,在切 片完成之後,形成凸塊(突出部),增加製造過程中的人工 時數。 本發明係鑑於上述實際狀況而完成。本發明之目的在於 從供一種容易製造之高可靠性之薄型半導體裝置。 【钤明内容】 本發明提供一種垛線架,包含:一導線架本體,包含一 3丨2/發叫說明故_(牛)Λ)3-()4/93 Η)丨000 1339429 金屬製成之板狀本體:一槽部,用於形成一導線,其係以 « * 一預定深度形成於導線架本體表面上之導線形成區域中; 及一導線部,其形成方式係可使導線部從槽部突出到導線 架本體之表面上,導線部係由不同於導線架本體材料之材 料製成。 根據上述構造,所形成之導線部係從槽部突出。因此執 行组裝可使得導線部從密封樹脂突出。因此,當半導體裝 1組裝到印刷電路板時,所提供的半導體裝置不會產生不 完全接觸。據此,可形成一種穩定的外部端結構,在樹脂 密封完成之後,不需要進行電鍍製程。 此外端可在經由導線架本體電性連接的條件下形 成。因此,當外部端形成時,能夠採用一電解電鍍方式, 其中使用導線架本體做為電極。據此,可以高精確度來控 制厚度,以高效率形成高可靠性之外部端。 半導體晶片安裝在導線部上之後,藉由打線接合或直接 接合而進行電性連接。然後1進行樹脂密封,並藉由從反 而蚀刻而將導線架本體移除。因而,可提供一種高可靠性 之溥型半導體裝置。詳言之1半導體裝置的厚度可縮小成 大約習知半導體裝置厚度的四分之三。 在半導體晶片安裝時,導線部係固定於導線架本體。因 此,不會產生位置偏移,可以高可靠度確實地進行接合。 又,由於藉由樹脂密封確實地固定裝置,並從反面移除導 線架本體,故半導體裝置中不會產生變形。 又,樹脂密封完成後,進行切片使其可分割成個別半導 3 1),¾明,丨丨:(fili件)/93-04/93 丨 ϋ 1000 1339429 體裝置。此種情形,導線部可製作成不存在於切片區域中。 因此,切}ί時切割刀片不需要切除導線部。因此,可減少 • . 切割刀片的磨損,切割刀片的壽命玎延長。 由於導線只有從密封樹脂的主平面導出,未從密封樹脂 的側面導出,不會有濕氣從大氣中經由導線導出部而進入 密封樹脂。因此,可增進可靠性。 又,導線部的截面輪廓可根據槽部的截面輪廓而自由地 設計。因此,可容易地形成高密度與精準之導線部圖案。 本發明提供一種導線架,導線包括:一第一導體層,形 成於槽部中;一第二導體層,形成於第一導體層上;及一 第三導體層,形成於第二導體層上,其中,第一導體層係 組裝至一組裝構件,及第三導體層係組裝至半導體晶片之 接合墊。 根據上述構造,導線較佳包含一種三層結構,並由對應 於欲連接構件之材料製成。又,位於中央之本體較佳係由 不昂貴之導電材料製成。 本發明提供一種導線架,其中,第一導體層覆蓋槽部之 整個内壁。 根據上述構造,一半導體裝置可與此導線架形成,其方 式使得從密封樹脂暴露出的導線部僅包含第一導體層。因 此,當第一導體層係由可容易與焊錫一同形成合金之穩定 金屬例如黃金製成時,可形成穩定之外部端結構,在密封 完成後不需進行電鍍製程。 此種情況中,只有第一導體層可由不易氧化之穩定金屬 8 312/發明說明書(補件)/93-04/93丨01000 1339429 製成,而第二導體層可由低電阻之不昂貴金屬製成。第一 與第三導齄層可由容易與焊錫接合之材料製成。第三導體 • . 層可由相同於第二導體層材料之材料製成。 第一導體層較佳覆蓋槽部的整個内壁,並覆蓋槽部周圍 的平坦平面之一部分。因此,能夠確實防止第二導體層暴 露。因此,能夠形成高可靠性之半導體裝置。 在本發明之導線架中,第一與第二導體層之介面係位於 導線架本體的表面之上。 根據上述構造,在組裝完成後,第二導體層可完全地以 密封樹脂密封,使得第二導體層不會暴露至表面。因此, 如同上述導線架,可提供壽命長之穩定導線架。 在本發明之導線架中,導線包括一障壁層,用於抑制導 線架本體與第一導體層之間的反應,障壁層係設置於第一 導體層與槽部之間。 根據上述結構,由於存在有鎳或鈦製成之障壁層,第一 導體層與導線架本體之間因加熱而產生介面反應,及第一 導體層可防止劣化。此障壁層可形成得很薄。又,最後可 將此障壁層移除。 在本發明之導線架中,第一導體層係由可與焊錫一同形 成合金之金屬製成。 根據上述導線架所組裝之半導體裝置,當半導體裝置組 裝至一印刷電路板時,可適當地進行接合。 在本發明之導線架中,第三導體層係由打線接合特性高 之金屬製成。 9 312/發明說明書(補件)/93-04/93101000 1339429 根據上述構造,若第三導體層係由打線接合特性高之金 屬例如黃备製成,則半導體晶片可容易地組裝。 * . 在本發明之導線架中,當金屬係接合至一半導體晶片之 接合墊時,第三導體層係由高接合特性之金屬製成。 根據上述構造,即使半導體晶片係藉由直接接合而安 裝,亦可容易地進行組裝。 在本發明之導線架中,第一與第二導體層之膜厚為 0.5 至 2 // m。 根據上述構造,整體厚度可充分地減少。又,第二導體 層的膜厚可充分地增加。因此,能夠構成整體厚度充分減 小之半導體裝置,其外部端電阻很低》 在本發明之導線架中,第一導體層包含一黃金層。 根據上述構造,能夠構成一低電阻之穩定外部端,其可 容易地與焊錫形成合金。 在本發明之導線架中,第三導體層包含一黃金層。 根據上述構造,能夠構成高可靠性之外部端,其與半導 體晶片之連接特性極佳。 在本發明之導線架中,第二導體層包含一金屬層,其主 要成分為鎳。 根據上述構造,能夠形成一低電阻之導線,其黃金的附 著特性很高。 此種情況中,若第一導體層係由容易與焊錫一同形成合 金之穩定金屬例如黃金製成,可形成一穩定外部端結構1 在密封完成後不需要進行電鍍製程。 10 312/發明說明書(補件)/93-04/93101000 1339429 此種情況中,只有第一導體層可由不易氧化之穩定金屬 製成,而第二導體層可由低電阻之不昂貴金屬製成。第一 > * 與笫三導體層可由容易與焊錫接合之材料製成。第三導體 層可由相同於第二導體層材料之材料製成。 本發明之導線架之製造方法包含·: 一阻劑圖案形成步 w ·在包含一金屬製成之板狀本體之導線架本體一表面上 形成一阻劑圖案,使得一導線形成區域可開放;一槽部形 成步驟,以阻劑圆案做為遮罩,進行蝕刻,形成一槽部, IH以在導線形成區域中形成一預定深度之導線;及一導線 形成步驟,形成一導線,使得導線可從槽部突出到導線架 本體之一表面上,導線之材料係不同於導線架本體之材料。 根據上述構造,能夠容易地形成一高精確、可靠性之導 線架。又,當使用微影技術製程時,能夠形成一精細之高 在本發明導線架之製造方法中,導線形成步驟包括一電 解電鍍步驟,以阻劑圖案做為一遮罩,在槽部之一内壁上 形成一金屬薄膜。 根據上述構造,可以導線架本體做為電極,進行電解電 诞。因此,可在短時間内容易地形成一低電阻之導線架。 由於電iW電鍍之進行係使用形成槽部之阻劑圖案做為遮 革,可在槽部的内璧上形成金屬薄膜。因而,能夠形成一 Η有層結搆之外部端,其中整個外部端係被最外部金屬薄 脱坨蓋。 本發明導線架之製造方法又包含一阻劑圖案縮小步 11 川 2/¾明説明U::( Hlii牛)/93-04/93 丨 01000 1339429 w ,在以阻劏圖案做為遮罩而形成槽部之後,縮小阻 案,使得導線架本體之環繞槽部之一表面可稍微暴露 根據上述結構,能夠使槽部之周圍邊緣暴露出。因 導體層的形成方式’可使得導體層從槽部之内壁升起 坦部。 本發明導線架之製造方法,導線形成步驟包括:一 導體層形成步驟,在槽部中' 以及從已在縮小步驟裡 之阻劑圆案暴露出之憎部周圍,形成一第一導體層: 二導《層形成步郫,在第一導體層上形成一第二導體 其層合方式係可使得第一導體層之一末端邊緣可被留 及一第三導體層形成步驟,在第二導體層上形成一第 體層。 根據上述構造,第一導體層之形成方式,係使其從 内側升起到平坦部,然後,層合第二與第三層,使.得 導體層的一末端邊緣部可被留置。因此,可容易地形 外部端結構,其中外部端的整個表面為第一導體層所4 在本發明導線架之製造方法中,第二導體層形成步 杧:一薄導電脱形成步驟,在第一導體層上形成一薄 聪:及一回你(e t c h - b a c 1()步现,41由非等向性蚀刻 導電膜上進行回蚀。 在第一導體層已形成於槽部内壁上後,形成第二 層,並進行回蝕過程。以此方式,能夠形成整個第二 層被第一導體層所笟蓋之結構。 在本發明導線架之製造方法中,導線形成步驟包括 3丨2/贺丨丨)ίΗ丨丨件)/W-()4/93丨0丨0()() 劑圖 出。 此, 到平 第一 縮小 一第 層, 置; 三導 槽部 第一 成一 [蓋。 驟包 導電 在薄 導體 導體 一第 12 1339429 一至第三導體層形成步驟,依序在槽部中形成第一至第三 導體層,第一與第二導體層之介面係位於導線架本體的表 面之上。 根據上述構造,能夠形成一種導線架,其中,從密封樹 脂暴露之一半導體裝置表面係做為一外部端,其係為第一 導體層所覆蓋。 在本發明導線架之製造方法中,導線形成步驟包括一障 璧層形成步驟,在第一導體層與槽部之間形成一障壁層, 用於抑制導線架本體與第一導體層之間的反應。 根據上述方法,可藉由一系列電鍍製程而容易地形成障 壁層。因此,製造可容易地進行。 在本發明導線架之製造方法中,槽部形成步驟包括一非 等向性蝕刻步驟,用於形成一槽,其戠面為一深度0 , 5至 2 . 5 μ 111之矩形。 根據上述方法,能夠形成一精細之導線,其圖奉精確度 很高。若矩形槽的深度小於0. 5 μ in,則不可能充分地減小 電阻》若矩形憎的深度超過2. 5 μ in,則很難減小半導體裝 置的厚度。 本發明之一種半導體裝置,包含:一半導體晶片;一導 線部,連接半導體晶片:及一密封樹脂,其中導線部之反 面的一部分係從密封樹脂之主平面突出,且導線部係為一 從外表面側形成至内表面側之薄。 根據上述構造,導線部的外表面會成為一組裝面,將會 被組裝至例如印刷電路板之組裝搆件,導線部的外表面係 13
Μ :/發叨説明·;1;:(補件)/93-04/93 IOIOOO 1339429 於薄膜形成過程中配置在底惻。因此,表面可維持在方向 性極诖且精準度高之狀態。因此,能夠提供一種高可靠性 連接。 在本發明之半導體裝置中,導線包括:一第一導體層; 一第二導體層,層合在第一導體層内側;及一第三導體層, 形成在第二導體層内側,其中,從密封樹脂暴露出之導線 之整個表面,係被第一導體層覆蓋。 根據上述構造,從密封樹脂暴露出的導線部只有第一導 體層。因此,能夠形成一穩定外部端結構,在密封完成後 不需要進行電鍍製程。 在本發明之半導體裝置中,第一與第二導體層之介面係 位於密封樹脂之表面内側。 根據上述構造,組裝完成後,第二導體層係完全地以密 封樹脂密封,使其不會暴露到表面上。因此,以前述半導 體裝1相同的方式,可提供一壽命長之穩定導線架。 在本發明之半導體裝置中,第一導體層係由可與焊錫一 同形成合金之金屬製成。 在本發明之半導體裝置中,第三導體層係由可以打線接 合方式接合之金屬製成。 在本發明之半導體裝置中,第三導體層係由可接合至半 導體晶片之接合墊的金屬製成。 在本發明之半導體裝置中,第一與第二導體層之膜厚為 0 . 5 至 2 μ in。 在本發明之半導體裝置中,第一導體層包含一黃金層。 14 3丨2/發叨說明丨丨;:(fi丨丨件)/93-04/93101000 1339429 在本發明之半導體裝置中,第三導體層包含一黃金層。 在本發明之半導體裝置中,第二導體層包含一金屬層, • . 其主要成分為鎳。 本發明提供一種半導體裝置之製造方法,其中準備一導 線架,導線架包括一導線架本體,其包含一金屬製成之板 狀本體,又包括一用於形成一導線之槽部,槽部係以一預 定深度形成於導線架本體表面上之導線形成區域中,及又 包括一導線,其形成方式係可使導線從槽部突出到導線架 本體之表面上,導線係由不同於導線架本體材料之材料製 成,半導體裝置之製造方法包含:一半導體晶片安裝步驟, 將一半導體晶片安裝於一導線架上,並將半導體晶片電性 連接至導線;一樹脂密封步驟,以密封樹脂覆蓋半導體晶 片:一藉由蝕刻將導線架本體移除之步驟;及一切片步驟, 切;彳成個別半導體裝置。 根據上述構造,在半導體晶片安裝時,導線部係固定於 導線架本體。因此,不會產生位置偏移,可以高可靠度確 實地進行接合。藉由樹脂密封確實地固定導線部之後,並 從反面移除導線架本體。因此,半導體裝置中不會產生變 形。 由於所形成之導線部係從槽部突出,在樹脂密封後,從 密封樹脂突出之導線部不會接受電鍍製程,可形成一穩定 之外部端結搆。因此,半導體裝置可組裝至一印刷電路板, 不t發生不完全接觸。 一独高可靠性之薄型半導體裝置可容易地提供。 15 312/發明說fill 件)/93-04/93 丨 01000 1339429 樹脂密封完成後,進行切片,使半導體裝置可分割成個 別件。由k導線部可製作成不存在於切片區域中,因此切 片時切割刀片不需要切割導線部。因此,可減少切割刀片 的磨損,切割刀片的壽命可延長。 除此之外,導線部的截面輪廓可根據槽部的截面輪廓而 自由地設計。因此,可容易地形成高密度與精準之導線部 圖案。 在本發明半導體裝置之製造方法中,導線包括:一第一 導體層,形成於槽部中;一第二導體層,層合於第一導體 層上;及一第三導體層,形成於第二導體層上,其中,第 一導體層係組裝至一組裝構件,及第三導體層係組裝至半 導體晶片之接合墊。 根據上述構造,可容易地以低成本提供一種高可靠性之 薄型半導體裝置。 在本發明半導體裝置之製造方法中,第一導體層之形成 係使其可覆蓋槽部之整個内壁。 根據上述構造,不需要增加人工天數,即可形成更高可 靠性之薄型半導體裝置。 在本發明半導體裝置之製造方法中,第一與第二導體層 之介面係位於導線架本體的表面之上。 根據上述構造,不需要增加人工天數,即可形成高可靠 性之薄型半導體裝置。 在本發明半導體裝置之製造方法中,導線包括一障壁 層,用於抑制導線架本體與第一導體層之間的反應,障壁 16 312/發明說明書(補件)/93-04/93101000 1339429 層係設置於第一導體層與槽部之間,半導體裝置之製造方 法又包含在樹脂密封完成後藉由蝕刻將障壁層移除之步 驟。 根據上述構造,能夠防止第一導體層因接合製程中所產 生之熱所導致的介面反應而劣化g 【實施方式】 接下來將參照圖式說明本發明之具體例。 (第一具體例) 囷1 A至1 D分別為本發明第一具體例之半導體裝置的上 視® 、沿線A-A所繪製之載面圖、下視囷及沿線所飧 製之截面圖。如圖所示,此半導體裝置係為面組裝型半導 體裝置,其形成方式如下。構成一雙極性電晶體之半導體 晶片1 1係放置於晶粒墊1 0 a上,連接至集極之墊與連接至 射極之墊係分別經由接合線1 2而電性連接至導線端1 0 b ' 】0 c,並以樹脂密封。構成基極端之晶粒墊1 0 a及構成射極 端與集極端之導線端I 0 b、1 0 c,係從此密封樹脂的反面略 微突出,以形成一面組裝型半導體裝置。 晶粒墊與導線端包含一三層結構a如圖2之主要部分放 大圖所示,晶粒墊與導線端包括:一障壁層3 a,包含一鎳 層,其膜厚為0.0005 mm; —第一導體層3b,包含一黃金 層,其膜厚為0.0015mm,形成於障壁層3a上;一第二導 體層3c,包含一鎳層,其膜厚為0,030mm,層合於第一導 體層上;及一第三導體層 3d,包含一黃金層,其膜厚為 0.0007 mm,形成於第二導體層上。 17 312/發明說明書(補件)/93-04/93〗01000 1339429 如圊3之主要部分放大圖所示,此種層結構的特徵 明如下。i導線架本體 1的一銅板表面上所形成之0 mm厚的槽部2中,連續地依序層合障壁層3a、第一導 3b、第二導體層3c及第三導體層 3d,所形成之第一 層係經由障壁層3a而覆蓋槽部2的内壁。此圖顯示阻 移除前之狀態。 接著,以下將說明此種半導體裝置之組裝方法。 首先,將說明此種導線架之製造方法。 根據此方法,淺槽部2係利用微影技術而形成於導 本體之表面上,導線架本體係包含一金屬製成之板狀 (銅板)。然後,藉由電鍍在此槽部2中形成包含一四 構之金屬層的導線部,使得導線部可從槽部突出到導 本體之表面上。 如圖4A所示,準備包含一銅板之導線架本體1。 如圖4 B所示,塗布阻劑R。 之後,如圖4 C所示,藉由微影技術而在阻劑R上 圖案化。以此阻劑做為一遮罩,進行非等向性蝕刻, 形成厚度為0.5至2.5 //m之淺槽2,其截面為矩形 之後,如圖 5 A所示,將阻劑 R留置在原處,並將 架本體1浸入一電鍍溶液中,即磺酸鎳水溶液,藉由 形成障壁層3 a之鎳層。 然後,如圖 5 B所示,藉由電嫂連續地層合第一導 3b之黃金層及第二導體層3c之鎳層。此時,障壁層: 鎳層及第一導體層3b之黃金層係形成於槽部2的整個 312/發明說明書(補件)/93-(M/93101000
係說 .008 體層 導體 劑R 線架 本體 層結 線架 進行 以便 〇 導線 電鍍 體層 ia之 内壁 18 1339429 進一步地,形成第三導體層3d之黃金層。 最後,如圖5 D所示,移除阻劑R,形成本發明第一具體 例之導線架。 接著,將說明使用此種導線架之雙極性電晶體的製造方 法。 首先,如圖6A所示,半導體晶片11的反面係安裝並固 定於圖4 A至5 D所示之導線架的晶粒墊1 0 a。然後,藉由 接合線1 2將半導體晶片與導線端互相電性連接。 之後,如圖6 B所示,以環氧樹脂進行樹脂密封。如此, 形成由密封樹脂1 3所固定之半導體裝置。 最後,如圖 6C所示,以蝕刻的方式,移除包含一銅板 之導線架本體1。如此,可獲得半導體裝置,其障壁層3a 及第一導體層3 b係從密封樹脂1 3暴露出。 然後,如圖7 A所示,將膠帶1 4黏貼至導線端3 ( 3 a、 3 b、3 c )之暴露側。 之後,如圖7 B所示,利用切割的方式,以切割刀片16, 從未黏貼膠帶1 4的一側朝向黏貼膠帶1 4的另一側形成切 片槽1 5,使得半導體裝置可被分離。 如圖7C所示,當半導體裝置被組裝至一印刷電路板時, 半導體裝置可從此膠帶14分離並組裝。 關於此點,接合完成後,可在樹脂密封完成後,藉由蝕 刻而將障壁層連同導線架本體移除。 根據上述結構,由於導線部從密封樹脂表面突出,因此 19 312/發明說明書(補件)/93-04/9310 ] 000 1339429 可穩定地執行组裝,使得導線部可從密封樹脂突出。β 能夠提供一種半導體裝置,在將半導體裝置組裝到印 • . 路板上時,不會產生不完全接觸。如上所述,根據本 之具體例,可構成一種穩定的外部端結構,在樹脂密 成之後,不需要進行電鍍製程。 半導體晶片係安裝在導線部上,並藉由打線接合或 接合而進行電性逹接。然後,進行樹脂密封,並藉由 面蝕刻而將導線架本體移除。因而,可提供一種薄型 t性之半導體裝s 。因此,半導體裝置的厚度能夠ί 地縮小。亦即,半t體裝置的厚度可縮小成大約習知 遛裝置厚度的四分之三。 在半導體晶片安裝時,由於導線部係固定於導線 逋,不會產生位置偏移,可以高可靠度確實地進行接 在杻由樹脂密封確1?地固定半導體晶片後,從反面移 線架本體。因此,半導體裝置中不會產生變形。由於 冇障璧層,即使半導體元件安裝或彳了線接合時連接部 熱到高溫,可防止導線部劣化。此障壁層可留置於原 或者,最後可豬由蝕刻而將此障受層移除。在蝕刻的 屮•若在樹HI密封完成後進行蝕刻1由於其他部分係 封樹脂所覆蓋,因此可逕行將其浸入蝕刻液中。因此 作特性甚佳。 樹脂密封完成後,將半導體裝置切X成個別半導 '使得半導體裝置可分割成個別件a此時,由於切 域未存在有導線部 > 因此,切片時刀片不需要切割導^ 2/發丨(11¾明前補件)/93-04/93 )⑴ 000 此, 刷電 發明 封完 直接 從反 μ可 可能 半導 架本 合。 提供 被加 處。 情況 由密 , 工 體裝 片區 20 1339429 因此,刀片很少產生磨損,刀片的壽命可延長。 由於導k部只有從半導體的主平面導出,不會有空 導線部導出的部分進入半導體裝置。因此,可提供高 性之半導體裝置。 又,導線部的截面輪廓可根據槽部的截面輪廓而自 設計。因此,可形成高精準與高密度之導線部圖案。 由於從半導體裝置之密封樹脂暴露之導線部包含 金層,在樹脂密封完成後,不需要進行電鍍製程,即 成穩定之外部端。 關於此點,第一導體層可由例如黃金、錫及鈀等可 錫一同形成合金之金屬製成。 由於存在有障壁層,因此可利用接合過程中所產生 所導致的介面反應,來防止第一導體層及導線架本 化。此障壁層可由鎳、鈦或鎢製成。障壁層可形成得招 或者,最後可藉由蝕刻將障壁層移除。在金-矽共熔 (eutectic solder)的情況中,必須進行約4 0 0 °C之 接合。另一方面,在金-錫或金-鍺共熔焊錫的情況中 以約3 5 0 °C之相對低溫接合,其不需要提供障壁層。 在本發明之導線架中,若第一導體層係由例如黃金 輕易與焊錫形成合金的金屬製成,當半導體裝置組裝 印刷電路板時,可進行極佳的接合。 若第三導體層係由金屬製成,其打線接合特性高, 體晶片可容易組裝。 此種導線架可應用於打線接合與直接接合。第三導 312/發明說明書(補件)/93-04/93101000 氣從 可靠 由地 一黃 可形 與焊 之熱 體劣 薄。 焊錫 古、,田 肉 /瓜 ,可 等可 到一 半導 體層 21 1339429 可由金屬製成,與半導體晶片之接合墊的接合特性很高。 笫一與第三導體層係提供用於增進接合特性與組裝特 性。因此 ',第一與第三導體層較佳形成得足夠薄。 因此,可顯著地減少整體厚度,且進一步地,第二導體 層的膜厚可製作得足夠厚。據此,能夠搆成一種半導體裝 笠 > 其整體厚度足夠小,具有一低電阻之外部端。 關於此點,在上述第一具體例中,設有障壁層。然而, 亦可採用未設有障壁層之結構,導線部包含三層結構。 乂 根據本具體例之導線架的製造方法1能夠透過微影技術 製程而形成高精確且可靠之導線架。 由於第一導體層係透過障壁層而形成於導線架本體之 槽部的整個内壁上,在樹脂密封完成後,第二導體層不會 從密封樹脂暴露出。如後述之第二具體例所示,較佳第一 與第二導體層的介面係位於槽部的上表面之上。換言之, 笫一與第二導體層之介面較佳係位於導線架本體的上表面 之上。然而,即使第一與第二導體層的介面係位於槽部上 表面的較低層,只要第二層係由不易氧化之材料製成,就 不會產生任何問題。 根據本發明之導線架之製造方法,在導線部形成的過程 屮,金屬薄膜係形成於槽部的内璧上,而阻劑圖案係做為 遮罩。因此,可在短時間内容易地形成低電阻之導線。 由於以用於形成槽$卩之阻劑圖案做為遮罩而進行蝕 剡,能夠沿著憎部内壁形成一導電薄膜,例如一金屬薄膜。 因此,可容易地形成一外部端,其層結構之形成方式,可 22 3 12/發明説明韵補件)/93-()4/931 ϋ 1000 1339429 使得整個裝置被最外部導電薄膜覆蓋。 (第二具體例) 接著將說明本發明之第二具體例。 在本具體例之半導體裝置中,外部端的結構係以 式形成。如圖1 0所示,以第一導體層3 c ' 3 d從槽 升起到平坦gr的方式,形成第一導體層3 c、3 d之後 二與第三導體層彼此層合在一起,使得第一導體層 邊緣部可留置,外部端的整個表面構成覆蓋有第一 之外部端結構。 此種情況中,在第一導體層 3 b的外層上,設有 做為障壁層3a。 如上所述,導體層之形成方式,係使得槽部的周 暴露出,並製作成從槽部内壁升起到平坦部。因此 構造中,導線端的整·個表面都覆蓋有第一導體層, 導體層 3 c包含一嵌入於樹脂中的鎳層,使得第二 3c不會暴露至外部空氣。 半導體裝置所使用之導線架的製造方法中,當導 成時,係使用一電解電鍍製程,其中使用阻劑圖案 罩,將一金屬薄膜形成於槽部的内壁。 根據此方法,以憎部形成時之阻劑圖案做為遮罩 行電解電鍍。因此,能夠在槽部内壁上形成一導電 例如一金屬溥膜,以及形成一外部端,其層結構中 裝1被最外部導電薄膜覆蓋。 圖8與9顯示本發明第二具體例之導線架,而圖 31riv( fi〇i^)/93-04/93 I ϋ 1000 下列方 部内側 ,將第 3 b的一 導體層 一錄層 圍邊緣 ,在此 而第二 導體層 線部形 做為遮 ,而進 薄膜, ,整個 1 0顯 23 1339429 示包含此種導線架之半導體裝置。 此方法包含一步驟,以阻劑圖案做為遮罩形成一槽部之 後,將阻劑圖案縮小,使得導線架本體上環繞槽部之一表 面可稍微暴露出。 如圖8A至8C所示,從開始到槽部2形成之製造過程係 相同於圖4A至4C之第一具體例所說明之製造過程。如圖 8 D所示,以5 0 0 °C加熱3 0分鐘後,阻劑圖案R被缩小,以 形成阻劑圖案Rs,使槽部2的周圍部分暴露出。 之後,如圊9 A所示,阻劑圖案R s留置於原處,裝置被 浸入一含有磺酸鎳水溶液之電鍍溶液中,藉由電解電鍍的 方式形成障壁層3a之鎳層3a。此時,所形成之障壁層3a, 可沿著槽部2之内壁而達到槽部2周圍的平坦部。 接著,如圖9 B所示,第一導體層3 b之黃金層係相繼地 形成,並藉由非等向性蝕刻將平坦部中的第一導體層移除。 進一步地,如圖 9C所示,藉由電解電鍍,將第二導體 層3c之鎳層相繼地層合於第一導體層3b上。 進一步地,形成第三導體層3d之黃金層。 最後,如圖9D所示,移除阻劑圖案Rs。以此方式,形 成本發明第二具體例之導線架。 第二具體例之半導體裝置之導線架的組裝,係以相同於 第一具體例之方式進行。 如圖 10所示,在如此形成之半導體裝置中,整個表面 均以包含黃金層之第一導體層覆蓋。因此,以鎳製成之第 二導體層不會暴露至表面。據此,能夠形成一種穩定的半 24 312/發明說明書(補件)/93-04/93〗01000 1339429 導 體 裝 置 > 不 會 發 生 表 面 氧 化 5 壽 命 較 長 〇 由 於 設 置 有 障 壁 層 3 a, 即 使 以 溫 焊 接 在 第 三 導 體 層 上 進 行 打 線 接 合 5 也 不 可 能 會 使 第 — 導 體 層 與 導 線 架 本 體 產 生 反 應 〇 上 述 具 體 例 中 係 說 明 — 雙 極 性 電 晶 體 之 組 裝 〇 然 而 應 瞭 解 本 發 明 並 不 囿 限 於 上 述 離 散 元 件 〇 當 然 本 發 明 亦 可 應 用 於 I C及 LSI 丨。 如 上 述 說 明 > 根 據 本發明之: 導; 線 架 J 能 夠 形 成 一 精 、 可 靠 之 薄 型 半 導 體 裝 置 〇 根 據 本 發 明 之 導 線 架 之 製 造 方 法 > 由 於 金 屬 基 板 之 一 部 分 係 選 擇 性 地 、 輕度地· 蚀 刻: |而導線端係形成於此才曹 1部中 > 可 容 易 地 形 成 一 14 型 半 導 體 裝 置 〇 根 據 本 發 明 1 能 夠 提供一 •種丨 可 靠 性 之 薄 型 半 導 體 裝 0 根 據 本 發 明 之 半 導 體 裝 置 之 製 造 方 法 > 不 會 產 生 位 置 偏 移 可 以 高 產 率 組 裝 — 南 可 靠 度 之 薄 型 半 導 體 裝 置 0 本 發 明 不 限 於 上 述 具 體 例 與 說 明 0 熟 •心 本 技 藝 者 在 不 離 開 中 請 專 利 4Ί1 圍 之 敘 述 所 容 易 達 成 的 各 種 變 化 均 包 含 於 本 發 明 中 〇 [ 圆 式 簡 單 說 明 ] 圓 1 A至 1 D 顯 示 本 發 明 第 一 具 體 例 之 半 導 體 裝 置 固 1 A 係 為 上 視 圓 1 圖 1 B係‘ % ; 線 Α- A 所 繪 製 之 戠 面 圖 7 圖 1C 係 為 下 視 圖 而 圖 1 1: >係為沿線 B- B所繪製之戠面圖 圖 2 係 為 本 發 明 第 一 具 體 例 之 導 線 架 的 主 要 部 分 放 大 戠 W 2/發明說明I.丨丨:(補件)/93-04/93丨0100() 25 1339429 面圖; 圖 3彳i為本發明第一具體例之半導體裝置的概念示意 圖; 圖4 A至4 C係為本發明第一具體例之導線架的製造過程 圖; 圖5A至5D係為本發明第一具體例之導線架的製造過程 圖: 圖6 A至6 C係為本發明第一具體例之半導體裝置的製造 過程圊; 圖7A至7C係為本發明第一具體例之半導體裝置的製造 過程圖; 圖8 A至8 D係為本發明第二具體例之導線架的製造過程 圖; 圖9A至9D係為本發明第二具體例之導線架的製造過程 圖: 圖1 0顯示本發明第二具體例中所形成之半導體裝置: 及 圖11A至11C顯示習知半導體裝置。 (元件符號說明) 1 導線架本體 2 槽部 3a 障壁層 3b 第一導體層 3c 第二導體層 26 312/發明說明書(補件)/93-04/93101000 1339429 3d 第三導體層 10a 晶粒墊 10b 導線端 10c 導線端 11 半導體晶片 12 接合線 13 密封樹脂 14 膠帶 15 切片槽 16 切割刀片 6 1 島狀物 6 1 A 島狀物 6 2 導線端 6 2 A 導線端 63 導線端 6 3 A 導線端 72 半導體晶片 R 阻劑圖案
Rs 阻劑圖案 27
312/發明說明書(補件)/93-〇4/93101000

Claims (1)

1339429 曰修疋辞换頁| 1.2_______i 拾、申請專利範圍 OCT 1 2 2010 替換本 1 . 一種導線架,包含: 一導線架本體,包含一金屬製成之板狀本體; 一用於形成導線的槽部,其係以一預定深度形成於該導 線架本體表面上之一導線形成區域中;及 一具有一從該槽部側向突出到該導線架本體表面上而 與該表面接觸之部位的導線,該導線完全充填該槽部且係 由不同於該導線架本體之材料的材料所製成, 該導線包括:一形成於該槽部中之第一導體層;一形成 於該第一導體層上之第二導體層;及一形成於該第二導體 層上之第三導體層,其中該第一導體層係組裝至一組裝構 件,及該第三導體層係組裝至一半導體晶片之晶粒墊, 其中,該導線包括一用於抑制該導線架本體與該第一導 體層間之反應的障壁層,該障壁層係設置於該槽部之一部 分上而與在該槽部中的該導線架本體接觸,以及該障壁層 係由錄、鈦、嫣其中一種製成。 2. 如申請專利範圍第1項之導線架,其中,該第一導體 層覆蓋該槽部之整個内壁。 3. 如申請專利範圍第1項之導線架*其中,該第一與第 二導體層之一介面係位於該導線架本體表面之上。 4. 如申請專利範圍第1項之導線架,其中,該障壁層係 由鎳製成。 5. 如申請專利範圍第1項之導線架,其中,該第一導體 層係由可與焊錫一同形成合金之金屬製成。 28 93101000 1339429 6. 如申請專利範圍第1項之導線架,其中,該第一 層之膜厚為0.5至2/zm。 7. 如申請專利範圍第1項之導線架,其中,該第一 層包含一黃金層。 8. 如申請專利範圍第1項之導線架,其中,該第三 層包含一黃金層。 9. 如申請專利範圍第1項之導線架,其中,該第二 層包含一金屬層,而其主要成分為鎮。 1 0 . —種導線架之製造方法,包含: 一阻劑圖案形成步鄉,該阻劑圖案係在一包含一金 成之板狀本體之導線架本體表面上圖案化,使得一導 成區域可開放; 一導線形成用槽部形成步驟,當使用該阻劑圖案做 罩進行蝕刻時,於該導線架本體之形成有該阻劑圖案 的導線形成區域中形成預定深度的槽部; 一導線部形成步驟,形成一包含由不同於該導線架 之材料製成之複數導線的導線部,使得該導線可從該 連續地突出到該導線架本體表面上1該導線包括一障 層,用於抑制在一接合步驟中因熱所導致之該導線架 與該導線間的反應,該障壁層係設置於該槽部之一部 上,而與該導線架本體在該槽部接觸,以及該障壁層 鎳、鈦、鎢其中一種製成;及 一阻劑圖案縮小步驟,在使用該阻劑圖案做為遮罩 成該槽部之後,縮小該阻劑圊案,使得該導線架本體 93101000 導體 導體 導體 導體 屬製 線形 為遮 之惻 本體 槽部 壁 本體 分 係由 而形 之環 29 1339429 繞該槽部的表面可稍微暴露出 其中,該導線部形成步驟包括: ♦ . 一第一導體層形成步驟,在該槽部及其從已在該阻劑圖 案縮小步驟中縮小之阻劑圖案暴露出的周圍,形成一第一 導體層; 一第二導體層形成步驟,在該第一導體層上形成一第二 導體層,其層合方式係可使得該第一導體層之末端邊緣可 被留置;及 一第三導體層形成步驟,在該第二導體層上形成一第三 導體層。 1 1 .如申請專利範圍第1 0項之導線架之製造方法,其 中,該導線部形成步驟包括一電解電鍍步驟,使用該阻劑 圖案做為遮罩,在該槽部之内壁上形成一金屬薄膜。 1 2 .如申請專利範圍第1 0項之導線架之製造方法,其 中,該第二導體層形成步驟包括: 一薄導電膜形成步驟,在該第一導體層上形成一薄導電 膜;及 一回触(etch-back)步驟,藉由非等向性姓刻在該薄 導電膜上進行回ϋ。 1 3 .如申請專利範圍第1 0項之導線架之製造方法,其 中,該導線部形成步驟包括一第一至第三導體層形成步 驟,依序在該槽部中形成該第一至第三導體層,而該第一 與第二導體層之介面係位於該導線架本體表面之上。 1 4 .如申請專利範圍第1 0項之導線架之製造方法,其 30 93101000 1339429
線部形成步驟包括一障壁層形成步驟,在該第一 導體層與該槽部間形成一障壁層,用於抑制該導線架本體 與該第一導體層間的反應。 1 5 .如申請專利範圍第1 0項之導線架之製造方法,其 中,該槽部形成步驟包括一非等向性蝕刻步驟,用於形成 一槽,其截面為深度0.5至2. 5//m之矩形。
31 93101000 1339429 QEC. 2 2 测 替換頁 旧涵圖式 32 93101000
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101091896B1 (ko) * 2004-09-04 2011-12-08 삼성테크윈 주식회사 플립칩 반도체 패키지 및 그 제조방법
TWI253161B (en) * 2004-09-10 2006-04-11 Via Tech Inc Chip carrier and chip package structure thereof
JP2006093575A (ja) * 2004-09-27 2006-04-06 Hitachi Cable Ltd 半導体装置およびその製造方法
US7863102B2 (en) * 2008-02-22 2011-01-04 Stats Chippac Ltd. Integrated circuit package system with external interconnects within a die platform
KR100983341B1 (ko) 2008-08-05 2010-09-20 (주)하드램 디지털 마이크로미러 디바이스를 이용한 마킹 장치 및 방법
KR101001876B1 (ko) * 2008-09-19 2010-12-21 엘지이노텍 주식회사 반도체 패키지용 다열 리드리스 프레임 및 이를 이용한 반도체 패키지의 제조방법
KR101029028B1 (ko) * 2008-09-19 2011-04-19 엘지이노텍 주식회사 반도체 패키지용 다열형 리드리스 프레임 및 이를 이용한 반도체 패키지의 제조방법
KR101040136B1 (ko) * 2008-09-23 2011-06-09 엘지이노텍 주식회사 반도체 패키지용 다열 리드리스 프레임 및 이를 이용한 반도체 패키지의 제조방법
US8610156B2 (en) 2009-03-10 2013-12-17 Lg Innotek Co., Ltd. Light emitting device package
KR101047603B1 (ko) * 2009-03-10 2011-07-07 엘지이노텍 주식회사 발광 소자 패키지 및 그 제조방법
JP5271949B2 (ja) 2009-09-29 2013-08-21 ルネサスエレクトロニクス株式会社 半導体装置
JP2012028694A (ja) * 2010-07-27 2012-02-09 Panasonic Corp 半導体装置
CN102569099B (zh) * 2010-12-28 2014-12-10 万国半导体(开曼)股份有限公司 一种倒装芯片的封装方法
US8877555B2 (en) * 2012-11-16 2014-11-04 Alpha & Omega Semiconductor, Inc. Flip-chip semiconductor chip packing method
US20140261661A1 (en) * 2013-03-13 2014-09-18 Gtat Corporation Free-standing metallic article with overplating
JP2015090350A (ja) * 2013-11-07 2015-05-11 旭化成エレクトロニクス株式会社 磁気センサ及び磁気センサ装置、磁気センサの製造方法
JP6681165B2 (ja) * 2014-12-27 2020-04-15 マクセルホールディングス株式会社 半導体装置用基板、半導体装置用基板の製造方法、及び半導体装置
CN108884984B (zh) * 2016-03-15 2021-04-16 昕诺飞控股有限公司 细长引线框架和制造细长引线框架的方法
CN110970329B (zh) * 2019-11-27 2024-03-29 丽智电子(南通)有限公司 一种基于可溶解的保护膜制备晶体二极管的方法
CN111554653A (zh) * 2020-04-13 2020-08-18 东莞链芯半导体科技有限公司 引线框架制作方法及引线框架
CN113241338B (zh) * 2021-07-09 2021-10-19 东莞市春瑞电子科技有限公司 一种无引线预塑封半导体封装支架制备方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56148846A (en) * 1980-04-22 1981-11-18 Nec Corp Manufacture of circuit pattern
US4935803A (en) * 1988-09-09 1990-06-19 Motorola, Inc. Self-centering electrode for power devices
US5440805A (en) * 1992-03-09 1995-08-15 Rogers Corporation Method of manufacturing a multilayer circuit
JPH06148661A (ja) * 1992-11-12 1994-05-27 Matsushita Electric Ind Co Ltd 表示装置用基板の製法
US5976912A (en) 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US6376921B1 (en) * 1995-11-08 2002-04-23 Fujitsu Limited Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame
US6329711B1 (en) * 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
US6072239A (en) * 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
JP3007833B2 (ja) * 1995-12-12 2000-02-07 富士通株式会社 半導体装置及びその製造方法及びリードフレーム及びその製造方法
KR0185512B1 (ko) * 1996-08-19 1999-03-20 김광호 칼럼리드구조를갖는패키지및그의제조방법
JP3877401B2 (ja) 1997-03-10 2007-02-07 三洋電機株式会社 半導体装置の製造方法
JPH1167838A (ja) * 1997-08-22 1999-03-09 Matsushita Electric Ind Co Ltd バンプ付電子部品の製造方法
US6759597B1 (en) * 1998-02-02 2004-07-06 International Business Machines Corporation Wire bonding to dual metal covered pad surfaces
JPH11238840A (ja) 1998-02-19 1999-08-31 Oki Electric Ind Co Ltd リードフレーム
JP3764587B2 (ja) * 1998-06-30 2006-04-12 富士通株式会社 半導体装置の製造方法
JP3455685B2 (ja) * 1998-11-05 2003-10-14 新光電気工業株式会社 半導体装置の製造方法
JP4362163B2 (ja) 1999-04-06 2009-11-11 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP4464527B2 (ja) * 1999-12-24 2010-05-19 大日本印刷株式会社 半導体搭載用部材およびその製造方法
JP2001230345A (ja) 2000-02-17 2001-08-24 Sumitomo Metal Mining Co Ltd 半導体装置及びその製造方法並びにその製造に用いられるリードフレーム
JP3621869B2 (ja) 2000-06-15 2005-02-16 新光電気工業株式会社 半導体装置及びその製造方法
JP2003078094A (ja) * 2001-08-31 2003-03-14 Shinko Electric Ind Co Ltd リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法
JP2007051336A (ja) * 2005-08-18 2007-03-01 Shinko Electric Ind Co Ltd 金属板パターン及び回路基板の形成方法

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