TWI243419B - A barrier layer for a processing element and a method of forming the same - Google Patents

A barrier layer for a processing element and a method of forming the same Download PDF

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TWI243419B
TWI243419B TW093107839A TW93107839A TWI243419B TW I243419 B TWI243419 B TW I243419B TW 093107839 A TW093107839 A TW 093107839A TW 93107839 A TW93107839 A TW 93107839A TW I243419 B TWI243419 B TW I243419B
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processing element
layer
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patent application
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TW200425318A (en
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Gary Escher
Mark A Allen
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32458—Vessel
    • H01J37/32477—Vessel characterised by the means for protecting vessels or internal parts, e.g. coatings
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H01J37/32559—Protection means, e.g. coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Analytical Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Materials Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)
  • Formation Of Insulating Films (AREA)

Description

1243419 五、發明說明（1) ' ^ 一、【發明所屬之技術領域】 本發明係關於處理元件用之障壁層及其形成方法，尤 有關於處理包含有黏著層和保護層之元件用之障壁層及其 形成方法。 / 二、【 半 )的製 積材料 言，藉 之能量 且，加 以於預 定組之 於特定 基板去 雖 的形成 積等） 表面被 漿處理 逐漸退 為 漿處理 先前技術】 導體產業中 造通常使用 至基板所需 由加熱電子 ，於真空條 熱後的電子 定條件下（ 氣體來產生 處理進行於 除或沉積處 然一群帶電 對實施電漿 於基板表面 暴露於物理 系統中被暴 化及最後系 了使由暴露 系統的成分 積體電 電漿以 之表面 至足以 件下將 可具有 如處理 一群帶 處理室 理，於 荷物種 處理系 上為必 及化學 露的成 統的完 於處理 (已知
路（1C， 產生及協 化學於電 維持與供 電漿形成 足以維持 室内壓力 電荷的物 内（如餘 此將材料 (如離子 統的功能 需，於處 活性的電 分之腐蝕 全故障。 電漿遭受 遭受暴露 integrated c i rcu i ts 助自基板去除材料及沉 漿反應器内。一般而 應處理氣體 於電漿反應 分離的碰撞 、氣體流速 種及化學反 刻處理，於 加至基板） 等）及化學 (即材料蝕 理室内側上 漿及（及時） 可導致電賧 離子化碰撞 裔内。而 之能量及所 等）選擇特 應性物種適 此將材料自 〇 反應性物種 刻、材料沉 的其他成份 可腐蝕。電 處理表現的 的損害減到最小，將電 於處理電漿）以保護障
第6頁 !243419 五 、發明說明（2) 化紹表 將一個消 或碳化 I擔更大 面材料使 至形成於 或由於保 成分的消 維護可導 費用，其 ^貪佈。例如可將由鋁製造的成分電鍍以產生氧 ^ α其對電漿更有抵抗力。於另一個實例中，可 發:或可替換的成分（如由矽、石英、鋁土、石炭 、衣造者）插入處理室内以保護於經常替換期間 本之更貴重的成分之表面。此外，希望選擇表 不需要的污染物、雜質等之導入處理電漿及可能 基板上的裝置減至最小。 匕 ^ 於兩個情況中，保護重層不可避免的失敗， 護障壁的完善或製造保護障壁的完善，和可替換 耗品本質要求電漿處理系統的頻繁維護。此頻繁 致與電漿處理停工期及新電漿處理室成分相關的 可為極南。 三、【發明内容】 茲說明障壁層及其形成方法。 用於進行一處理之處理系統中處理元件上之保護障壁 包含有：結合層連結於處理元件，其中結合層包含有利用 電漿電解氧化形成的層；及保護層連結於結合層及安裝成 暴露於處理。 形成用於進行一處理之處理系統中處理元件上之保護 障壁的方法包含有··運用結合層至處理元件’其中結合層 之運用包含有電漿電解氧化；及運用保護層至結合層。 四、【實施方式】
1243419 五、發明說明（3) 將電漿處理系統1，如能夠電漿蝕刻者，描述在圖1 中，包括處理室10、上組件2〇、上壁24、支撐基板35用之 基板支架30、及連結於真空泵（未示）之抽吸導管40以提供 處理室1 0中減壓環境1 1。例如處理室丨〇可促進毗鄰基板3 5 的處理空間1 2中處理電漿的形成。可將電漿處理系統1配 置成處理各種基板（即2 〇 〇毫米基板、3 0 0毫米基板、或更 大）。 於說明的實施例中，上組件2 〇能包括至少一蓋子、氣 體射入配件、及上電極阻抗配合網路。例如可將上壁2 4配
第8頁 1243419
放射。 -1 η ί ί 5: : 〇可例如更包括由連結於基板支架3 0及處理 !； ^伸、、伯晨2環繞的垂直平移裝置50，及用來密封垂直 二移f置5〇以和處理室1 〇中減壓環境11隔開。料，可將 :縮，擋板54例如連結於基板1架3〇及肖來保護伸縮 ::處理電漿。或纟，基板支架不包括垂直平移裝 縮囊。 可進v將基板支架3 0連結於聚焦環6 〇，及視情況， 播板環56。再者，阻障板58可例如延伸環繞基板支架⑽ 周圍。 可將基板35例如經由機械臂基板轉移系統通過狹縫閥 (未圖示）及處理室穿通孔（未圖示）移入及移出處理室 1 〇，於此將其由位於基板支架30内之基板升起栓（未圖示 )接受及由位於其中的裝置機械上平移。—旦將基板35自 基板轉移系統接受後，將其降低至基板支架3〇的上表面。 例如可將基板3 5經由靜電夾緊系統固定至基板支架 ^。此外，例如基板支架30可更包括冷卻系統，包括接受 來自基板支架3 0的熱及轉移熱至熱交換器系統（未圖示 \二或當加熱，轉移熱自熱交換器系統至基板支架3 0的再 =% ~部劑流。而且，可將氣體例如經由背部氣體系統傳 遞至基板35的背部以改進基板35和基板支架3〇之間的氣體 熱傳導性。當基板的溫度控制必需在升高或減低的溫 又日守可運用此系統。在其它實施例中，可包括加熱元件， 如電阻加熱元件，或熱電子加熱器/冷卻器。
第9頁 1243419
五、發明說明（5) 妬雷ί說明的實施例中（圖1中所示），基板支架3〇可包 祜冤極（未圖示），經此將RF電力連結於處理空間12 ^處，電漿。例如可將基板支架30、經由RF電力自rf產生 :輸阻抗配合網路（未圖示）至基板支架 得輸KF電力電偏壓於RF電壓。RF偏壓可用於加熱電 m持電漿。.於此配置巾，系統可操作為反應性離子姓 = ，reactive i〇n etch)反應器，其中處理室和上 j =體射入電極作為接地表面。一個RF偏壓典型的頻率可 能靶圍從1兆赫至100兆赫，例如13· 56兆赫。電漿處理用 之評系統對熟悉本技藝者而言為已熟知。 '里用 或=’可將形成於處理空間丨2中的處理電漿利用平行 ，、電谷耦合電漿（ccp，capacitively ⑶叩led piwma 源電感輕合電聚（ICP， inductively coupled pUsma )源、變壓器耦合電漿（TCP, transformer ⑶up led pi asma )源、其任意組合，及有或無Dc磁鐵系統 而形成:或者’可將形成於處理空間1 2中的處理電漿利用 電子方疋加速為共振（Ecr，electron cyclotron resonance )而形成。於再另一實施例中，將處理空間12 中的處理電漿自螺旋波的發射而形成。於再另一實施例 中’將處理空間1 2中的處理電漿自傳播的表面波而形 成。 ^參知圖1 ’電漿處理設備1包括一或多個處理元 件’可將其各暴露於處理空間1 2中的處理電漿，及因此於 處理期間叉到可能的腐蝕。例如一或多個處理元件可包括
第ίο頁 1243419 五、發明說明（6) ' -------- 電極板、、、"拉、， 光風、* ’儿積擋板、處理室内襯、伸縮囊擋板、阻障板、 予視窗沉積擋板、擋環、聚焦環等。為了減輕暴 J里 jr 南 H ^ 卞叉處理電漿和基板的任何隨後污染的腐蝕，將 元件覆蓋保護障壁。 ^處理 於一實施例中，如描述於圖2，一個處理元件丨〇 〇包括 一個保護障壁11 〇，其具有抵抗電漿腐蝕之保護層1 2 0，及 黏合層1 3 0，其改善保護層丨2 〇對處理元件丨〇 〇的黏附力以 減輕由保遵層失效可能的處理污染。 保護層120可例如包括至少AiJ3和\〇3的當中一個。於 本發明另一個實施例中，保護層包括丨丨I行元素（週期表的 ¥ 第I Π行）及鑭系元素之至少一者。於本發明另一個實施例 中，III行元素包括釔、銃、和鑭之至少一者。於本發明 另一個貫施例中’鋼糸元素包括飾、鋼、和銷之至少一 者。於本發明另一個實施例中，形成保護層之化合物包括 氧化釔（Y2 03 )、Sc2 03、Sc2F3、YF3、La2 03、Ce02、Eu2 03、和
Dy03之至少一者。 黏合層為例如Keroni te (表面塗層處理，市面上可購 自Keron ite有限公司，先進表面技術、郵政信箱70 0，
Granta Park，Great Abington,劍橋CB1 6ZY，英國）。 一般而言，黏合層可包括三層，包括：稀過渡層在（金屬） 處理元件和陶瓷之間、提供堅硬的密集主要層、和更軟、 更多孔的外層。更軟、更多孔的外層（其典型包括高達1 0 到2 0 %總黏合層厚度）可错抛光而去除以便提供黏合表面 以塗佈保護層。因為黏合層（如所描述）為轉換層，它由於
第11頁 1243419 五、發明說明（7) 分子黏合擁有改善的黏附力性質。 口 圖3呈現在處理元件上形成保護.障壁之方法。將方法 壬現於流程圖5 0 0中，以步驟5 1 0開始，其中將黏合層塗佈 ^ =理元件的至少一個表面。可將處理元件例如使用機器 製造、拋光、和研磨之至少一者而製造。例如上述之處理 凡=可根據於機械圖上提出的規格，利用習見技術包括銑 ，等 > 用機器製造。利用例如銑床之用機器製造成分的技 術對熟悉機械製造此材料的技藝者為已熟知。處理元件可 u括至屬以矽為基本的材料、和陶瓷之至少一者。處理 元件可例如包括鋁。黏合層可包括“⑺心“。例如可將 yonite層經由電漿電解氧化作用（ρΕ〇， = 形成，其包括遮蔽處理元件和 ΐ Σ換：屬表S' :化學電解浴以藉於液體電解質中電漿放 电艾換孟屬表面成一堅硬、宓隹 藉拋光可將黏合層中的（第ϋ:者'陶瓷。視情況’ 在步糊中，將保孔的層去除。 於是，要 陶麵塗佈技藝者r已之術形成’其對熟悉 護障壁可進-步包括拋光熱喷霧塗展—貫施例形成保 層可包括應用沙紙至被喷霧的表面=。例如拋光熱喷霧塗 雖然僅已將本發明的某些例示 熟悉本技藝者將輕易地了解於例示告&列於上詳細描述， 能的而不實質上偏離本發明新穎的1，例中許多修改是可 將所有此類修改包括於本發明的範圍=和優點 第]2頁 1243419 圖式簡單說明 五' 【圖式簡單說明】 圖1說明根據本發明之實施例一電漿處理系統之示意 方塊圖； 圖2呈現圖1中所示電漿處理系統中一部份處理元件之 放大橫剖面圖；及 圖3呈現根據本發明之實施例於電漿處理系統中的處 理元件上形成保護層之方法。 % 元件符號說明： 卜電漿處理系統 1 0〜處理室 11〜減壓環境 1 2〜處理空間 1 4〜沉積擋板 1 6〜光學視埠 17〜光學視窗 1 8〜光學視窗沉積擋板 1 9〜光學視窗凸緣 2 0〜上組件 24〜上壁 3 0〜基板支架 3 5〜基板 4 0〜抽吸導管 5 0〜垂直平移裝置
第13頁 1243419 圖式簡單說明 5 2〜伸縮囊 5 4〜伸縮囊擋板 5 6〜擋板環 5 8〜阻障板 6 0〜聚焦環 7 0〜開口 I 0 0〜處理元件 II 0〜保護障壁 1 2 0〜保護層 1 3 0〜黏合層

Claims (1)

1243419 六、申請專利範圍 1. 一種處理元件上的保護障壁，用於實施一處理之處理 系統中，包含： 一黏合層，連結於該處理元件，其中該黏合層包含利 用電漿電解氧化而形成的層；以及 一保護層，連結於該黏合層及用來暴露於該處理。 2. 如申請專利範圍第1項之處理元件上的保護障壁，其 中，該黏合層包含Keronite。 .如申請專利範圍第2項之處理元件上的保護障壁，其 主要層、及一外層 中，該Keronite包含一過渡層 4.如申請專利範圍第3項之處理元件上的保護障壁，其 中，在利用拋光、研磨、及喷粒之至少一種方式將該外層 的至少一部份去除後，將該保護層連結於該黏合層。 5.如申請專利範圍第1項之處理元件上的保護障壁，其 中，該保護層包括含有I I I行元素及鑭系元素之至少一者 的化合物。 6. 如申請專利範圍第5項之處理元件上的保護障壁，其 中，該I I I行元素包括紀、銃、和_之至少一者。 7. 如申請專利範圍第5項之處理元件上的保護障壁，其
第15頁 1243419 ’、、申請專利範圍 Λ鑭系凡素包括鈽、鏑、和銪之至少—者 中如申請專利範圍第丨項之處理元件 中，4 Θ不丄$ <慝理兀件上的保罐昧 甲该保護層包括AW、氧化紀ΓΥ0保❸早 、I^ η 3 虱化釔（Y2〇3)、Sc2(L、ς e 2、Eu2〇3、和j)y〇3之至少一者 YF3、La9 壁，其 SC2〇3、Sc2F3、 卜，？虚=”第1項之處理元件上的保護 的材料、和陶瓷之 中 至少一者 處理元件包括金屬：口基Γ俯護障壁’其 第1項之處理元件上的保護障*，其 中， 該處第1項之處理元件上的保護障 壁，其 12. -严：種ΐ處理元件上形成保護障壁的方法，庫用於每 處理之處理系統中，包含： 應用於貫施 塗佈一黏合層至該處理 包含電漿電解氧化作用；以及件，、中°亥黏5層之塗佈 塗佈一保護層至該黏合層。 ^ + 士申°月專利範圍第1 2項之在處理元件上形成伴1 ^ 的方法’其中該黏合層包含Keronite。 /成保遠障壁
第16頁 1243419 六、申請專利範圍 14.如申請專利範圍第1 3項之在處理元件上形成保護障壁 的方法，其中，該Keronite包含一過渡層、一主要層、及 一外層。 15.如申請專利範圍第1 4項之在處理元件上形成保護障壁 的方法，其中，利用拋光、研磨、及喷粒之至少一種方式 將該外層去除。
16.如申請專利範圍第1 2項之在處理元件上形成保護障壁 的方法，其中，該保護層包含一化合物含有I I I行元素及 鑭系元素之至少一者。 17.如申請專利範圍第1 6項之在處理元件上形成保護障壁 的方法，其中，該I I I行元素包括記、銃、和鑭之至少一 者0 18.如申請專利範圍第1 6項之在處理元件上形成保護障壁 的方法，其中，該鑭系元素包括鈽、鏑、和銪之至少一 者0 19.如申請專利範圍第1 2項之在處理元件上形成保護障壁 的方法，其中，該保護層包括A 12 03、氧化纪（Y2 03 )、S c2 03 ' Sc2F3、YF3、La2 03、Ce02、Eu2 03、和Dy03 之至少一者。
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WO2004095532A2 (en) 2004-11-04
US7291566B2 (en) 2007-11-06
US20060183344A1 (en) 2006-08-17
KR20050120681A (ko) 2005-12-22
JP2007524993A (ja) 2007-08-30
JP4532479B2 (ja) 2010-08-25
TW200425318A (en) 2004-11-16
KR101016913B1 (ko) 2011-02-22

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