TW591447B - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
- Publication number
- TW591447B TW591447B TW091114846A TW91114846A TW591447B TW 591447 B TW591447 B TW 591447B TW 091114846 A TW091114846 A TW 091114846A TW 91114846 A TW91114846 A TW 91114846A TW 591447 B TW591447 B TW 591447B
- Authority
- TW
- Taiwan
- Prior art keywords
- unit
- trunk
- ground
- line
- main line
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract description 39
- 239000002184 metal Substances 0.000 description 57
- 229910052751 metal Inorganic materials 0.000 description 57
- 230000004913 activation Effects 0.000 description 28
- 238000010586 diagram Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 8
- 238000009826 distribution Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 2
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 2
- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 235000015170 shellfish Nutrition 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- RDYMFSUJUZBWLH-UHFFFAOYSA-N endosulfan Chemical group C12COS(=O)OCC2C2(Cl)C(Cl)=C(Cl)C1(Cl)C2(Cl)Cl RDYMFSUJUZBWLH-UHFFFAOYSA-N 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009396 hybridization Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002014532A JP2003218210A (ja) | 2002-01-23 | 2002-01-23 | 半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW591447B true TW591447B (en) | 2004-06-11 |
Family
ID=19191884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW091114846A TW591447B (en) | 2002-01-23 | 2002-07-04 | Semiconductor integrated circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6759698B2 (enExample) |
| JP (1) | JP2003218210A (enExample) |
| KR (1) | KR100475504B1 (enExample) |
| DE (1) | DE10244232A1 (enExample) |
| TW (1) | TW591447B (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6969952B2 (en) * | 2003-08-01 | 2005-11-29 | Hewlett-Packard Development Company, L.P. | System and method for automatically routing power for an integrated circuit |
| US7448012B1 (en) | 2004-04-21 | 2008-11-04 | Qi-De Qian | Methods and system for improving integrated circuit layout |
| JP4094614B2 (ja) | 2005-02-10 | 2008-06-04 | エルピーダメモリ株式会社 | 半導体記憶装置及びその負荷試験方法 |
| JP2006228954A (ja) * | 2005-02-17 | 2006-08-31 | Matsushita Electric Ind Co Ltd | 半導体装置とそのレイアウト設計方法 |
| JP2008103587A (ja) | 2006-10-20 | 2008-05-01 | Matsushita Electric Ind Co Ltd | 半導体集積回路の設計方法、半導体集積回路装置、並びに、電子装置 |
| US20090126859A1 (en) * | 2007-11-16 | 2009-05-21 | Cadwallader Robert J | Process for producing glass laminates |
| KR101012437B1 (ko) * | 2010-07-26 | 2011-02-08 | 주식회사 화성 | 개폐수단을 가지는 통신장비 안치용 랙 |
| US8819610B2 (en) | 2013-01-09 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and layout of an integrated circuit |
| CN106024780B (zh) * | 2016-07-14 | 2019-03-01 | 王培林 | 功率器件及其制备方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ATE53709T1 (de) * | 1984-06-19 | 1990-06-15 | Siemens Ag | In c-mos-technik realisierte basiszelle. |
| JPS6114734A (ja) * | 1984-06-29 | 1986-01-22 | Fujitsu Ltd | 半導体集積回路装置及びその製造方法 |
| US5410173A (en) * | 1991-01-28 | 1995-04-25 | Kikushima; Ken'ichi | Semiconductor integrated circuit device |
| JP3144967B2 (ja) * | 1993-11-08 | 2001-03-12 | 株式会社日立製作所 | 半導体集積回路およびその製造方法 |
| US5698873A (en) * | 1996-03-08 | 1997-12-16 | Lsi Logic Corporation | High density gate array base cell architecture |
| JPH10150175A (ja) | 1996-11-19 | 1998-06-02 | Toshiba Corp | 半導体集積回路およびその製造方法 |
| JPH10189749A (ja) | 1996-12-27 | 1998-07-21 | Toshiba Corp | 半導体集積回路装置、半導体集積回路装置の多電源供給方法、半導体集積回路装置の多電源供給プログラムを記録した機械読み取り可能な記録媒体 |
| JPH1131803A (ja) | 1997-07-10 | 1999-02-02 | Oki Electric Ind Co Ltd | ゲートアレイ |
| JPH11224901A (ja) | 1998-02-05 | 1999-08-17 | Toshiba Corp | 複数電源混在回路、そのレイアウト方法、及びそのレイアウトプログラムを記録したコンピュータ読みとり可能な記録媒体 |
| JP3819186B2 (ja) * | 1999-09-22 | 2006-09-06 | 株式会社東芝 | スタンダードセル、半導体集積回路およびそのレイアウト方法 |
| US6766496B2 (en) * | 2001-06-01 | 2004-07-20 | Virtual Silicon Technology, Inc. | Method and apparatus for integrated circuit design with a software tool |
-
2002
- 2002-01-23 JP JP2002014532A patent/JP2003218210A/ja active Pending
- 2002-07-04 TW TW091114846A patent/TW591447B/zh not_active IP Right Cessation
- 2002-07-12 US US10/193,250 patent/US6759698B2/en not_active Expired - Fee Related
- 2002-08-16 KR KR10-2002-0048322A patent/KR100475504B1/ko not_active Expired - Fee Related
- 2002-09-23 DE DE10244232A patent/DE10244232A1/de not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| US20030136977A1 (en) | 2003-07-24 |
| JP2003218210A (ja) | 2003-07-31 |
| US6759698B2 (en) | 2004-07-06 |
| KR100475504B1 (ko) | 2005-03-10 |
| KR20030064249A (ko) | 2003-07-31 |
| DE10244232A1 (de) | 2003-08-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100676980B1 (ko) | 집적 회로 및 집적 회로의 도전체 레이아웃 설계 방법 | |
| TW480669B (en) | Standard cell, standard cell array, and system and method for placing and routing standard cells | |
| TW591447B (en) | Semiconductor integrated circuit | |
| JP2004046962A5 (enExample) | ||
| US12341093B2 (en) | Method for protecting anti-fuse cell | |
| JPS58207666A (ja) | 既拡散集積回路とその接続方法 | |
| TWI750997B (zh) | 半導體結構及其形成方法 | |
| JP3115787B2 (ja) | ポリセル集積回路 | |
| JPH0494556A (ja) | 集積回路のセルレイアウト方法 | |
| TW451457B (en) | Method to optimize the placement design by adjusting the reference routing | |
| JPH04137651A (ja) | スタンダード・セル方式の半導体集積回路 | |
| JP3224885B2 (ja) | 集積回路装置及びその設計方法 | |
| JPH06140607A (ja) | 半導体集積回路 | |
| JP2002190572A5 (enExample) | ||
| JPH0556864B2 (enExample) | ||
| US6912703B2 (en) | Structure of integrated circuit standard cell library for reducing power supply voltage fluctuation | |
| JP3257525B2 (ja) | 半導体集積回路装置 | |
| TW437056B (en) | Semiconductor integrated circuit | |
| JPH03209745A (ja) | スタンダード・セル方式のレイアウト方法 | |
| CN105825881B (zh) | 记忆体 | |
| JP2830781B2 (ja) | マスタスライス型ゲートアレイ | |
| CN117709283B (zh) | 版图的布局方法、装置和集成电路版图结构 | |
| JP2007059043A5 (enExample) | ||
| TWI521533B (zh) | 由陣列階層隔開之裝置階層中具解碼裝置之記憶體裝置結構 | |
| JPH0794587A (ja) | 半導体装置、半導体設計方法及びその設計装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |