KR100475504B1 - 반도체 집적 회로 - Google Patents

반도체 집적 회로 Download PDF

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Publication number
KR100475504B1
KR100475504B1 KR10-2002-0048322A KR20020048322A KR100475504B1 KR 100475504 B1 KR100475504 B1 KR 100475504B1 KR 20020048322 A KR20020048322 A KR 20020048322A KR 100475504 B1 KR100475504 B1 KR 100475504B1
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KR
South Korea
Prior art keywords
trunk
cell
ground
power supply
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2002-0048322A
Other languages
English (en)
Korean (ko)
Other versions
KR20030064249A (ko
Inventor
다나카겐이치
Original Assignee
미쓰비시덴키 가부시키가이샤
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Application filed by 미쓰비시덴키 가부시키가이샤 filed Critical 미쓰비시덴키 가부시키가이샤
Publication of KR20030064249A publication Critical patent/KR20030064249A/ko
Application granted granted Critical
Publication of KR100475504B1 publication Critical patent/KR100475504B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR10-2002-0048322A 2002-01-23 2002-08-16 반도체 집적 회로 Expired - Fee Related KR100475504B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002014532A JP2003218210A (ja) 2002-01-23 2002-01-23 半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム
JPJP-P-2002-00014532 2002-01-23

Publications (2)

Publication Number Publication Date
KR20030064249A KR20030064249A (ko) 2003-07-31
KR100475504B1 true KR100475504B1 (ko) 2005-03-10

Family

ID=19191884

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-0048322A Expired - Fee Related KR100475504B1 (ko) 2002-01-23 2002-08-16 반도체 집적 회로

Country Status (5)

Country Link
US (1) US6759698B2 (enExample)
JP (1) JP2003218210A (enExample)
KR (1) KR100475504B1 (enExample)
DE (1) DE10244232A1 (enExample)
TW (1) TW591447B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6969952B2 (en) * 2003-08-01 2005-11-29 Hewlett-Packard Development Company, L.P. System and method for automatically routing power for an integrated circuit
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
JP4094614B2 (ja) 2005-02-10 2008-06-04 エルピーダメモリ株式会社 半導体記憶装置及びその負荷試験方法
JP2006228954A (ja) * 2005-02-17 2006-08-31 Matsushita Electric Ind Co Ltd 半導体装置とそのレイアウト設計方法
JP2008103587A (ja) 2006-10-20 2008-05-01 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法、半導体集積回路装置、並びに、電子装置
US20090126859A1 (en) * 2007-11-16 2009-05-21 Cadwallader Robert J Process for producing glass laminates
KR101012437B1 (ko) * 2010-07-26 2011-02-08 주식회사 화성 개폐수단을 가지는 통신장비 안치용 랙
US8819610B2 (en) 2013-01-09 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and layout of an integrated circuit
CN106024780B (zh) * 2016-07-14 2019-03-01 王培林 功率器件及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR860000712A (ko) * 1984-06-29 1986-01-30 후지쑤 가부시끼가이샤 반도체 집적회로 및 그 회로 패턴 설계방법
KR20010030457A (ko) * 1999-09-22 2001-04-16 니시무로 타이죠 스탠다드 셀, 반도체 집적 회로 및 그 레이아웃 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE53709T1 (de) * 1984-06-19 1990-06-15 Siemens Ag In c-mos-technik realisierte basiszelle.
US5410173A (en) * 1991-01-28 1995-04-25 Kikushima; Ken'ichi Semiconductor integrated circuit device
JP3144967B2 (ja) * 1993-11-08 2001-03-12 株式会社日立製作所 半導体集積回路およびその製造方法
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
JPH10150175A (ja) 1996-11-19 1998-06-02 Toshiba Corp 半導体集積回路およびその製造方法
JPH10189749A (ja) 1996-12-27 1998-07-21 Toshiba Corp 半導体集積回路装置、半導体集積回路装置の多電源供給方法、半導体集積回路装置の多電源供給プログラムを記録した機械読み取り可能な記録媒体
JPH1131803A (ja) 1997-07-10 1999-02-02 Oki Electric Ind Co Ltd ゲートアレイ
JPH11224901A (ja) 1998-02-05 1999-08-17 Toshiba Corp 複数電源混在回路、そのレイアウト方法、及びそのレイアウトプログラムを記録したコンピュータ読みとり可能な記録媒体
US6766496B2 (en) * 2001-06-01 2004-07-20 Virtual Silicon Technology, Inc. Method and apparatus for integrated circuit design with a software tool

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR860000712A (ko) * 1984-06-29 1986-01-30 후지쑤 가부시끼가이샤 반도체 집적회로 및 그 회로 패턴 설계방법
KR20010030457A (ko) * 1999-09-22 2001-04-16 니시무로 타이죠 스탠다드 셀, 반도체 집적 회로 및 그 레이아웃 방법

Also Published As

Publication number Publication date
US20030136977A1 (en) 2003-07-24
JP2003218210A (ja) 2003-07-31
US6759698B2 (en) 2004-07-06
KR20030064249A (ko) 2003-07-31
TW591447B (en) 2004-06-11
DE10244232A1 (de) 2003-08-07

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