KR860000712A - 반도체 집적회로 및 그 회로 패턴 설계방법 - Google Patents

반도체 집적회로 및 그 회로 패턴 설계방법

Info

Publication number
KR860000712A
KR860000712A KR1019850004145A KR850004145A KR860000712A KR 860000712 A KR860000712 A KR 860000712A KR 1019850004145 A KR1019850004145 A KR 1019850004145A KR 850004145 A KR850004145 A KR 850004145A KR 860000712 A KR860000712 A KR 860000712A
Authority
KR
South Korea
Prior art keywords
semiconductor integrated
design method
pattern design
circuit
integrated circuit
Prior art date
Application number
KR1019850004145A
Other languages
English (en)
Other versions
KR900000202B1 (ko
Inventor
노부히꼬 아네하
시게노리 바바
Original Assignee
후지쑤 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쑤 가부시끼가이샤 filed Critical 후지쑤 가부시끼가이샤
Publication of KR860000712A publication Critical patent/KR860000712A/ko
Application granted granted Critical
Publication of KR900000202B1 publication Critical patent/KR900000202B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/923—Active solid-state devices, e.g. transistors, solid-state diodes with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1019850004145A 1984-06-29 1985-06-12 반도체 집적회로 및 그 회로 패턴 설계방법 KR900000202B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59-135410 1984-06-29
JP59135410A JPS6114734A (ja) 1984-06-29 1984-06-29 半導体集積回路装置及びその製造方法

Publications (2)

Publication Number Publication Date
KR860000712A true KR860000712A (ko) 1986-01-30
KR900000202B1 KR900000202B1 (ko) 1990-01-23

Family

ID=15151074

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850004145A KR900000202B1 (ko) 1984-06-29 1985-06-12 반도체 집적회로 및 그 회로 패턴 설계방법

Country Status (6)

Country Link
US (1) US4701778A (ko)
EP (1) EP0167365B1 (ko)
JP (1) JPS6114734A (ko)
KR (1) KR900000202B1 (ko)
CA (1) CA1219380A (ko)
DE (1) DE3571102D1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100475504B1 (ko) * 2002-01-23 2005-03-10 미쓰비시덴키 가부시키가이샤 반도체 집적 회로

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61191047A (ja) * 1985-02-20 1986-08-25 Toshiba Corp 半導体集積回路装置
JPH0785490B2 (ja) * 1986-01-22 1995-09-13 日本電気株式会社 集積回路装置
US5150309A (en) * 1987-08-04 1992-09-22 Texas Instruments Incorporated Comprehensive logic circuit layout system
JPH01239871A (ja) * 1988-03-19 1989-09-25 Rohm Co Ltd Ｌｓｉのレイアウト方法
JP2508206B2 (ja) * 1988-07-28 1996-06-19 日本電気株式会社 集積回路装置
DE69031609T2 (de) * 1989-04-19 1998-03-12 Seiko Epson Corp Halbleiteranordnung
JP2573414B2 (ja) * 1990-11-21 1997-01-22 株式会社東芝 半導体集積回路製造方法
JP2509755B2 (ja) * 1990-11-22 1996-06-26 株式会社東芝 半導体集積回路製造方法
JP3027990B2 (ja) * 1991-03-18 2000-04-04 富士通株式会社 半導体装置の製造方法
JP2742735B2 (ja) * 1991-07-30 1998-04-22 三菱電機株式会社 半導体集積回路装置およびそのレイアウト設計方法
JP2757647B2 (ja) * 1992-01-27 1998-05-25 日本電気株式会社 メッキ膜厚均一化方式
US7068270B1 (en) * 1994-12-02 2006-06-27 Texas Instruments Incorporated Design of integrated circuit package using parametric solids modeller
US5798541A (en) * 1994-12-02 1998-08-25 Intel Corporation Standard semiconductor cell with contoured cell boundary to increase device density
US5682323A (en) 1995-03-06 1997-10-28 Lsi Logic Corporation System and method for performing optical proximity correction on macrocell libraries
US5768146A (en) * 1995-03-28 1998-06-16 Intel Corporation Method of cell contouring to increase device density
GB2300983A (en) * 1995-05-13 1996-11-20 Holtek Microelectronics Inc Flexible CMOS IC layout method
US5909376A (en) * 1995-11-20 1999-06-01 Lsi Logic Corporation Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple "jiggles"
US6025616A (en) * 1997-06-25 2000-02-15 Honeywell Inc. Power distribution system for semiconductor die
JP2000068488A (ja) * 1998-08-20 2000-03-03 Oki Electric Ind Co Ltd 半導体集積回路のレイアウト方法
JP3186715B2 (ja) * 1998-10-29 2001-07-11 日本電気株式会社 半導体集積回路装置
US6838713B1 (en) 1999-07-12 2005-01-04 Virage Logic Corporation Dual-height cell with variable width power rail architecture
JP4521088B2 (ja) * 2000-03-27 2010-08-11 株式会社東芝 半導体装置
JP2006156929A (ja) * 2004-04-19 2006-06-15 Fujitsu Ltd 半導体集積回路及びその設計方法
US7149142B1 (en) 2004-05-28 2006-12-12 Virage Logic Corporation Methods and apparatuses for memory array leakage reduction using internal voltage biasing circuitry
US20060208317A1 (en) * 2005-03-17 2006-09-21 Tsuoe-Hsiang Liao Layout structure of semiconductor cells
US7616036B1 (en) 2005-09-12 2009-11-10 Virage Logic Corporation Programmable strobe and clock generator
JP2011242541A (ja) * 2010-05-17 2011-12-01 Panasonic Corp 半導体集積回路装置、および標準セルの端子構造
US9238367B2 (en) * 2013-03-15 2016-01-19 Ricoh Company, Ltd. Droplet discharging head and image forming apparatus
US10490543B2 (en) * 2017-12-05 2019-11-26 Qualcomm Incorporated Placement methodology to remove filler

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1440512A (en) * 1973-04-30 1976-06-23 Rca Corp Universal array using complementary transistors
US4161662A (en) * 1976-01-22 1979-07-17 Motorola, Inc. Standardized digital logic chip
US4125854A (en) * 1976-12-02 1978-11-14 Mostek Corporation Symmetrical cell layout for static RAM
US4240097A (en) * 1977-05-31 1980-12-16 Texas Instruments Incorporated Field-effect transistor structure in multilevel polycrystalline silicon
GB2018021B (en) * 1978-04-01 1982-10-13 Racal Microelect System Uncommitted logic cells
JPS58119649A (ja) * 1982-01-08 1983-07-16 Mitsubishi Electric Corp 半導体集積回路装置
US4566022A (en) * 1983-01-27 1986-01-21 International Business Machines Corporation Flexible/compressed array macro design

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100475504B1 (ko) * 2002-01-23 2005-03-10 미쓰비시덴키 가부시키가이샤 반도체 집적 회로

Also Published As

Publication number Publication date
JPH0527981B2 (ko) 1993-04-22
EP0167365A3 (en) 1986-03-26
US4701778A (en) 1987-10-20
JPS6114734A (ja) 1986-01-22
EP0167365B1 (en) 1989-06-14
KR900000202B1 (ko) 1990-01-23
DE3571102D1 (en) 1989-07-20
EP0167365A2 (en) 1986-01-08
CA1219380A (en) 1987-03-17

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Legal Events

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A201 Request for examination
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E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19921110

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