JP2003218210A - 半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム - Google Patents

半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム

Info

Publication number
JP2003218210A
JP2003218210A JP2002014532A JP2002014532A JP2003218210A JP 2003218210 A JP2003218210 A JP 2003218210A JP 2002014532 A JP2002014532 A JP 2002014532A JP 2002014532 A JP2002014532 A JP 2002014532A JP 2003218210 A JP2003218210 A JP 2003218210A
Authority
JP
Japan
Prior art keywords
cell
trunk
ground
line
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002014532A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003218210A5 (enExample
Inventor
Genichi Tanaka
玄一 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2002014532A priority Critical patent/JP2003218210A/ja
Priority to TW091114846A priority patent/TW591447B/zh
Priority to US10/193,250 priority patent/US6759698B2/en
Priority to KR10-2002-0048322A priority patent/KR100475504B1/ko
Priority to DE10244232A priority patent/DE10244232A1/de
Publication of JP2003218210A publication Critical patent/JP2003218210A/ja
Publication of JP2003218210A5 publication Critical patent/JP2003218210A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2002014532A 2002-01-23 2002-01-23 半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム Pending JP2003218210A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2002014532A JP2003218210A (ja) 2002-01-23 2002-01-23 半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム
TW091114846A TW591447B (en) 2002-01-23 2002-07-04 Semiconductor integrated circuit
US10/193,250 US6759698B2 (en) 2002-01-23 2002-07-12 Semiconductor integrated circuit
KR10-2002-0048322A KR100475504B1 (ko) 2002-01-23 2002-08-16 반도체 집적 회로
DE10244232A DE10244232A1 (de) 2002-01-23 2002-09-23 Integrierte Halbleiterschaltung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002014532A JP2003218210A (ja) 2002-01-23 2002-01-23 半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム

Publications (2)

Publication Number Publication Date
JP2003218210A true JP2003218210A (ja) 2003-07-31
JP2003218210A5 JP2003218210A5 (enExample) 2005-08-04

Family

ID=19191884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002014532A Pending JP2003218210A (ja) 2002-01-23 2002-01-23 半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム

Country Status (5)

Country Link
US (1) US6759698B2 (enExample)
JP (1) JP2003218210A (enExample)
KR (1) KR100475504B1 (enExample)
DE (1) DE10244232A1 (enExample)
TW (1) TW591447B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7760573B2 (en) 2005-02-10 2010-07-20 Elpida Memory, Inc. Semiconductor memory device and stress testing method thereof
US7844923B2 (en) 2006-10-20 2010-11-30 Panasonic Corporation Semiconductor integrated circuit designing method, semiconductor integrated circuit device, and electronic device

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6969952B2 (en) * 2003-08-01 2005-11-29 Hewlett-Packard Development Company, L.P. System and method for automatically routing power for an integrated circuit
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
JP2006228954A (ja) * 2005-02-17 2006-08-31 Matsushita Electric Ind Co Ltd 半導体装置とそのレイアウト設計方法
US20090126859A1 (en) * 2007-11-16 2009-05-21 Cadwallader Robert J Process for producing glass laminates
KR101012437B1 (ko) * 2010-07-26 2011-02-08 주식회사 화성 개폐수단을 가지는 통신장비 안치용 랙
US8819610B2 (en) 2013-01-09 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and layout of an integrated circuit
CN106024780B (zh) * 2016-07-14 2019-03-01 王培林 功率器件及其制备方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE53709T1 (de) * 1984-06-19 1990-06-15 Siemens Ag In c-mos-technik realisierte basiszelle.
JPS6114734A (ja) * 1984-06-29 1986-01-22 Fujitsu Ltd 半導体集積回路装置及びその製造方法
US5410173A (en) * 1991-01-28 1995-04-25 Kikushima; Ken'ichi Semiconductor integrated circuit device
JP3144967B2 (ja) * 1993-11-08 2001-03-12 株式会社日立製作所 半導体集積回路およびその製造方法
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
JPH10150175A (ja) 1996-11-19 1998-06-02 Toshiba Corp 半導体集積回路およびその製造方法
JPH10189749A (ja) 1996-12-27 1998-07-21 Toshiba Corp 半導体集積回路装置、半導体集積回路装置の多電源供給方法、半導体集積回路装置の多電源供給プログラムを記録した機械読み取り可能な記録媒体
JPH1131803A (ja) 1997-07-10 1999-02-02 Oki Electric Ind Co Ltd ゲートアレイ
JPH11224901A (ja) 1998-02-05 1999-08-17 Toshiba Corp 複数電源混在回路、そのレイアウト方法、及びそのレイアウトプログラムを記録したコンピュータ読みとり可能な記録媒体
JP3819186B2 (ja) * 1999-09-22 2006-09-06 株式会社東芝 スタンダードセル、半導体集積回路およびそのレイアウト方法
US6766496B2 (en) * 2001-06-01 2004-07-20 Virtual Silicon Technology, Inc. Method and apparatus for integrated circuit design with a software tool

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7760573B2 (en) 2005-02-10 2010-07-20 Elpida Memory, Inc. Semiconductor memory device and stress testing method thereof
US7844923B2 (en) 2006-10-20 2010-11-30 Panasonic Corporation Semiconductor integrated circuit designing method, semiconductor integrated circuit device, and electronic device

Also Published As

Publication number Publication date
US20030136977A1 (en) 2003-07-24
US6759698B2 (en) 2004-07-06
KR100475504B1 (ko) 2005-03-10
KR20030064249A (ko) 2003-07-31
TW591447B (en) 2004-06-11
DE10244232A1 (de) 2003-08-07

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