JP2003218210A5 - - Google Patents
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- Publication number
- JP2003218210A5 JP2003218210A5 JP2002014532A JP2002014532A JP2003218210A5 JP 2003218210 A5 JP2003218210 A5 JP 2003218210A5 JP 2002014532 A JP2002014532 A JP 2002014532A JP 2002014532 A JP2002014532 A JP 2002014532A JP 2003218210 A5 JP2003218210 A5 JP 2003218210A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002014532A JP2003218210A (ja) | 2002-01-23 | 2002-01-23 | 半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム |
| TW091114846A TW591447B (en) | 2002-01-23 | 2002-07-04 | Semiconductor integrated circuit |
| US10/193,250 US6759698B2 (en) | 2002-01-23 | 2002-07-12 | Semiconductor integrated circuit |
| KR10-2002-0048322A KR100475504B1 (ko) | 2002-01-23 | 2002-08-16 | 반도체 집적 회로 |
| DE10244232A DE10244232A1 (de) | 2002-01-23 | 2002-09-23 | Integrierte Halbleiterschaltung |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002014532A JP2003218210A (ja) | 2002-01-23 | 2002-01-23 | 半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003218210A JP2003218210A (ja) | 2003-07-31 |
| JP2003218210A5 true JP2003218210A5 (enExample) | 2005-08-04 |
Family
ID=19191884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002014532A Pending JP2003218210A (ja) | 2002-01-23 | 2002-01-23 | 半導体集積回路、自動配置配線装置及び半導体集積回路の多電源供給方法並びにプログラム |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6759698B2 (enExample) |
| JP (1) | JP2003218210A (enExample) |
| KR (1) | KR100475504B1 (enExample) |
| DE (1) | DE10244232A1 (enExample) |
| TW (1) | TW591447B (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6969952B2 (en) * | 2003-08-01 | 2005-11-29 | Hewlett-Packard Development Company, L.P. | System and method for automatically routing power for an integrated circuit |
| US7448012B1 (en) | 2004-04-21 | 2008-11-04 | Qi-De Qian | Methods and system for improving integrated circuit layout |
| JP4094614B2 (ja) | 2005-02-10 | 2008-06-04 | エルピーダメモリ株式会社 | 半導体記憶装置及びその負荷試験方法 |
| JP2006228954A (ja) * | 2005-02-17 | 2006-08-31 | Matsushita Electric Ind Co Ltd | 半導体装置とそのレイアウト設計方法 |
| JP2008103587A (ja) | 2006-10-20 | 2008-05-01 | Matsushita Electric Ind Co Ltd | 半導体集積回路の設計方法、半導体集積回路装置、並びに、電子装置 |
| US20090126859A1 (en) * | 2007-11-16 | 2009-05-21 | Cadwallader Robert J | Process for producing glass laminates |
| KR101012437B1 (ko) * | 2010-07-26 | 2011-02-08 | 주식회사 화성 | 개폐수단을 가지는 통신장비 안치용 랙 |
| US8819610B2 (en) | 2013-01-09 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and layout of an integrated circuit |
| CN106024780B (zh) * | 2016-07-14 | 2019-03-01 | 王培林 | 功率器件及其制备方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ATE53709T1 (de) * | 1984-06-19 | 1990-06-15 | Siemens Ag | In c-mos-technik realisierte basiszelle. |
| JPS6114734A (ja) * | 1984-06-29 | 1986-01-22 | Fujitsu Ltd | 半導体集積回路装置及びその製造方法 |
| US5410173A (en) * | 1991-01-28 | 1995-04-25 | Kikushima; Ken'ichi | Semiconductor integrated circuit device |
| JP3144967B2 (ja) * | 1993-11-08 | 2001-03-12 | 株式会社日立製作所 | 半導体集積回路およびその製造方法 |
| US5698873A (en) * | 1996-03-08 | 1997-12-16 | Lsi Logic Corporation | High density gate array base cell architecture |
| JPH10150175A (ja) | 1996-11-19 | 1998-06-02 | Toshiba Corp | 半導体集積回路およびその製造方法 |
| JPH10189749A (ja) | 1996-12-27 | 1998-07-21 | Toshiba Corp | 半導体集積回路装置、半導体集積回路装置の多電源供給方法、半導体集積回路装置の多電源供給プログラムを記録した機械読み取り可能な記録媒体 |
| JPH1131803A (ja) | 1997-07-10 | 1999-02-02 | Oki Electric Ind Co Ltd | ゲートアレイ |
| JPH11224901A (ja) | 1998-02-05 | 1999-08-17 | Toshiba Corp | 複数電源混在回路、そのレイアウト方法、及びそのレイアウトプログラムを記録したコンピュータ読みとり可能な記録媒体 |
| JP3819186B2 (ja) * | 1999-09-22 | 2006-09-06 | 株式会社東芝 | スタンダードセル、半導体集積回路およびそのレイアウト方法 |
| US6766496B2 (en) * | 2001-06-01 | 2004-07-20 | Virtual Silicon Technology, Inc. | Method and apparatus for integrated circuit design with a software tool |
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2002
- 2002-01-23 JP JP2002014532A patent/JP2003218210A/ja active Pending
- 2002-07-04 TW TW091114846A patent/TW591447B/zh not_active IP Right Cessation
- 2002-07-12 US US10/193,250 patent/US6759698B2/en not_active Expired - Fee Related
- 2002-08-16 KR KR10-2002-0048322A patent/KR100475504B1/ko not_active Expired - Fee Related
- 2002-09-23 DE DE10244232A patent/DE10244232A1/de not_active Withdrawn