TW564433B - Test array and method for testing memory arrays - Google Patents
Test array and method for testing memory arrays Download PDFInfo
- Publication number
- TW564433B TW564433B TW091119697A TW91119697A TW564433B TW 564433 B TW564433 B TW 564433B TW 091119697 A TW091119697 A TW 091119697A TW 91119697 A TW91119697 A TW 91119697A TW 564433 B TW564433 B TW 564433B
- Authority
- TW
- Taiwan
- Prior art keywords
- test
- wires
- array
- wire
- group
- Prior art date
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 201
- 230000015654 memory Effects 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims description 16
- 238000003491 array Methods 0.000 title abstract description 12
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052704 radon Inorganic materials 0.000 claims 1
- SYUHGPGVQRZVTB-UHFFFAOYSA-N radon atom Chemical compound [Rn] SYUHGPGVQRZVTB-UHFFFAOYSA-N 0.000 claims 1
- 239000004020 conductor Substances 0.000 abstract description 38
- 239000000523 sample Substances 0.000 abstract description 28
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 239000012467 final product Substances 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C2029/2602—Concurrent test
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/983,697 US6639859B2 (en) | 2001-10-25 | 2001-10-25 | Test array and method for testing memory arrays |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW564433B true TW564433B (en) | 2003-12-01 |
Family
ID=25530063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW091119697A TW564433B (en) | 2001-10-25 | 2002-08-29 | Test array and method for testing memory arrays |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6639859B2 (enExample) |
| EP (1) | EP1308965A3 (enExample) |
| JP (1) | JP4037728B2 (enExample) |
| KR (1) | KR100935645B1 (enExample) |
| CN (1) | CN1414619A (enExample) |
| TW (1) | TW564433B (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030218896A1 (en) * | 2002-05-22 | 2003-11-27 | Pon Harry Q | Combined memory |
| US6978407B2 (en) * | 2003-05-27 | 2005-12-20 | Lsi Logic Corporation | Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory |
| US7085183B2 (en) * | 2004-07-13 | 2006-08-01 | Headway Technologies, Inc. | Adaptive algorithm for MRAM manufacturing |
| US20070014307A1 (en) * | 2005-07-14 | 2007-01-18 | Yahoo! Inc. | Content router forwarding |
| KR100689841B1 (ko) | 2006-02-13 | 2007-03-08 | 삼성전자주식회사 | 반도체 제조장치용 레벨링 알고리듬 및 관련된 장치 |
| CN101458968B (zh) * | 2007-12-13 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | 获取非挥发存储器中失效二进制位分布信息的方法与装置 |
| US8526254B2 (en) * | 2008-04-03 | 2013-09-03 | Sidense Corp. | Test cells for an unprogrammed OTP memory array |
| US8868820B2 (en) * | 2011-10-31 | 2014-10-21 | Microsemi SoC Corporation | RAM block designed for efficient ganging |
| US8750031B2 (en) * | 2011-12-16 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test structures, methods of manufacturing thereof, test methods, and MRAM arrays |
| CN112767989A (zh) * | 2021-01-06 | 2021-05-07 | 波平方科技(杭州)有限公司 | 新型存储器测试结构 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2629213B2 (ja) * | 1987-11-13 | 1997-07-09 | 松下電器産業株式会社 | アクティブマトリックスアレイの検査方法および検査装置 |
| DE3937187A1 (de) * | 1989-11-08 | 1991-05-16 | Philips Patentverwaltung | Verfahren zum herstellen von integrierten schaltungen sowie integrierte schaltung |
| US5083697A (en) * | 1990-02-14 | 1992-01-28 | Difrancesco Louis | Particle-enhanced joining of metal surfaces |
| US5107459A (en) * | 1990-04-20 | 1992-04-21 | International Business Machines Corporation | Stacked bit-line architecture for high density cross-point memory cell array |
| JPH05144293A (ja) * | 1991-11-20 | 1993-06-11 | Sony Corp | 半導体メモリーｔｅｇ及び半導体メモリー回路の検査方法 |
| US5952838A (en) * | 1995-06-21 | 1999-09-14 | Sony Corporation | Reconfigurable array of test structures and method for testing an array of test structures |
| JPH0991998A (ja) * | 1995-09-20 | 1997-04-04 | Nittetsu Semiconductor Kk | 半導体記憶装置 |
| US5764569A (en) * | 1996-09-24 | 1998-06-09 | Altera Corporation | Test structure and method to characterize charge gain in a non-volatile memory |
| US5794175A (en) * | 1997-09-09 | 1998-08-11 | Teradyne, Inc. | Low cost, highly parallel memory tester |
| JPH11120797A (ja) * | 1997-10-15 | 1999-04-30 | Toshiba Microelectronics Corp | 強誘電体メモリ及びそのスクリーニング方法 |
| US6018484A (en) * | 1998-10-30 | 2000-01-25 | Stmicroelectronics, Inc. | Method and apparatus for testing random access memory devices |
| US6456525B1 (en) * | 2000-09-15 | 2002-09-24 | Hewlett-Packard Company | Short-tolerant resistive cross point array |
| US6552409B2 (en) * | 2001-06-05 | 2003-04-22 | Hewlett-Packard Development Company, Lp | Techniques for addressing cross-point diode memory arrays |
-
2001
- 2001-10-25 US US09/983,697 patent/US6639859B2/en not_active Expired - Lifetime
-
2002
- 2002-08-29 TW TW091119697A patent/TW564433B/zh not_active IP Right Cessation
- 2002-10-02 JP JP2002290178A patent/JP4037728B2/ja not_active Expired - Fee Related
- 2002-10-18 EP EP02257238A patent/EP1308965A3/en not_active Withdrawn
- 2002-10-24 KR KR1020020065107A patent/KR100935645B1/ko not_active Expired - Fee Related
- 2002-10-25 CN CN02147054A patent/CN1414619A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN1414619A (zh) | 2003-04-30 |
| EP1308965A2 (en) | 2003-05-07 |
| KR20030034012A (ko) | 2003-05-01 |
| US20030081477A1 (en) | 2003-05-01 |
| JP4037728B2 (ja) | 2008-01-23 |
| EP1308965A3 (en) | 2004-09-22 |
| KR100935645B1 (ko) | 2010-01-07 |
| JP2003203499A (ja) | 2003-07-18 |
| US6639859B2 (en) | 2003-10-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |