TW511431B - Bump-attached wiring circuit board and method for manufacturing same - Google Patents
Bump-attached wiring circuit board and method for manufacturing same Download PDFInfo
- Publication number
- TW511431B TW511431B TW090116215A TW90116215A TW511431B TW 511431 B TW511431 B TW 511431B TW 090116215 A TW090116215 A TW 090116215A TW 90116215 A TW90116215 A TW 90116215A TW 511431 B TW511431 B TW 511431B
- Authority
- TW
- Taiwan
- Prior art keywords
- wiring circuit
- thin film
- layer
- bump
- thickness
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 142
- 239000002184 metal Substances 0.000 claims abstract description 142
- 239000011888 foil Substances 0.000 claims abstract description 70
- 239000010409 thin film Substances 0.000 claims abstract description 64
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 52
- 239000010410 layer Substances 0.000 claims description 114
- 239000010408 film Substances 0.000 claims description 39
- 229920001721 polyimide Polymers 0.000 claims description 34
- 239000002243 precursor Substances 0.000 claims description 32
- 239000004642 Polyimide Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 27
- 230000001681 protective effect Effects 0.000 claims description 20
- 238000000576 coating method Methods 0.000 claims description 17
- 239000011248 coating agent Substances 0.000 claims description 15
- 239000011247 coating layer Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052770 Uranium Inorganic materials 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 238000013459 approach Methods 0.000 claims description 8
- 229910052718 tin Inorganic materials 0.000 claims description 8
- 229910052725 zinc Inorganic materials 0.000 claims description 8
- 239000011889 copper foil Substances 0.000 claims description 7
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910017709 Ni Co Inorganic materials 0.000 claims description 5
- 229910003267 Ni-Co Inorganic materials 0.000 claims description 5
- 229910003262 Ni‐Co Inorganic materials 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 230000002079 cooperative effect Effects 0.000 claims 2
- JHRWWRDRBPCWTF-OLQVQODUSA-N captafol Chemical compound C1C=CC[C@H]2C(=O)N(SC(Cl)(Cl)C(Cl)Cl)C(=O)[C@H]21 JHRWWRDRBPCWTF-OLQVQODUSA-N 0.000 claims 1
- 238000007747 plating Methods 0.000 abstract description 6
- 238000002203 pretreatment Methods 0.000 abstract 2
- 238000009413 insulation Methods 0.000 description 5
- 238000009434 installation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229920005575 poly(amic acid) Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910000531 Co alloy Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 150000003949 imides Chemical class 0.000 description 2
- 150000002466 imines Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002098 polyfluorene Polymers 0.000 description 2
- 238000012993 chemical processing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000006358 imidation reaction Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/032—Organic insulating material consisting of one material
- H05K1/0346—Organic insulating material consisting of one material containing N
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09481—Via in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
511431 A7 ------B7 ______ 五、發明說明(1 ) 發明之枝術領域 本發明係關於一種具有高度一定之突塊之具突塊之配 線回路基板及其製造方法。 習知技術 半導體元件及液晶顯示元件等之電子零件與配線回路 基板進行連接的場合,或多層配線基板之層間連接的場合 ,以微小的突塊(例如突塊直徑突塊高度 作連接係廣受使用著。 用以形成此般大小的突塊之代表的方法如圖3所示。 亦即,如圖3 (a)所示般,備妥在聚醯亞胺膜31上貼 覆有銅箔32之2層軟性基板33,藉由光微影法將銅箔圖 案化來形成配線回路34 (圖3 (b))。 然後,在配線回路34上,以一般的方法形成覆塗層 35 (圖3 (c))。例如,可在配線回路34上形成聚醯胺酸 層,藉由光微影法圖案化後,經由醯亞胺化形成覆塗層35 。或者,藉由光阻油墨印刷亦可。 然後,對與配線回路34對應之聚醯亞胺膜31的區域 ,進行雷射光照射形成突塊用孔36 (圖3 (d)),然後,於 必要時可對覆塗層35覆以保護膜(未圖示),之後,以電 鍍法在露出於突塊用孔底部之配線回路34上使金屬突塊 37生長,藉此形成微小突塊(圖3 (e))。 發明所欲解決之課穎 然而,藉由雷射光之照射進行突塊用孔36之開孔的 4 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) -----------裝--------訂---------^9 (請先閱讀背面之注意事項再填寫本頁) 511431 A7 ------------_B7_____ 五、發明說明(> ) 場合,因於在突塊用孔36的底部所附著之污點(smear)量 之參差,開孔面積也會參差不齊,其結果,金屬突塊37 的高度也會產生大的參差情形,是問題所在。因此,難以 得到安定的突塊連接。尤其是,欲將半導體元件藉由超音 波同時連接到配線回路上會有困難。又,爲改善配線回路 34與其上所形成之金屬突塊37之間的密著強度,必須有 鍍敷的前處理。 本發明,係爲解決上述的習知技術之問題而提出,目 的在於提供:有安定的突塊連接,且不須鍍敷之前處理般 的繁雜的操作之具突塊之配線回路基板之製造方法。 $ 用以解決課顆少丰段 本發明者等發現,藉由將金屬箔(其厚度爲配線回路 的厚度與待形成於配線回路上之突塊的高度之合計厚度) 半蝕刻至相當於金屬突塊之厚度的深度,可不須施行鍍敷 的前處理之類的繁雜的操作,而可製得具有均一高度的突 塊’且藉由在金屬箔的突塊形成面上,形成由與金屬箔相 異的金屬所構成之金屬薄膜層,可改善金屬箔的突塊形成 面與其上之絕緣層之間的接著性,改善配線回路基板的耐 藥品性、防止突塊側的金屬箔面與其上的絕緣層之間的剝 離’同時可實現安定的突塊連接,終於完成了本發明。 亦即,本發明提供一種具突塊之配線回路基板(係於 配線回路的單面上形成覆塗層,於另一面上形成絕緣層, 用以與配線回路導通之突塊係以自該絕緣層突出之方式形 ---------裝--------訂---------^9. (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511431 A7 ^_B7 __ 五、發明說明(1 ) 成者),其特徵在於,其中,配線回路與突塊係由一金屬 箔所一體形成,且配線回路的突塊形成面與絕緣面之間, 設置有由與該金屬箔相異的金屬所構成之金屬薄膜層。 此處,於絕緣層爲將聚醯亞胺前驅物層進行醯亞胺化 之聚醯亞胺膜的場合,金屬薄膜層以顯示出對聚醯亞胺前 驅物層之接著力較對金屬箔者高者爲佳。作爲此般的金屬 箱與金屬薄膜之組合,可舉出金屬箔爲銅箔、金屬薄膜爲 Ni、Zn、Sn或Ni_Co合金之薄膜之組合。又,在此具突 塊之配線回路基板中,覆塗層,以具有可自覆塗層側接近 配線回路之連接口爲佳。 又,本發明提供一種具突塊之配線回路基板(係於配 線回路上形成有突塊者)之製造方法,其特徵在於,係包 含下述之製程: (a) 在金屬箔(其厚度爲配線回路的厚度與待形成於 配線回路上之突塊的高度之合計厚度)之突塊形成面上積 層保護膜,在金屬箔之配線回路形成面上形成配線回路形 成用蝕刻遮罩之製程; (b) 自配線回路形成用蝕刻遮罩側對金屬箔進行半蝕 刻’以形成所期的厚度的配線回路之製程; (c) 將配線回路形成用蝕刻遮罩去除後,在配線回路 上設置覆塗層之製程; (d) 將設置於金屬箔之突塊形成面上之保護膜去除後 ’在突塊形成面上形成突塊形成用蝕刻遮罩之製程; (e) 自突塊形成用蝕刻遮罩側對金屬箔進行半蝕刻, 6 本紙張尺度巾關家群(CNS)A4規格咖χ & ) - ^ ----------------訂--------1 (請先閱讀背面之注意事項再填寫本頁) 511431 A7 ______ _ 五、發明說明(欠) 以形成所期的高度的突塊之製程; (f )將突塊形成用鈾刻遮罩去除後,形成由與金屬箱 相異的金屬所構成之金屬薄膜層之製程; (g) 在金屬薄膜上’以將突塊埋入的方式形成聚醯亞 胺前驅物之製程;以及 (h) 將聚醯亞胺前驅物蝕刻,進行醯亞胺化,形成所 期之厚度的絕緣層之製程。 在此製造方法中,配線回路係先形成於突塊形成之前 〇 進而,本發明提供一種在配線回路上形成有突塊之具 突塊之配線回路基板之製造方法,其特徵在於,係包含下 述之製程: (aa)在金屬箔(其厚度爲配線回路的厚度與必須形成 於配線回路上之突塊的高度之合計厚度)之配線回路形成 面上積層保護膜,在金屬箔之突塊形成面上形成突塊形成 用蝕刻遮罩之製程; (bb)自突塊形成用蝕刻遮罩側對金屬箔進行半蝕刻 ,以形成所期的高度的突塊之製程; (cc)將突塊形成用蝕刻遮罩去除後,設置由與金屬 箔相異的金屬所構成之金屬薄膜層之製程; (dd)在金屬薄膜上,以將突塊埋入之方式形成聚醯 亞胺前驅物層之製程; (ee)將聚醯亞胺前驅物蝕刻,再進行醯亞胺化形成 所期的厚度之絕緣層之製程; 7 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) *t--------IT--------- (請先閱讀背面之注意事項再填寫本頁) 511431 A7 _ _B7 五、發明說明('< ) (ff)將設置於金屬箔的配線回路形成面上之保護膜 去除後,在配線回路形成面上形成配線回路形成用蝕刻遮 罩之製程; (gg)自配線回路形成用蝕刻遮罩側對金屬箔進行半 蝕刻以形成所期之厚度的配線回路之製程;以及 (hh)將配線回路形成用鈾刻遮罩去除後,在配線回 路上設置覆塗層之製程。 在此製造方法中,配線回路係先形成於突塊形成之前 發明之實施形熊 茲就本發明之具突塊之配線回路基板,依隨製造例, 一邊參照圖示,就每一製程加以詳細地說明。 首先爲關於,在配線回路上形成有突塊之具突塊之配 線回路基板之製造方法中,於突塊形成前之形成配線回路 之製造方法(製程(a)〜(g)),一邊參照圖1就每一製程加 以說明。 製稈(a) 首先,在金屬箔3(其厚度爲配線回路1(參照圖中虛線 部份)的厚度tl與待形成於配線回路1上之突塊2(參照_ 中虛線部份)的高度t2之合計厚度)之突瑰形成面3a上積 層保護膜4,在金屬箔3之配線回路形成面3b形成配線 回路形成用蝕刻遮罩5 (圖1 (a))。 8 Γ4先閱讀背面之注音?事項再填寫本頁} W裝--------訂--------- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511431 A7 ____B7 五、發明說明(V ) 有關配線回路1的厚度ti及突塊的高度,可依於 配線回路基板的使用目的選擇最適的數値。例如,在將配 線回路基板作爲半導體元件的搭載基板使用的場合,配線 回路1的厚度tl可設定爲2〇//m,突塊2的高度t2可設 定爲30#m,突塊2的直徑可設定爲5〇 // m。 作爲金屬箔3,可使用配線回路基板的導體層所使用 之材料,而可舉例以銅箔爲佳。 配線回路形成用蝕刻遮罩5,可於金屬箔3的配線回 路形成面3b,藉由光阻油墨之網版印刷來形成。或,亦可 藉由設置感光性樹脂層或乾式薄膜,以通常的方法進行曝 光、顯影來圖案化而形成。 製程(b) 然後,自配線回路形成用蝕刻遮罩5側,對金屬箔3 進行半蝕刻以形成所期之厚度tl的配線回路1 (圖1 (b) 〇 半蝕刻的條件(溫度、蝕刻液組成等)可依據金屬箔3 之材料或待鈾刻之厚度等來適宜選擇。 製程(c) 然後,將配線回路形成用蝕刻遮罩5以通常的方法去 除後,在配線回路1上設置覆塗層6 (圖1(c))。 覆塗層6,可將覆塗層用塗料藉由網版印刷法形成。 或,亦可藉由設置感光性樹脂層或乾式薄膜,以通常的方 9 -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511431 A7 ____B7_______ 五、發明說明(' ) 法進行曝光、顯影來圖案化而形成。又,亦可藉由通常的 方法設置由聚醯胺酸等之聚醯亞胺前驅物所構成的層,然 後藉由圖案化、醯亞胺化而形成。 於設置覆塗層6之際,以設置可自覆塗層6側接近配 線回路1之連接口 11爲佳。 製程(d) 將設置在金屬箔3的突塊形成面3a之保護膜4以通 常之方法去除之後,在突塊形成面3a上形成突塊形成用 蝕刻遮罩7 (圖1 (d))。 突塊形成用蝕刻遮罩7,可在金屬箔3的突塊形成面 3a,藉由光阻油墨之網版印刷來形成。或,亦可藉由設置 感光性樹脂層或乾式薄膜,以通常的方法進行曝光、顯影 來圖案化而形成。 製程(e) 自突塊形成用鈾刻遮罩7側對金屬箔3進行半蝕刻, 以形成所期的高度t2的突塊2 (圖1(e))。 半蝕刻條件(溫度、蝕刻液組成等),可依金屬箔3的 材料及待蝕刻之厚度等作適當的選擇。 又,於半蝕刻之前,覆塗層6亦可用保護膜覆蓋(未 圖示)。 製程(f) 將突塊形成用蝕刻遮罩7去除後,形成由與金屬箔3 10 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------------------訂·-------- (請先閱讀背面之注意事項再填寫本頁) 511431 A7 ___B7__ 五、發明說明(δ ) 相異的金屬所構成之金屬薄膜層10 (圖1(f))。 作爲金屬薄膜層1〇,以使用對後述之聚醯亞胺前驅物 層8顯示高接著力之金屬來形成爲佳。藉此,可提高聚醯 亞胺前驅物層8與金屬箔3之間的接著性,因而,可防止 在其後的藥品處理(例如,製程(g )的聚_亞胺前驅物層8 的平坦化蝕刻(etch back)處理等)之際,金屬箔3與聚 醯亞胺前驅物層8或其醯亞胺化之絕緣層9 (參照製程 (h))之間所發生之剝離現象。 作爲此般的金屬薄膜層1Q,於金屬范3爲一般的銅范 之場合,可列舉Ni、Zn、Sn或Ni-c〇合金之薄膜爲較佳 。此等之薄膜’可藉由化學鍍法、電鍍法、真空蒸鍍法等 形成。 金屬薄膜層10的層厚,若太薄,則無法充分改善與 絕緣層9及配線回路1之間的接著性,若太厚,並無法得 到加厚之膜厚的對應效果,因此以〇·01〜4//πι爲佳。尤 其是,於金屬薄膜層10爲Ζη或Sn的薄膜之場合,其較 佳之層厚爲0.1〜0.5/zm,爲Ni-Cc)合金的場合,其較佳 之層厚爲〇·1〜4#m,而若爲Ni的薄膜之場合,其較佳之 層厚爲0.01〜1/Zm。 又,於去除突塊形成用鈾刻遮罩7之際,於覆塗層6 覆有保護膜之場合時’亦可將保護膜同時去除。 製程(q) 在金屬薄膜層10上,以將突塊埋入的方式形成聚酿 11 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) -------------------訂--------I (請先閱讀背面之注意事項再填寫本頁) 511431 A7 ____________Β7__ 五、發明說明(1 ) 亞胺前驅物層8 ( _ 1 ( g ))。 聚醯亞胺前驅物層8,可藉由將聚醯胺酸以通常的方 法進行成膜而形成。醯亞胺化條件亦可依所使用之聚醯亞 胺前驅物的種類等而決定。 製程(h) 將聚醯亞胺前驅物層8進行平坦化蝕刻,再行醯亞胺 化,形成所期之厚度t3的絕緣層9。藉此,可得到如圖 1 (h)所示之具突塊之配線回路基板。 接著’係爲於配線回路上形成有突塊之具突塊之配線 回路基板之製造方法,就配線回路形成前的形成突塊之製 造方法(製程(aa)〜(hh)),一邊參照圖2就每一製程加以 說明。又’於圖2中,以符號表示之構成要素,係與圖1 之相同符號之構成要素相對應。 製程(aa) 首先’在金屬箔3(其厚度爲配線回路1(參照圖中虛 線部份)的厚度tl與待形成於配線回路1上之突塊2 (參 照圖中虛線部份)的高度t2之合計厚度)之配線回路形成 面3b積層保護膜4,在金屬箔3之突塊形成面3b形成突 塊形成用蝕刻遮罩7 (圖2 (a))。 製程(bb) 自突塊形成用蝕刻遮罩7側對金屬箔3進行半蝕刻, 12 -----------裝--------訂--------I (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511431 A7 ___— _B7 ___ 五、發明說明(、。) 以形成所期的高度t2的突塊2 (圖2 (b))。 製程(cc) 將突塊形成用蝕刻遮罩7以通常的方法去除後,形成 由與金屬箔3相異的金屬所構成之金屬薄膜層1〇(圖 2(c))。 製程(dd) 在金屬薄膜層10上,以將突塊2埋入之方式形成聚 醯亞胺前驅物層8 (圖2 (d))。 製程(e e ) 將聚醯亞胺前驅物層8平坦化飩刻,再進行醯亞胺化 形成所期的厚度13之絕緣層9 (圖2(e))。 製程(ff) 將設置於金屬箔3的配線回路形成面3b上之保護膜 4以通常的方法去除後,在配線回路形成面3b上形成配線 回路形成用蝕刻遮罩5 (圖2 (f))。 製程(qq) 自配線回路形成用蝕刻遮罩5側對金屬箔3進行半鈾 刻以形成所期之厚度tl的配線回路1 (圖2 (g))。 又,在半蝕刻之前,亦可將突塊2覆以保護膜(未圖 示)。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -----------裝--------訂---------^9. (請先閱讀背面之注意事項再填寫本頁) 511431 A7 _____B7_ 五、發明說明(l\ ) mp (hh) 將配線回路形成用蝕刻遮罩5以通常的方法去除後( 圖2 (h)),在配線回路1上設置覆塗層6 °藉此可得到如 圖2(i)所示之具突塊之配線回路基板。此時’以設置有 可自覆塗層6接近配線回路1之連接口 11爲佳。 又,於去除配線回路形成用鈾刻遮罩5之際’於突塊 2覆有保護膜之場合’保護膜亦可同時去除° 以上之依據本發明的製造方法所得到之具突塊之配線 回路基板,如圖丄丨11)及圖2(i)所示般’在配線回路1 的單面上形成有覆塗層6,另一面上形成有絕緣層9 ’與 配線回路1導通之突塊2係以突出於絕緣層9之方式形成 ,配線回路1與突塊2係由同一金屬箔一體形成’且於配 線回路1之突塊形成面與絕緣層9之間,設置有由與該金 屬箔相異的金屬所構成之金屬薄膜層10。此金屬薄膜層 10,於絕緣層9係由聚醯亞胺前驅物層進行醯亞胺化之聚 醯亞胺膜的場合,以由展現出對聚醯亞胺前驅物層之接著 力高於對金屬箔之材料所形成爲佳。例如,金屬箔爲銅箔 的場合,係由Ni、Zn、Sn或Ni-Co合金之薄膜所形成。 藉由此般之構成,可提高聚醯亞胺前驅物與金屬箔之間的 接著性,因而,可防止在藥品處理(例如,聚醯亞胺前驅 物層的平坦化蝕刻處理等)之際,金屬箔與聚醯亞胺前驅 物層或其醯亞胺化之絕緣層9之間所發生之剝離現象。 又,此具突塊之配線回路基板,於覆塗層6上,設有 可自覆塗層6接近配線回路1之連接口 11,因此,成爲 14 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) —--------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 511431 A7 B7 五、發明說明(〆) 兩面存取基板,而可期提高電子元件之組裝密度。 (請先閱讀背面之注意事項再填寫本頁) 發明之效果 本發明可提供一種具突塊之配線回路基板,其係爲突 塊強度安定而可有安定的突塊連接,且不須鍍敷之前處理 般的繁雜的操作者。尤其是,於積體回路中之突塊連接, 可藉由超音波同時進行安定的連接。 圖式之簡單說明 圖1爲本發明之具突塊之配線回路基板之製造方法的 製程說明圖。 圖2爲本發明之具突塊之配線回路基板之製造方法的 製程說明圖。 圖3爲習知之具突塊之配線回路基板之製造方法的製 程說明圖。 元件符號說明 1 2 3 4 5 6 7 配線回路 突塊 金屬箔 保護膜 配線回路形成用蝕刻遮罩 覆塗層 突塊形成用飩刻遮罩 15 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511431 A7 _B7 五、發明說明(0 ) 聚醯亞胺前驅物 9 絕緣層 10 金屬薄膜層 11 連接口 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Claims (1)
- 經濟部智慧財產局員工消費合作社印製 511431 A8 B8 C8 ____ D8 六、申請專利範圍 1· 一種具突塊之配線回路基板,係在配線回路的單 面形成有覆塗層,在另一面形成有絕緣層,與配線回路導 通之突塊,係以突出於該絕緣層之方式形成者;其特徵在 於, 配線回路與突塊係由一金屬箔所一體形成,且於配線 回路之突塊形成面與絕緣層之間,設置有由與該金屬箔相 異的金屬所構成之金屬薄膜層。 2·如申請專利範圍第1項之具突塊之配線回路基板 ,其中,絕緣層係將聚醯亞胺前驅物層進行醯亞胺化之聚 醯亞胺膜,金屬薄膜層顯示出對聚醯亞胺前驅物層之接著 力較對金屬箔者高。 3. 如申請專利範圍第或2項之具突塊之配線回路 基板,其中,金屬箔係銅箔,金屬薄膜層係Ni、Zn、Sn 或Ni-Co合金之薄膜。 4. 如申請專利範圍第3項之具突塊之配線回路基板 ,其中,金屬薄膜層之層厚爲0.01〜4^111。 5. 如申請專利範圍第3項之具突塊之配線回路基板 ,其中,金屬薄膜層爲Zn或Sn的薄膜之場合,金屬薄膜 層之膜厚爲〇·1〜〇.5/zm。 6. 如申請專利範圍第3項之具突塊之配線回路基板 ,其中,金屬薄膜層爲Ni-Co合金的薄膜之場合,金屬薄 膜層之膜厚爲0.1〜4/zm。 7. 如申請專利範圍第3項之具突塊之配線回路基板 ,其中,金屬薄膜層爲Ni的薄膜之場合,金屬薄膜層之 1 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 511431 A8 B8 C8 ______ D8 六、申請專利範圍 膜厚爲0·01〜。 8 ·如申請專利範圍第1或2項之具突塊之配線回路 基板’其中,覆塗層具有可自覆塗層側接近配線回路之連 接口。 9·如申請專利範圍第3項之具突塊之配線回路基板 ’其中,覆塗層具有可自覆塗層側接近配線回路之連接口 〇 10·如申請專利範圍第4項之具突塊之配線回路基板 ’其中,覆塗層具有可自覆塗層側接近配線回路之連接口 〇 11·如申請專利範圍第5項之具突塊之配線回路基板 ,其中,覆塗層具有可自覆塗層側接近配線回路之連接口 〇 12.如申請專利範圍第6項之具突塊之配線回路基板 ,其中,覆塗層具有可自覆塗層側接近配線回路之連接口 〇 13·如申請專利範圍第7項之具突塊之配線回路基板 ,其中,覆塗層具有可自覆塗層側接近配線回路之連接口 〇 14· 一種具突塊之配線回路基板之製造方法,該配線 回路基板係於配線回路上形成有突塊者,其特徵在於,係 包含下述之製程: (a)在金屬箔(其厚度爲配線回路的厚度與待形成於 配線回路上之突塊的高度之合計厚度)之突塊形成面上積 2 tr---------^· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511431 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 層保護膜,在金屬箔之配線回路形成面上形成配線回路形 成用蝕刻遮覃之製程; (b)自配線回路形成用蝕刻遮罩側對金屬箔進行半鈾 刻,以形成所期的厚度的配線回路之製程; (C)將配線回路形成用蝕刻遮罩去除後’在配線回路 上設置覆塗層之製程; (d) 將設置於金屬箔之突塊形成面上之保護膜去除後 ,在突塊形成面上形成突塊形成用餓刻遮罩之製程; (e) 自突塊形成用鈾刻遮罩側對金屬箔進行半蝕刻’ 以形成所期的高度的突塊之製程; (f) 將突塊形成用蝕刻遮罩去除後’形成由與金屬箔 相異的金屬所構成之金屬薄膜層之製程; (g) 在金屬薄膜層上,以將突塊埋入的方式形成聚醯 亞胺前驅物層之製程;以及 (h) 將聚醯亞胺前驅物層進行平坦化蝕刻,再行醯亞 胺化,形成所期之厚度的絕緣層之製程。 丄5·如申請專利範圍第14項製造方法,其中,以製 程(f)形成之金屬箔膜層顯示出對聚醯亞胺前驅物層之接 著力較對金屬箔者高。 I6·如申請專利範圍第14或15項製造方法,其中 ,金屬箔係銅箔,金屬薄膜層係Ni、Zn、Sn或合 金之薄膜。 ^ I7·如申請專利範圍第16項之製造方法,其中,金 屬薄膜層之層厚爲0.01〜4/zm。 3 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ^---------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 511431 A8 B8 C8 -- ---D8____ 六、申請專利範圍 18·如申請專利範圍第16項之製造方法,其中,金 屬薄膜層爲Zri或Sn的薄膜之場合,其金屬薄膜層之膜厚 爲 0·1 〜0·5/ζπ\〇 丄9·如申請專利範圍第16項之製造方法,其中,金 屬薄膜層爲Ni〜C〇合金的薄膜之場合,其金屬薄膜層之膜 厚爲〇·1〜4/zm。 2〇·如申請專利範圍第16項之製造方法,其中,金 屬薄膜層爲Ni的薄膜之場合,其金屬薄膜層之膜厚爲 0.01〜l//mo 21· —種在配線回路上形成有突塊之具突塊之配線回 路基板之製造方法,其特徵在於,係包含下述之製程: (aa)在金屬箔(其厚度爲配線回路的厚度與待形成於 配線回路上之突塊的高度之合計厚度)之配線回路形成面 上積層保護膜’在金屬箔之突塊形成面上形成突塊形成用 蝕刻遮罩之製程; (bb)自突塊形成用蝕刻遮罩側對金屬箔進行半蝕刻 ,以形成所期的高度的突塊之製程; (cc)將突塊形成用蝕刻遮罩去除後,形成由與金屬 箔相異的金屬所構成之金屬薄膜層之製程; (dd)在金屬薄膜層上,以將突塊埋入之方式形成聚 醯亞胺前驅物層之製程; (ee)將聚醯亞胺前驅物層平坦化蝕刻,再進行醯亞 胺化形成所期的厚度之絕緣層之製程; (ff)將設置於金屬箔的配線回路形成面上之保護膜 4 --------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(21Q x 297公爱) 經濟部智慧財產局員工消費合作社印製 511431 A8 B8 __§_ 六、申請專利範圍 去除後,在配線回路形成面上形成配線回路形成用蝕刻遮 罩之製程; (gg)自配線回路形成用蝕刻遮罩側對金屬箔進行半 蝕刻以形成所期之厚度的配線回路之製程;以及 (hh)將配線回路形成用蝕刻遮罩去除後,在配線回 路上設置覆塗層之製程。 22. 如申請專利範圍第21項之製造方法,其中,在 製程(CC)所形成之金屬薄膜層顯示出對聚醯亞胺前驅物層 之接著力較對金屬箔者高。 23. 如申請專利範圍第21或22項之製造方法,其 中,金屬范係銅箱,金屬薄膜層係Ni、Zn、Sn或Ni-Co 合金之薄膜。 24. 如申請專利範圍第23項之製造方法,其中,金 屬薄膜層之層厚爲〇.〇1〜4/zm。 25. 如申請專利範圍第23項之製造方法,其中,金 屬薄膜層爲Zn或Sn的薄膜之場合,其金屬薄膜層之膜厚 爲 0.1 〜0.5/imo 26. 如申請專利範圍第23項之製造方法,其中,金 屬薄膜層爲Ni-Co合金的薄膜之場合,其金屬薄膜層之膜 厚爲0·1〜4//m。 27. 如申請專利範圍第23項之製造方法,其中,金 屬薄膜層爲Ni的薄膜之場合,其金屬薄膜層之膜厚爲 〇· 01〜1 // m。 5 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------訂---------線 (請先閱讀背面之注意事項再填寫本頁)
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US6406991B2 (en) * | 1999-12-27 | 2002-06-18 | Hoya Corporation | Method of manufacturing a contact element and a multi-layered wiring substrate, and wafer batch contact board |
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2000
- 2000-07-11 JP JP2000210482A patent/JP3760731B2/ja not_active Expired - Fee Related
-
2001
- 2001-07-02 US US09/895,210 patent/US6518510B2/en not_active Expired - Lifetime
- 2001-07-03 TW TW090116215A patent/TW511431B/zh not_active IP Right Cessation
- 2001-07-11 CN CNB011231599A patent/CN1185913C/zh not_active Expired - Fee Related
- 2001-07-11 KR KR1020010041438A patent/KR100771030B1/ko not_active IP Right Cessation
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2002
- 2002-10-11 US US10/268,722 patent/US7020961B2/en not_active Expired - Fee Related
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2005
- 2005-12-06 US US11/294,530 patent/US7520053B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR100771030B1 (ko) | 2007-10-29 |
US7520053B2 (en) | 2009-04-21 |
CN1335740A (zh) | 2002-02-13 |
JP3760731B2 (ja) | 2006-03-29 |
KR20020006462A (ko) | 2002-01-19 |
US20060070978A1 (en) | 2006-04-06 |
US20030034173A1 (en) | 2003-02-20 |
US20020005292A1 (en) | 2002-01-17 |
US6518510B2 (en) | 2003-02-11 |
CN1185913C (zh) | 2005-01-19 |
US7020961B2 (en) | 2006-04-04 |
JP2002026489A (ja) | 2002-01-25 |
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