JPS5718357A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5718357A JPS5718357A JP9344080A JP9344080A JPS5718357A JP S5718357 A JPS5718357 A JP S5718357A JP 9344080 A JP9344080 A JP 9344080A JP 9344080 A JP9344080 A JP 9344080A JP S5718357 A JPS5718357 A JP S5718357A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- region
- type
- voltage
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 3
- 229910008062 Si-SiO2 Inorganic materials 0.000 abstract 2
- 229910006403 Si—SiO2 Inorganic materials 0.000 abstract 2
- 239000002245 particle Substances 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000003321 amplification Effects 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
PURPOSE:To prevent the generation of a surface level for the subject semiconductor device by a method wherein a backward yielding is obtained by performing a P-N junction between the base high density region provided at the bottom of an emitter and the emitter region, and damage is given to an Si-SiO2 interface by hot charged particles. CONSTITUTION:A high density N type impurity layer 3 and an N type epitaxial layer 3 are formed on a P type silicon substrate 1, a P type isolated diffusion region 4 is formed and, at the same time, a P type diffusion region 8 is formed. Then, a P type base region 5, an emitter region 6 and a collector lead-out region 7 are formed. As regards the backward yielding voltage of an emitter base junction, said voltage at the junction part with the P type diffusion region at the bottom of the emitter is lower than that of the surface part of the epitaxial layer. Therefore, the voltage yields at the bottom part of the emitter and the hot charged particles generated at the time of yielding is not caught by the Si-SiO2 interface. According to this constitution, a lowering of current amplification factor due to the generation of a surface level and the deterioration of noise characteristic are not generated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9344080A JPS5718357A (en) | 1980-07-09 | 1980-07-09 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9344080A JPS5718357A (en) | 1980-07-09 | 1980-07-09 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5718357A true JPS5718357A (en) | 1982-01-30 |
Family
ID=14082378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9344080A Pending JPS5718357A (en) | 1980-07-09 | 1980-07-09 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5718357A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61128593A (en) * | 1984-11-27 | 1986-06-16 | 株式会社 麗光 | Evaporation film for printed circuit |
JPS633461A (en) * | 1986-06-24 | 1988-01-08 | Nec Corp | Semiconductor device |
US7520053B2 (en) | 2000-07-11 | 2009-04-21 | Sony Corporation | Method for manufacturing a bump-attached wiring circuit board |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4831887A (en) * | 1971-08-18 | 1973-04-26 | ||
JPS50120971A (en) * | 1974-03-09 | 1975-09-22 | ||
JPS5410845U (en) * | 1977-06-24 | 1979-01-24 |
-
1980
- 1980-07-09 JP JP9344080A patent/JPS5718357A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4831887A (en) * | 1971-08-18 | 1973-04-26 | ||
JPS50120971A (en) * | 1974-03-09 | 1975-09-22 | ||
JPS5410845U (en) * | 1977-06-24 | 1979-01-24 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61128593A (en) * | 1984-11-27 | 1986-06-16 | 株式会社 麗光 | Evaporation film for printed circuit |
JPS633461A (en) * | 1986-06-24 | 1988-01-08 | Nec Corp | Semiconductor device |
US7520053B2 (en) | 2000-07-11 | 2009-04-21 | Sony Corporation | Method for manufacturing a bump-attached wiring circuit board |
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