TW505946B - Polycrystaline semiconductor material and method of manufacturing the same - Google Patents

Polycrystaline semiconductor material and method of manufacturing the same Download PDF

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TW505946B
TW505946B TW089117249A TW89117249A TW505946B TW 505946 B TW505946 B TW 505946B TW 089117249 A TW089117249 A TW 089117249A TW 89117249 A TW89117249 A TW 89117249A TW 505946 B TW505946 B TW 505946B
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zinc oxide
polycrystalline semiconductor
film
scope
thin film
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TW089117249A
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Koichi Haga
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Tohoku Techno Arch Co Ltd
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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505946 A7 B7 五、發明說明（1 ) 技術領域 ----^/---------裝--- (請先閱讀背面之注意事項再填寫本頁) 本發明係有關適於構成透明的半導體元件之半導體 構件，特別關於最合適之透明度高且電阻率低的鋅氧化物 背景技術 以鋅和氧作為構成元素之多結晶氧化鋅構件，被期 待應用·在受光元件、表面彈性波元件、壓電元件、透明導 電電極、主動元件等。製作方法有使用超高真空之MBe 法、雷射燒蝕法、濺鍍法、真空蒸鍍法、溶膠凝膠（s〇1 gei) 法、MO-CVD法等多種方法已被研討。 經濟部智慧財產局員工消費合作社印製 如就透明電晶體等之主動元件而言，從結晶性的觀 點，將使用超高真空之MBE法與雷射燒蝕法予以併用的 方法已成為主流。但是，此方法對於實現低價位且大面積 之主動元件而言，並非適宜的製作方法。然而，在透明導 電電極的製作中，採用上述方法則可以得出最高的數據。 又，在大面積堆積中濺鍍法雖已被試過，惟無法獲得可與 MBE法匹敵的低電阻率。由於現狀如此，因此集中注目 在結晶性良好且可以形成大面積薄膜的M〇_CVD法（Metal Organic Chemical Vapor Deposition System) ° 藉使用/5二酮型化合物之有機金屬的氧化鋅材料之 M〇-CVD法之製作方式已由南等人揭示於Appl. PhyS· Lett. ，· 41 (1982) 958。其内容，材料之使用目的被限制在透明 導電電極，因為是對玻璃基板上所形成的具有〇軸定向性 之多結晶氧化鋅薄膜產物，所以電阻率並不是十分足夠。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） 4 經濟部智慧財產局員工消費合作社印製 五、發明說明（2 ) 又有關使用此製作法而應用於其他元件之例並無報告。 使用MBE法而將氧化鋅應用於透明電晶體元件之例 已由東工大的川崎等，在平成12年春季應用物理學會講 演會預稿集中提出報告。在此報告中，因為使用玻璃基板 文為基板，所以結晶定向性為纖鋅礦（^町⑸⑷構造之c轴 〇 與採用薄膜之深度方向的傳導之太陽電池不同，透 月電曰曰體透明導電電極、表面彈性波元件為利用面内方 向的傳‘之元件。東北大學的中村等（jpn. J_ Appl. Phys. 39 (〇) L534)已對使用MBE法，且a軸定向之單結晶氧化鋅 薄膜適合於表面彈性波元件的情形加以報告。 多結晶或非晶質基板上所形成之氧化鋅（ZnO)薄膜幾 乎都顯不出結晶軸的〇軸定向性。此係因〇軸定向在薄膜製 作盼之堆積能量最小所造成。具有此c軸定向性之氧化鋅 ，在深度方向傳導性佳。但是，難以形成具有在面内方向 傳導性優良之a軸定向性的氧化鋅薄膜。如果以非常特殊 的製作條件形成薄膜，則雖也有變成a軸定向的情形，惟 再現性低。 本發明之目的在於，提供一種平面方向上電阻率低 ’且具有結晶軸之a軸定向性的多結晶氧化鋅半導體構件 及其製作方法。 ‘ 又，在可見區域具有透明性之氧化鋅半導體構件亦 為本發明之目的。 發明說明 表紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐 ---------------I I l· I I I 訂· I I--— II (請先閱讀背面之注意事項再填寫本頁) 505946 A7 B7 五、發明說明（ 為達成上述目的，為形成在基板上之多結晶半導體 構件，特徵在於構成元素至少具有辞'氧，結晶定向面係 定向於纖鋅礦構造a軸。 此多結晶半導體構件含有1族細族之雜質，而基板 侧之雜質濃度高亦可。此種多結晶半導體構件係形成於基 板上’包含基板在内在可見區域可以形成具有鄕以上的 穿透率。 此多結晶半導體也可以由結晶性或雜質濃度之至少 者不同的第1與第2多結晶氧化鋅薄膜而形成，且可以用 例如以濺鍍法和MO-CVD法二種方法形成多結晶氧化鋅薄 膜的方式而實現。 訂 也可以用雜質組成不同之第丨與第2多結晶氧化鋅薄 膜形成則述半導體構件，藉此，可以形成電晶體等之主動 元件。
又本發明為多結晶半導體構件之製作方法，其特 徵在於，將導電膜形成於支持基板上，並對前述所形成的 導電膜施加直流偏壓，再以濺鍍法製作成具有&軸定向性 之多結晶氧化鋅薄膜。 經濟部智慧財產局員工消費合作社印製 前述導電膜為具有導電性之I族或ΙΠ族的薄膜，形成 前述多結晶氧化鋅薄膜後，利用加熱的方式，可以將導電 膜在可見區域施以透明化。 進一步，以MO-CVD法，也可以將具有a軸定向性之 第2多結晶氧化鋅薄膜形成於前述多結晶氧化鋅薄膜上， 而’前述導電膜可以是具有導電性之〗族或ΙΠ族的薄膜。 6 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） 505946 A7 _____B7 五、發明說明（4 ) 在MO-CVD法中，也可以在原料中使用冷二酮型化合 物的有機金屬，也可以將此万二酮型化合物的有機金屬施 ； 以預備加熱而分解，並使其與氧氣反應。前述/3二酮型化 1 合物的有機金屬中也可以含有j族或ΙΠ族的雜質。 圖式之簡單說明 第1(a)〜(d)圖為本發明之多結晶氧化鋅半導體構件之 φ 製造過程的示意圖。 第2圖為改變直流偏壓的施加電壓而作成之氧化鋅薄 膜的X射線繞射測定結果之示意圖。 第3圖為Zn(acac)2之分子構造式示意圖。 第4圖為Zn(acac)2之水和物原料（a)及非水和物原料 的TG、DTA測定結果示意圖。 弟5圖為有機金屬氣相成長（MO-CVD)裝置的構造示 意圖。 -------------裝----l·---訂· (請先閱讀背面之注意事項再填寫本頁) 圖 第6圖為製造過程之各階段中，試料之穿透率的示意 線 第7圖為添加Li做為雜質之試料的電阻率變化示意圖 經濟部智慧財產局員工消費合作社印製 第8圖為添加Ga做為雜質之試料的電阻率變化示意圖 〇 第9(a)〜(b)圖所示為將本發明的構件應用於透明電晶 體之例。 實施發明之最佳態樣 參照圖式以詳細說明本發明之實施態樣。 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 五、 經濟部智慧財產局員工消費合作社印製 A7 B7 發明說明（ 第1圖所示為形成本發明之具有a軸定向性的氧化鋅薄 膜之過程。 在製作本發明目的之a軸定向性的Zn0薄膜中，重要 、疋在、、Ό日日〖生基板或非晶質基板上，製作成具有纖鋅礦構 這a軸疋疋向性的氧化鋅薄膜。因此，首先，在透明基板 上知用例如蒸鍍而形成導電性膜120 (參照第l(a)—(b)圖） 適合於透明元件之形成的透明基板110中，非晶質基 板可以使用鉛玻璃、派勒斯玻璃（硬質玻璃， 、石英玻璃等。結晶性玻璃可以舉例如矽晶圓、Mg〇、 鋁、監寶石（sapphire)等。又，導電性膜12〇以氧化鋅之n 型雜質所構成的III族材料為合適。具體的材料可以使用… 、In、Ga、B等之金屬或化合物。但是，用p型雜質所構 成之I族材料來形成導電性膜亦佳。 接著，如第1(c)圖所示，採用施加直流偏壓的高頻濺 鍍法，形成ZnO膜130。直流偏壓之施加法係對堆積在透 明基板110之導電性膜120的表面施加直流偏壓。直流偏壓 採用恆電壓源、恆電流源之那一種都可以。如果可以施加 直流偏壓，則濺鍍電源使用高頻以外的頻率，例如使用微 波亦佳。 第2圖中’改變源自恆電壓源的直流偏壓之施加電壓 時’ X射線繞射測定的結果以圖表示。第2圖所示為採用Ai 做為使玻璃基板上之直流偏壓導電的薄膜的情況之示音圖 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)
505946
五、發明說明（6 ) 經濟部智慧財產局員工消費合作社印製 由弟2圖可知’在正的偏壓電壓下，為纖辞讀構造c軸 之（002)軸變成優先定向，惟直流偏壓在.μ以上時，會 出現為a軸定向之⑽)軸。第2圖之圖表所示的姓果可以 獲得良好的再現性。即使將導電性薄収變成例如為⑽ 合物之rnx氧化錫銦合金），仍然可以獲得大致相同的結 果。此點被認為是因為對基板施加負的0€:偏壓，正離子 對基板表面造成衝擊’六方晶構造t軸定向乃向a轴定向 面傾斜’並再定向而成的結果。 在此狀態中，因為使用A1薄膜，而Zn〇/A1/玻璃構 造的試料A1之穿透率低’會變成*透明而無法利用於透明 裝置中。因此，接著’如第i⑷圖所示，以常壓姆-CVD 法在此試料的表面上形成第2氧化鋅薄膜14〇。在此常壓 MO-CVD法中係於原料中使用乙醯丙_金屬。 以MO-CVD法在第1氧化鋅薄膜上所堆積的第2氧化鋅 薄膜之X射線繞射結果係，反映第丨多結晶氧化鋅薄膜13〇 之結晶定向性，a軸、c軸定向都顯示發生了磊晶（epha_ χί&1) 的成長。因此，如果施加直流偏壓，再於利用濺鍍所形成 之為a軸定向性的第1氧化鋅薄膜上，以m〇_cvD法形 成堆積成的第2氧化鋅薄膜140，則此第2氧化鋅薄膜14〇會 變成具有a軸定向性。 在此，將就常壓MO-CVD法中使用於原料中的乙醯丙 酮金屬作說明。例如，/5二酮型化合物的有機金屬中的一 種為乙醯丙酮鋅（Zn(acac)2)，其為市售試劑，通常純度為 99.80/。〜99_99%。此（Zn(acac)2)中，如第3圖所示之分子結 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） 9 I----裝 illl·· — — 訂·！ — 1! (請先閱讀背面之注意事項再填寫本頁) 505946 A7 B7 五、發明說明（7 --------— (請先閱讀背面之注意事項再填寫本頁) 構式般’有水分子結合在辞元素而成之水和物Ζη(—2 (H2〇)與非水和物之Zn(acac)2。市售之試劑中並無區分二 者的明確記載，而是水和物與非水合物混合販售。2〇(扣扣） (h2〇)在精製過程中結W個分子的水分子而構⑴水和物 ，此乃最安定的水和物。 而，水和物與非水和物的原料評估方法有熱分析法 (DTA)與熱重量（TG)法。熱分析法係測定材料構2發生變 化時之吸熱或發熱反應。熱重量法則測量材料在進行昇華 或蒸發時之重量變化。^4變化對應於加熱速度而顯示出 不同的數值，而吸熱及發熱反應則為材料固有的數值。 經濟部智慧財產局員工消費合作社印製 第4圖所示為zn(acac)2之水和物原料（a)及非水和物原 料（b)之TG、DTA測定結果。TG與DTA之測定條件為昇溫 速度HTC / min、队氣體流量1〇〇 cc / min之大氣壓雾圍氣 。第4圖中之水和物0)的丁(}曲線從50艺附近開始，重量一 點一點的減少，DTA曲線也發現有大的吸熱反應。此點被 認為是因為隨著溫度的上昇，結合於Zn(acac)2材料之Zn 原子而成為水和物的水分子緩緩蒸發所致。若材料被進一 步加熱，則從DTA曲線之熔融波峰（132.1°C)附近開始，重 量減少急遽變大。非水和物原料（b)之TG曲線從60X：附近 開始一樣會減少，而且從比水和物高一些的熔融波峰 (133.4°C)附近開始會急遽減少。 從結晶性及再現性之觀點，在常壓MO-CVD法之薄膜 製作中’相較於非水和物，以使用水和物者為佳。又，在 薄膜之製作中，將水和物與非水和物混合使用的情形會變 10 本紙張尺度_巾_家標準（CNS)A4規格（210 x 297公爱） 經濟部智慧財產局員工消費合作社印製 505946 A7 __________B7__ 五、發明說明（8 )
* 成製作良質的薄膜之阻礙。又，熔融溫度對於良質的ZnO 薄膜之製作是重要的。熔融溫度以132°c至135它的範圍為 . 宜。
〜 在Zn0薄膜的製作中所使用的有機金屬氣相成長（MO -CVD)裝置200示於第5圖。在本發明中，考慮到工業上的 大量生產，而以濺鍍法形成決定結晶方位之第1多結晶氧 _ 化鋅薄膜，並以常壓MO-CVD法形成第2結晶氧化鋅薄膜 第5圖中，常壓M0-CVD的原料Zn(acac)2被充填於玻 璃製的加熱爐（容器）21 8内。原料Zn(acac)2係使用以熱分 析確認其結構安定性之純度99·99%的原料。在加熱爐内 幵華的原料被以流量計（flow meter, FM) 222控制流量之來 自容器212的氮（NO運載氣體運送到使薄膜堆積的反應室 230。而，來自容器214之做為氧原料的氧氣（〇2)為了避免 與原料間的氣相反應，係以玻璃管分離輸送至堆積薄膜的 基板跟前。
Zn(acac)2與氧氣Ο:的反應性低，通常，必需使用純水 做為氧之供給原料。但是，在常壓CVD製程的原料中使 用純水時，在配管和裝置的低溫區域冷凝之水分會隨著用 圍溫度的上昇而再蒸發，已知會造成難以獲得薄膜組成的 再現性。此種情形變成工業製程的障礙之可能性大。第5 圖所示之本發明的裝置200中，為了彌補和〇2氣體的低反 應性’在反應室230的跟前設置預備加熱區域220，利用加 熱而促進Zn(acac)2原料的分解。此構造亦為本發明之一特 -------------裝-----：----訂---------線 (請先閱讀背面之注意事項再填寫本頁)
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五、發明說明（9 ) 徵。 · 形成第2多結晶氧化鋅薄膜14〇後之構造，穿透率大 幅地提咼。此點示於第6圖所示之穿透率圖表中。第6圖之 圖表示出第1圖所示之製造過程的各階段（b)、（c)、（句中 之試料的穿透率。如第6圖所示，具有Zn〇 (SpuUer) / A1 /派勒斯（pyrex)構造之試料（c)的穿透率在55〇 1^為23 0/〇 ，相對地，以MO-CVD法於其上部堆積以〇薄膜而成之試 料（d)的穿透率為80%，向上提昇了約4倍左右。此係因， 形成於玻璃基板110上之A1薄膜12〇的A1原子因形成第2多 結晶氧化鋅薄膜140時之熱，而向第丨多結晶氧化鋅薄膜13〇 擴散所致。因此，以濺鍍法一邊施加直流而在A1薄膜上形 成a軸定向之氧化鋅薄膜（參照第1(c)圖）後，再予以加熱， 也可以提高在這個階段的透明度。此時，即使未形成利用 MO-CVD法之第2氧化鋅薄膜亦可。 也有於第2多結晶氧化鋅薄膜中進一步使用丨族化合物 之Li，Cu，III族化合物之B，Ga，Ιη，μ等的乙醯丙酮金屬 或（DPM)金屬做為摻雜材料，於製作薄膜時添加雜質的情 形。 第7圖為有關添加Li做為雜質的試料之電阻率變化示 意圖。加熱導入有Li原料鋰（Li(DPM))之容器216而調整Li 的添加量。如第7圖所示，隨著使容器216之溫度Tc增加， 電阻率會單調地增加。 第8圖為添加Ga做為雜質之試料的電阻率變化示意圖 。添加的Ga原料係使用乙醯丙酮.（Ga(acac)3)。^之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） (請先閱讀背面之注意事項再填寫本頁)
經濟部智慧財產局員工消費合作社印製 12 505946 A7 B7 五、發明說明（ίο ) 加量係，將導入了 Ga原料乙醯丙酮鎵（Ga(acac)3)之容器2 i 6 予以加熱而整調。由此圖可知，昇高容器216的溫度，則 隨著增加Ga之添加量，電阻率會單調地減少，在11〇艺顯 示出最小值。 如第7圖及第8圖所示，雖然添加（^雜質會顯示出使 電阻率下降之一般的摻雜特性，添加Li則顯示使電阻率增 加的傾向。此點可以考慮是因為未添加雜質的薄膜本來是 η型，因添加p型雜質而變成真半導體之故。透明元件中所 使用的薄膜被要求低電流的作動，所以必需是高電阻，因 而以此特性為宜。 (實施例1) 採用真空蒸鍍法在派勒斯（pyrex)基板上蒸鍍數百Α之 A1薄膜，並在其上部arf濺鍍裝置堆積Zn〇薄膜。八丨薄膜 的電阻係使電極間距離5 mm之針狀電極接觸表面而進行 測定。施加於基板和反應室間之直流偏壓為-1〇〇 V，堆積 過程中的壓力為0.01 Torr。 以常壓MO-CVD法堆積的ZnO薄膜，其原料係使用乙 酿丙酮鋅（Zn(acac)2)及〇2氣體。Zn(acac)：^運載氣體中所 使用的N2和02氣體，流量分別為4〇〇 seem ° A1薄膜之電阻值在3 k Ω以下時，有顯示a軸定向之 ZnO( 11〇)面的繞射波峰，而在此以上的電阻值則會出現 ZnO(0〇2)面的c軸定向。 (實施例2) 第9圖所示為有關應用此構件於透明電晶體中之例。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝—— (請先閱讀背面之注意事項再填寫本頁) · -·線· •經濟部智慧財產局員工消費合作社印製 發明說明（η ) 第9⑷圖為電晶體310之剖面圖。所使用的氧化辞薄膜之 定向性係採用最適合於透明電晶體之電流的流動之a轴。 玻璃基板m上所形成的第i氧化鋅薄膜13〇,膜厚為5〇〇〜 1500A左右。傳導形式因來自堆積在界面的A1電極之A1原 子钠擴散而顯示出η型的傳導形式。第2氧化鋅薄膜14〇的 膜厚成為1000〜2000Α。添加Li於第2氧化鋅薄膜，並堆積 顯示電阻率為1〇4Ω ·⑽的數值之條件的氧化鋅。此電晶 體之總膜厚為例如2500 Α。 閘絕緣膜315可以採用矽的氧化物膜或矽的氮化物膜 。此膜厚亦因閘極驅動電壓而異，可以採用2〇〇〜ι〇〇〇 A 。源極314、汲極312雖係直接將A1電極堆積到第2氧化鋅 膜而使用，惟亦可以使傳導形式不同的雜質在第2氧化鋅 膜擴散，抑制因pn接合導致之漏電流。所獲得之透明電晶 體3 10可以對應閘極電壓的變化而控制沒極電流。 (實施例3) 實施例2中所示之透明電晶體31〇在上部有閘極，而 第9(b)圖之實施例3所示的電晶體32〇則是在下部形成閘極 326。此電晶體320的特徵在於，由於不易受外部環境之影 響，而且是先形成上等品質的閘絕緣膜後再形成電晶體構 件，所以不易受到因閘極電壓變化所導致之滯後現像的影 響。各薄膜之特性、膜厚全部與實施例2相同。此構造的 $明電極和實施例2相比，可以進一步降低off電壓。 505946 A7 B7 五、發明說明（12 ) 110···玻璃基板 120···導電性膜 13,0···多結晶氧化鋅薄膜 140···多結晶氧化鋅薄膜 200"_MO-CVD 裝置 212〜N2容器 214···02 容器 216…Li / Ga(C5H702)3容器 元件標號對照 218 …Ζη ((ϋ5Ι·Ι702)2 容器 220…預備加熱區域 230…反應室 310,320…透明電晶體 312,322…汲極 314,324…源極 315,325···閘絕緣膜 3 16，3 2 6…閘極 --------------^-----^----^---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 15 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. D8 中叫專利範圍 2. 侧17249號專利修正本91年6月21日 二種多結晶半導體構件’其為形成於基极上之多結 導體構件，特徵在於構成元素至少含有 以鋅礦構造㈣。 π Γ:請專利範圍第〗項之多結晶半導體構件，其中前述 =體構件含有1 一雜質，咖 3.=申請專利範圍第2項之多結晶半導體構件，其中前述 夕結晶半導體構件形餘透明基板上，以含基板在可 見區域具有50%以上的穿透率。 4·如申料利範圍第卜3項中任—項之多結晶半導體構件 -中則述多結晶半導體構件係由結晶性或雜質濃度之 至少一者不同的第i與第2多結晶氧化鋅薄膜所形成。 5. 如申請專利範圍第4項之多結晶半導體構件，其中前述 多結晶半導體構件係、由雜質組成不同的第！與第2多結 晶氧化鋅薄膜所形成。 6. -種多結晶半導體構件之製作方法，特徵在於，將導電 膜形成於支縣板上，再對前述所形叙導電膜施加直 流偏壓’以賤鑛法製作成具有3轴定向性之多結晶氧化 鋅薄膜。 7·如申請專利範圍第6項之多結晶半導體構件的製作方法 ’其中前述導電膜為具有導電性之！族或m族的薄膜: 而且於形成前述多結晶氧化鋅薄膜後再加熱。 &如申請專利範圍第7項之多結晶半導體構件的製作方法 本紙張尺度適用中國國家標準（CNS) A4規格（21〇χ297公釐） 16 、申請專利範圍 j其中進-步以MO-CVD法，將具有3轴定向性之第2 夕結晶氧化鋅薄膜形成於前述多結晶氧化辞薄膜上。 9.如申請專利範圍第8項之多結晶半導體構件的製作方法 1〇 述導電膜為具有導電性之1族或職的薄膜。 第8項或第9項之多結晶半導體構件的 屬。/ 〃中原料中使用了沒二_型化合物的有機金 U·如申請專利範圍第Π)項之多結晶半導體構件的製作方 法’其中將前述卜酮型化合物的有機金屬施以預備加 熱分解’並使其與氧氣起反應。 12·如申請專利範圍第10項之多結晶半導體構件”作方 前心二嗣型化合物的有機金屬含有ι族或出 本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公釐） -----------------------裝：................訂..................線· (請先閲讀背面之注意事項再填寫本頁) 17
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