TW503549B - Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified - Google Patents

Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified Download PDF

Info

Publication number
TW503549B
TW503549B TW089116018A TW89116018A TW503549B TW 503549 B TW503549 B TW 503549B TW 089116018 A TW089116018 A TW 089116018A TW 89116018 A TW89116018 A TW 89116018A TW 503549 B TW503549 B TW 503549B
Authority
TW
Taiwan
Prior art keywords
wiring
grid array
package
substrate
ball
Prior art date
Application number
TW089116018A
Other languages
English (en)
Chinese (zh)
Inventor
Kevin Lyne
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW503549B publication Critical patent/TW503549B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
TW089116018A 1999-09-20 2000-08-09 Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified TW503549B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/400,349 US6285560B1 (en) 1999-09-20 1999-09-20 Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified

Publications (1)

Publication Number Publication Date
TW503549B true TW503549B (en) 2002-09-21

Family

ID=23583264

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089116018A TW503549B (en) 1999-09-20 2000-08-09 Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified

Country Status (4)

Country Link
US (1) US6285560B1 (enExample)
EP (1) EP1085571A1 (enExample)
JP (2) JP2001127203A (enExample)
TW (1) TW503549B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859762A (zh) * 2009-04-07 2010-10-13 台湾积体电路制造股份有限公司 半导体装置及其制造方法

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323060B1 (en) 1999-05-05 2001-11-27 Dense-Pac Microsystems, Inc. Stackable flex circuit IC package and method of making same
US6689634B1 (en) * 1999-09-22 2004-02-10 Texas Instruments Incorporated Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
JP3371867B2 (ja) * 1999-10-05 2003-01-27 日本電気株式会社 半導体装置
DE60039569D1 (de) * 1999-11-02 2008-09-04 Canon Kk Gedruckte Leiterplatte
WO2001050526A1 (en) * 1999-12-30 2001-07-12 Intel Corporation Optimized driver layout for integrated circuits with staggered bond pads
US6262895B1 (en) 2000-01-13 2001-07-17 John A. Forthun Stackable chip package with flex carrier
JP3407025B2 (ja) * 2000-06-08 2003-05-19 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US6417463B1 (en) * 2000-10-02 2002-07-09 Apple Computer, Inc. Depopulation of a ball grid array to allow via placement
US6734540B2 (en) * 2000-10-11 2004-05-11 Altera Corporation Semiconductor package with stress inhibiting intermediate mounting substrate
US6940729B2 (en) 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US20060255446A1 (en) 2001-10-26 2006-11-16 Staktek Group, L.P. Stacked modules and method
US6914324B2 (en) 2001-10-26 2005-07-05 Staktek Group L.P. Memory expansion and chip scale stacking system and method
US6956284B2 (en) 2001-10-26 2005-10-18 Staktek Group L.P. Integrated circuit stacking system and method
US7053478B2 (en) 2001-10-26 2006-05-30 Staktek Group L.P. Pitch change and chip scale stacking system
US7371609B2 (en) 2001-10-26 2008-05-13 Staktek Group L.P. Stacked module systems and methods
US7485951B2 (en) 2001-10-26 2009-02-03 Entorian Technologies, Lp Modularized die stacking system and method
US7026708B2 (en) 2001-10-26 2006-04-11 Staktek Group L.P. Low profile chip scale stacking system and method
US7310458B2 (en) 2001-10-26 2007-12-18 Staktek Group L.P. Stacked module systems and methods
US20030234443A1 (en) 2001-10-26 2003-12-25 Staktek Group, L.P. Low profile stacking system and method
US7202555B2 (en) * 2001-10-26 2007-04-10 Staktek Group L.P. Pitch change and chip scale stacking system and method
US7656678B2 (en) 2001-10-26 2010-02-02 Entorian Technologies, Lp Stacked module systems
US7081373B2 (en) 2001-12-14 2006-07-25 Staktek Group, L.P. CSP chip stack with flex circuit
JP2003209202A (ja) * 2002-01-11 2003-07-25 Texas Instr Japan Ltd 半導体装置又はその実装方法
US20050040539A1 (en) * 2002-01-31 2005-02-24 Carlsgaard Eric Stephen Flip chip die bond pads, die bond pad placement and routing optimization
CN1659810B (zh) * 2002-04-29 2012-04-25 三星电子株式会社 直接连接信号传送系统
US7750446B2 (en) 2002-04-29 2010-07-06 Interconnect Portfolio Llc IC package structures having separate circuit interconnection structures and assemblies constructed thereof
US6891272B1 (en) 2002-07-31 2005-05-10 Silicon Pipe, Inc. Multi-path via interconnection structures and methods for manufacturing the same
US6784525B2 (en) * 2002-10-29 2004-08-31 Micron Technology, Inc. Semiconductor component having multi layered leadframe
US7014472B2 (en) * 2003-01-13 2006-03-21 Siliconpipe, Inc. System for making high-speed connections to board-mounted modules
US6762495B1 (en) * 2003-01-30 2004-07-13 Qualcomm Incorporated Area array package with non-electrically connected solder balls
US6916995B2 (en) * 2003-02-25 2005-07-12 Broadcom Corporation Optimization of routing layers and board space requirements for ball grid array package implementations including single and multi-layer routing
EP1460690A1 (en) * 2003-02-25 2004-09-22 Broadcom Corporation Optimization of routing layers and board space requirements in a BGA package (fka BGA package)
US7816247B2 (en) * 2003-02-25 2010-10-19 Broadcom Corporation Optimization of routing layers and board space requirements for ball grid array package implementations including array corner considerations
US7196908B2 (en) * 2003-06-05 2007-03-27 International Business Machines Corporation Dual pitch contact pad footprint for flip-chip chips and modules
US7542304B2 (en) 2003-09-15 2009-06-02 Entorian Technologies, Lp Memory expansion and integrated circuit stacking system and method
JP2005166794A (ja) * 2003-12-01 2005-06-23 Ricoh Co Ltd 部品パッケージとプリント配線基板および電子機器
JP4433298B2 (ja) * 2004-12-16 2010-03-17 パナソニック株式会社 多段構成半導体モジュール
US7309914B2 (en) 2005-01-20 2007-12-18 Staktek Group L.P. Inverted CSP stacking system and method
JP2006303173A (ja) * 2005-04-20 2006-11-02 Mitsubishi Electric Corp 回路基板デバイスおよびその製造方法
US7033861B1 (en) 2005-05-18 2006-04-25 Staktek Group L.P. Stacked module systems and method
US7446398B2 (en) * 2006-08-01 2008-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Bump pattern design for flip chip semiconductor package
US7417310B2 (en) 2006-11-02 2008-08-26 Entorian Technologies, Lp Circuit module having force resistant construction
WO2008096633A1 (ja) * 2007-02-07 2008-08-14 Rohm Co., Ltd. 実装基板および電子機器
US8053349B2 (en) * 2007-11-01 2011-11-08 Texas Instruments Incorporated BGA package with traces for plating pads under the chip
US20090174072A1 (en) * 2008-01-04 2009-07-09 Texas Instruments Incorporated Semiconductor system having bga package with radially ball-depopulated substrate zones and board with radial via zones
JP2009246166A (ja) * 2008-03-31 2009-10-22 Fujitsu Ltd 電子部品パッケージおよび基板ユニット並びにプリント配線板およびその製造方法
US8102667B2 (en) * 2008-10-27 2012-01-24 Motorola Solutions, Inc. Method and apparatus for spatially optimizing surface mount pads on a ball grid array package
US8097964B2 (en) * 2008-12-29 2012-01-17 Texas Instruments Incorporated IC having TSV arrays with reduced TSV induced stress
KR101665556B1 (ko) * 2009-11-19 2016-10-13 삼성전자 주식회사 멀티 피치 볼 랜드를 갖는 반도체 패키지
US8723337B2 (en) 2011-07-14 2014-05-13 Texas Instruments Incorporated Structure for high-speed signal integrity in semiconductor package with single-metal-layer substrate
JP5946370B2 (ja) * 2012-08-28 2016-07-06 ルネサスエレクトロニクス株式会社 電子装置
KR102079795B1 (ko) 2013-07-19 2020-02-21 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 화상형성장치 및 칩
US9853007B2 (en) 2014-12-30 2017-12-26 Microsemi Solutions (U.S.), Inc. Method for producing an integrated circuit package and apparatus produced thereby
US10076033B1 (en) 2016-12-22 2018-09-11 Juniper Networks, Inc. Printed circuit board with connector header mounted to bottom surface
KR20220169043A (ko) * 2021-06-17 2022-12-27 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
CN117390936B (zh) * 2023-12-12 2024-03-15 武创芯研科技(武汉)有限公司 一种芯片封装可靠性模型求解翘曲度的方法及系统

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495377A (en) * 1982-12-30 1985-01-22 International Business Machines Corporation Substrate wiring patterns for connecting to integrated-circuit chips
JP2872825B2 (ja) 1991-05-13 1999-03-24 三菱電機株式会社 半導体装置用パッケージ
US5729894A (en) 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US5424492A (en) * 1994-01-06 1995-06-13 Dell Usa, L.P. Optimal PCB routing methodology for high I/O density interconnect devices
US5491364A (en) 1994-08-31 1996-02-13 Delco Electronics Corporation Reduced stress terminal pattern for integrated circuit devices and packages
JPH09172105A (ja) * 1995-12-20 1997-06-30 Nec Corp 集積回路装置
JPH10173087A (ja) * 1996-12-09 1998-06-26 Hitachi Ltd 半導体集積回路装置
KR100369386B1 (ko) * 1996-12-27 2003-04-08 앰코 테크놀로지 코리아 주식회사 볼그리드어레이반도체패키지용인쇄회로기판및이를이용한볼그리드어레이반도체패키지의봉지방법
JP3386977B2 (ja) * 1997-06-05 2003-03-17 新光電気工業株式会社 多層回路基板
JPH11102990A (ja) * 1997-09-29 1999-04-13 Canon Inc 格子状に配列された複数の接続端子を有する電子部品を実装したプリント配線基板
US6133134A (en) * 1997-12-02 2000-10-17 Intel Corporation Ball grid array integrated circuit package
JPH11214832A (ja) * 1998-01-26 1999-08-06 Sumitomo Metal Electronics Devices Inc 回路基板のめっき線の形成方法
JPH11251353A (ja) * 1998-03-03 1999-09-17 Canon Inc 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859762A (zh) * 2009-04-07 2010-10-13 台湾积体电路制造股份有限公司 半导体装置及其制造方法

Also Published As

Publication number Publication date
EP1085571A1 (en) 2001-03-21
US6285560B1 (en) 2001-09-04
JP2001127203A (ja) 2001-05-11
JP2012069984A (ja) 2012-04-05

Similar Documents

Publication Publication Date Title
TW503549B (en) Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified
US6664483B2 (en) Electronic package with high density interconnect and associated methods
US7615872B2 (en) Semiconductor device
US7781325B2 (en) Copper pillar tin bump on semiconductor chip and method of forming the same
US7038917B2 (en) Low loss, high density array interconnection
US7102222B2 (en) Conductive trace structure and semiconductor package having the conductive trace structure
CN102804372A (zh) 具有降低电感的结合键合元件的微电子组件
JP3851797B2 (ja) ボールグリッドアレーパッケージとそれに用いられる回路基板
US6479894B2 (en) Layout method for thin and fine ball grid array package substrate with plating bus
CN1568543B (zh) 半导体元件
US6160313A (en) Semiconductor device having an insulating substrate
CN101447471B (zh) 用于半导体封装的基板及使用该基板的半导体封装
JP2007081374A (ja) ソルダマスク限定型ボンディングパッド及びソルダマスク非限定型ボンディングパッドを具備した半導体パッケージ、印刷回路基板及び半導体モジュール
CN102036475B (zh) 布线板
TW544822B (en) Common electrode line for plating
US20240395675A1 (en) Semiconductor device and mounting structure thereof
US8530754B2 (en) Printed circuit board having adaptable wiring lines and method for manufacturing the same
KR20100123415A (ko) 인쇄회로기판
JP3875407B2 (ja) 半導体パッケージ
JP2002031663A (ja) テスト用マルティプルライングリッド、半導体チップ、並びに、半導体チップの性能チェック用テスト素子
US20080083115A1 (en) Method for repairing metal finish layer on surface of electrical connection pad of circuit board
US6364669B1 (en) Spring contact for providing high current power to an integrated circuit
US20130153278A1 (en) Ball grid array package and method of manufacturing the same
KR20230115476A (ko) 기판 및 기판 제조 방법
TW200810045A (en) Semiconductor package substrate and method for manufacturing the same

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent