TW494531B - Semiconducting system and production method - Google Patents

Semiconducting system and production method Download PDF

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Publication number
TW494531B
TW494531B TW090105332A TW90105332A TW494531B TW 494531 B TW494531 B TW 494531B TW 090105332 A TW090105332 A TW 090105332A TW 90105332 A TW90105332 A TW 90105332A TW 494531 B TW494531 B TW 494531B
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TW
Taiwan
Prior art keywords
film
copper
wiring
semiconductor device
cobalt
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Application number
TW090105332A
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English (en)
Inventor
Hiroshi Nakano
Takeyuki Itabashi
Haruo Akahoshi
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Hitachi Ltd
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Publication of TW494531B publication Critical patent/TW494531B/zh

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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835Combinations of two or more different dielectric layers having a low dielectric constant
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864Thermal treatment
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865Selective removal of parts of the layer
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemically Coating (AREA)

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494531 A7 __B7______ 五、發明説明(1 ) [發明領域] 本發明關係於一半導體裝置及其製造方法,更明確地說, 關係於一半導體裝置及其製造方法,其中,該半導體裝置具有 由銅作成之接線結構,並具有一基本結構,其具有一線保護膜 • 於該銅接線旁,覆蓋銅接線的頂部,及一阻障膜包圍該銅接 線的側及底部。 [先前技藝的說明] 裝置之操作速度的改變係需要完成更高積集度及半導 體裝置的先進能力。這要求係跟隨著LSI內部接線之縮小及 膜層數量之增加的製程。接線的縮小及層膜數量的增加將 造成接線電阻及接線間能力之增加,並將影響於接線中之信 號傳送速度。因爲速度增加係受到由於延遲時間的限制,層 間絕緣膜之介電常數係被降低,以減少接線間電容。於此時, 該操作速度係藉由使用較低電阻之接線材料來降低接線電 阻,而改良操作速度。 有很多硏究已使用具有1.7 // Ω cm低比電阻之銅,作爲 ^ 接線材料。至於形成一銅接線的技術,雙層嵌入法係爲一引 | 入注意的方法。以此參考第丨〇圖說明此方法的例子: 4 | 絕緣膜4(第10a圖中)係被形成於基材(於此例子中,相 :] 當具有下層接線2b之下層接線層10a並提供有線保護膜8, 其特徵在於一高絕緣在所有側)(在第1 Ob圖中)。一接線凹 ^ 槽7,以內藏接線及一連接孔10以連接上及下接線係形成在 : 該絕緣膜4上。因爲一絕緣線保護膜8係位於下層接線層 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -4 - (請先閲讀背面之注意事 項再填寫· 本頁) 494531 A7 B7 五、發明説明(2 ) l〇a及絕緣膜4之間,線保護膜8可以由連接孔10之底部去 除(第10c圖)。於阻障層3被形成於接線凹槽7及連接孔上 之後(第10d圖),一種層5係形成於其上(第l〇e圖),並被塡以 接線材料6(第l〇f圖)。然後,CMP(化學機械硏磨)係被用以 去除接線材料6之過量部份,及接線插塞1 1係同時形成於上 層之接線2及連接孔10中(第i〇g圖)。然後,該線保護膜8 係被形成,以覆蓋接線2及絕緣層4(第1 Oh圖)。此雙層嵌入 法允許接線2及接線插塞1 1被一次形成,藉以確保製造成本 之大量降低。 另外,銅與絕緣膜4反應並擴散於絕緣膜中。爲了確保 良好之接線可靠度,絕緣線保護膜8及阻障膜3必須如上所 述提供於銅接線2及絕緣膜4之間。傳統上,例如氮化鈦,氮 化鉅及氮化鎢之氮化物金屬可以防止銅擴散,及例如鉅及鎢 及其合金之高熔點金屬已經被使用作爲阻障層3 。同時,絕 緣氮化矽膜(SiN)已經被使用作爲在銅接線2上之線保護膜8 (請先閲讀背面之注意事 1# 項再填< 裝-- 寫本頁) Φ 1 μ l :才 i 然而,SiN具有7.0至9.0之比介電常數。其具有Si〇2之 絕緣膜的兩倍之介電常數。因此,其阻礙了於極端細微接線 圖案中之接線間電容量的降低。爲了克服此問題,電容量必 須藉由形成一導電膜係爲在接線頂面上之線保護膜加以降 低。 美國專利第5,695,8 1 0號揭示一鈷鎢磷導電膜係藉由無 電電鍍加以形成爲線保護膜。於鈷鎢磷無電電鍍中,次磷酸 鈉係經常被使用作爲還原劑。次磷酸鈉係爲一已知不活性 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) •5- 494531 A7 _ B7 五、發明説明(3 ) 還原劑,不會有反應發生於銅上,其不能直接鍍於銅上(如由 美國佛州之美國電鍍者及表面加工協會之第318頁之”無電 電鍍-基礎及應用”)。因此,於例如鈀之種層施加至銅接線後, 鈷鎢磷膜必須被電鍍。然而,於此時,銷可能與構成接線層之 銅反應,而增加了銅電阻。再者,銷可以沉積於絕緣層上而不 是接線上,及鈷鎢磷膜可能形成於接線外之絕緣上。因此,當 生產細微接線時,這涉及了降低需要接線間絕緣之問題。 再者,日本專利公報1 6906/1 999揭示該含鈷無電電鍍係 被使用作爲抗氧化劑膜。然而,由該法所取得之含鈷膜具有 不夠之防銅擴散的能力。若於半導體形成製程或形成後執 行熱處理,則銅可能經由含鈷膜擴散入SiCh中。 日本專利公報1 20674/1 994揭示於生產電路基材中,一 由鎢鈷硼合金作爲主成份之中間金屬膜係被形成在接線板 之表面上,其係被提供有一接線導體,並係塗覆以由銅作成之 電路導體。然而,由鎢鈷硼合金作爲主成份之中間金屬膜係 想要增加於電路基材表面上之鎢或鉬之接線連接器及形成 於其表面上之銅的電路導體間之黏著力;其並不作爲一於銅 接線及絕緣間之線保護膜。 如上所述,已經被使用作爲線保護膜之SiN爲絕緣,並具 有商比介電常數。這係爲一阻礙接線間電容量降低之因素 。爲了解決此問題,一接線保護膜可以被以金屬材料加以形 成,以允許電容量之降低。然而,例如氮化鈦,氮化鉅及氮化 鎢之氮化物金屬被作爲一線保護膜,例如鉅及鎢之具有高熔 點之金屬並不能在選擇下形成於銅接線上。爲了避免於線 -6- (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 494531 A7 B7 五、發明説明(4 ) (請先閲讀背面之注意事項再填寫本頁) 間之短路,則需要如圖案化及蝕刻之此等複雜製程。這將使 接線形成精確度及可靠度劣化。因此,此二事項必須解決,以 金屬材料形成線保護膜。 (1)爲了確保銅接線可靠性,有必要形成一金屬材料,其能 防止銅擴散,而不會允許銅接線於熱處理中氧化。 (Π)示於(1)中之金屬材料必須以一選擇基礎形成在銅接 線上。 一種符合此兩種要求之形成方法必須加以提供。當例 如氮化鈦,氮化鉅及氮化鎢之金屬氮化物,例如鉅及鎢或其合 金之具高熔化點之金屬被使用作爲一阻障膜時,一種層必須 被形成,以提供因爲高電阻之銅電鍍。特別是,若能作爲功率 饋送層之阻障膜可以被形成時,則電鍍銅可以直接提供於阻 障膜上,及導電膜(銅接線膜)可以有效形成。特別是,當無電 電鍍被使用以形成一導電阻障膜時,阻障膜可以均勻地形成, 而不管接線的複雜架構,其有效地作爲電鍍銅之種層。然而, 符合這些要求之線保護膜或阻障膜於現在係爲未知的。 [發明槪要] 本發明之目的係解決上述先前技藝的技術上的問題。 更明確地說,本發明係想要防止由於銅接線氧化之電阻上升 及由於銅擴散之銅接線及元件之可靠度降低。同時,吾人想 要提供一半導體裝置及其形成方法,其中該半導體裝置係被 提供有一銅線保護膜及/或阻障膜允許均勻地形成銅接線膜, 而不管其複雜架構。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 494531 A7 ___B7_ 五、發明説明(5 ) 爲了完成上述目的,本發明提供一半導體裝置,其包含一 線保護膜,以覆蓋形成於絕緣膜中之銅接線之頂部,及一阻障 膜包圍住銅接線的側及底部,其中該線保護膜及/或阻障膜係 以鈷合金膜加以形成,該合金膜包含(1)鈷,(2)鉻,鉬,鎢,銶,銥, 及磷之至少之一,及(3)硼。 依據本發明之半導體裝置更特徵在於: 多數層之銅線係形成於絕緣膜中, 接線保護膜及阻障膜係被覆蓋以鈷合金膜,該膜包含(1) 鈷,(2)鉻,鉬,鎢,銶,銳及磷之至少之一,及⑶硼,及 該在上層上之銅線係經由該阻障層電氣連接至在下層 上之銅線。 於另一實施例中,該半導體裝置生產方法係特徵在於一 作爲蝕刻停止層之絕緣膜係進一步形成在線保護膜所形成 之區域以外之絕緣膜之表面上。在所有表面上形成此一蝕 刻停止層使半導體裝置製程中容易完成蝕刻連接。 本發明揭示了一半導體裝置生產方法,其特徵在於 半導體裝置包含一線保護膜,以覆蓋形成於絕緣膜中之 銅接線頂部,及一阻障膜包圍注銅接線的側及底部; 其中該線保護膜及/或阻障膜係以鈷合金膜加以形成,該 鈷合金膜包含(1)鈷,(2)鉻,鉬,鎢,銶,鉈,及磷之至少之一,及 (3)硼。 本發明由於銅接線的氧化之電阻增加,及由於銅擴散造 成之銅接線及元件之可靠度的降低,並允許線保護膜被以選 擇爲基礎單獨形成於銅接線上。然後,阻障膜係由導電銘合 (請先閲讀背面之注意事項再填寫本頁) ▼裝.
、1T 本纸朵尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) -8 - 494531 A/ B7 五、發明説明(6 ) 金膜形成,銅可以直接塗覆於阻障膜上,而不需要任何功率饋 送層。這解決了孔隙形成之問題並免除了形成一種層的步 驟。 於依據本發明之半導體裝置中,該鈷合金,即線保護膜及 /或阻障膜係較佳具有100奈米或更少之厚度,並包含50至 95原子百分比鈷作爲主成份,1至40原子百分比之鉻,組,鎢, 銶,銳及磷之至少之一,及0.1至10原子百分比之硼。 以下參考附圖,說明依據本發明之半導體裝置及其生產 方法的較佳實施例。依據本發明之半導體裝置係基本上依 據以下製程步驟加以製造(見第1圖): U)形成一絕緣膜4於基材10a上(並不限定於下述之下 層銅接線2b及線保護膜la,其係已經形成於第la圖中作爲 絕緣層(第1 b圖)); (b)形成一接線凹槽7及連接孔10於絕緣膜4上(第lc 圖); (c)形成一阻障膜3於接線凹槽7及連接孔10中(第Id 圖); 齊 I 】才 i (d) 形成一種層5於該阻障膜> 上(第le圖); (e) 內藏銅膜6於接線凹槽7及孔10中(第If圖); (f) 藉由去除形成於絕緣膜4上而不是接線凹槽7及孔 1〇中之銅6,而形成銅接線2及接線插塞11(第lg圖); (g) 形成線保護膜1於銅接線2的表面(第lh圖)。 一具有接線層積層於多層上(於圖中爲四層)之半導體裝 置係藉由重覆步驟(a)至(g)若干次加以完成,如同於第2圖所 -9 - (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 494531 9Κ 6.\ Η F; 舞立匕彌兀 la 第90105332號專利申請案 中文說明書修正頁A7 民國91年6月修正 B7 五、發明説明(7 ) 75 0 (請先閱讀背面之注意事項再填寫本頁) 低介電常數之Si〇2,倍半氧化物氫氧化物及甲基聚矽氧 院之絕緣材料及其積層膜可以使用作爲絕緣膜4。銅接線2 可以藉由電鍍銅或無電電鍍加以形成。如由後述,形成種層 5之步驟可以被免除,以銅接線2之無電銅電鍍可以當依據 本發明之鈷合金膜被使用作爲阻障膜3時被完成。 例如鈦,鉬及鎢或其合金之高熔點材料,及例如氮化鈦, 氮化钽,及氮化鎢之氮化物膜可以被使用作爲阻障膜3。再 者,依據本發明之鈷合金膜可以被使用。於此時,形成步驟係 藉由將被提供有接線凹槽7及孔10之基材浸入鈷爲主無電 電鍍浴中。 經濟部智慧財產局員工消費合作社印製 該鈷爲主無電電鍍浴包含金屬鹽,還原劑,完成劑,pH調 整劑及添加劑。氯化鈷,硫化鈷,及硝酸鈷可以使用作爲鈷鹽 。至於鎢鹽,有可能使用鎢酸鈉,鎢酸銨,三水合磷酸銨,五水 合仲鎢酸銨,η-水合磷鎢酸鈉,12-鎢矽酸26-水,鎢酸,氧化鎢, 檸檬酸鎢鈉,二矽酸鎢,硼酸鎢等。較佳使用鎢酸鈉,鎢酸胺, 鎢酸及檸檬酸鎢鈉。至於鉬鹽,有可能使用鉬酸,氯酸鉬,鉬 酸鉀,二水合鉬酸鈉,鉬酸銨,η-水合鉬酸矽化物,乙醯丙酮酸 氧化鉬,η-水合磷鉬酸鈉,硼酸鉬等。至於鉻鹽,也有可能使用 鉻酸銨,十二水合硫酸銨鉻,六水合氯酸鉻,硫酸鉻,η-水合,氧 化鉻,硼酸鉻,二水合重鉻酸鈉等。至於銶鹽,有可能使用高 銶酸銨,六氯銶酸鉀等。至於鉈鹽,有可能使用硝酸鉈,甲酸 鉈,硫酸鉈,氧化鉈等。磷可以由單水合次膦酸鈉,3-氨基丙次 膦酸及次膦酸。 -10- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 494531 A7 ___B7_ 五、發明説明(8 ) (請先閲讀背面之注意事項再填寫本頁) 爲了選擇性地只在銅接線2上形成形保護膜,還原劑係 爲聯氨及硼化合物,其中反應進行於銅接線2及鍍鈷膜之表 面上。有可能使用二甲胺硼烷,乙胺硼烷,胺硼烷,嗎林硼烷, 比定硼烷,六氫比定硼烷,乙二胺硼烷,乙二胺二硼烷,第三丁 胺硼烷,咪唑硼烷,甲氧乙銨硼烷,硼氫化鈉,等。使用此一還 原劑允許線保護膜1被直接形成於銅接線2上,而不必施加 例如鈀之電鍍觸媒。 檸檬酸,丁二酸鹽,丙二酸鹽,蘋果酸鹽,酒石酸鹽等係較 佳使用作爲完成劑。例如氫氧化鈉及氫氧化鉀之氫氧化鹼 金屬,及例如氨,四甲基銨,四乙基銨,膽鹼等係較佳被使用作 爲pH調整鹼溶液。一例如硫尿,糖精,硼酸,硝酸鉈及聚乙二 醇可以被使用作爲添加劑。電鍍溶液之溫度較佳爲由40至 90 〇C。 藉由使用此鈷爲主無電電鍍浴所形成之線保護膜1以 選擇爲主,如所示地覆蓋在銅接線2之頂部。於此,線保護膜 1展現由銅接線2之等向性成長,使得膜不只成長於銅接線2 上之方向。它由銅接線2之邊緣成長至阻障膜3或絕緣膜4 之頂部等於保護膜1之厚度。當線保護膜1之係薄於阻障膜 3時,其成長至阻障膜3之頂部。若線保護膜1係厚於阻障膜 3,則其延伸至阻障膜3上絕緣膜4之頂部。再者,若於形成於 步驟(c)中之阻障膜3之表面中之電鍍反應係活躍的,則其係 藉由延伸超出絕緣膜4之頂部,等向地由阻障膜3之邊緣形 成,如於第3圖所示。因此,由於線保護膜之等向性成長,線保 護膜1之邊緣爲圓形並不是矩形。 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) -Ή - 494531 6 A7 B7 五、發明説明(9 ) (請先閲讀背面之注意事項再填寫本頁) 當銅接線2之去除量由於步驟⑴中之過量硏磨,而大於 阻障膜3之去除量,及銅接線2係較阻障膜3下凹時,即,當 所謂碟形化發生時,銘爲主無電電鍍溶液係被選擇,以確保沉 積只發生在銅接線2之頂部,而沒有沉積在阻障膜3上。然 後,銅接線2之下凹部可以被降低,並且,這係較佳的。 [圖式簡要說明] 第la-h圖爲一製程,顯示如何生產依本發明之一實施例 之半導體裝置; 第2圖爲一剖面圖,顯示代表本發明之半導體裝置的實 施例; 第3圖爲一剖面圖,顯示代表本發明之半導體裝置的另 一實施例; 第4圖爲一剖面圖,顯示代表本發明之半導體裝置的另 一實施例; 第5圖爲一剖面圖,顯示代表本發明之半導體裝置的另 一實施例,其中提供有兩蝕刻停止層; 經濟部智慧財產局員工消費合作社印製 第6圖爲一剖面圖,顯示代表本發明之半導體裝置的另 一實施例,其中一蝕刻停止層係只提供在接線層之頂端上; 第7a -h圖爲一製程,例示如何生產具有示於第5及6圖 之蝕刻停止層.9之半導體裝置; 第8圖爲一剖面圖,代表一傳統半導體裝置; 第9圖爲一表面圖,代表一傳統半導體裝置; 第10a-h圖爲一製程,顯示如何生產一傳統半導體裝置; -12- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 494531 A7 B7 五、發明説明(10) 第11圖爲一剖面圖,代表本發明之半導體裝置之另一實 施例;及 (請先閲讀背面之注意事項再填寫本頁) 第12圖爲一剖面圖,代表本發明之半導體裝置之另一實 施例。 [符號說明] 1 線保護膜 la 線保護膜 2 銅接線 2b 銅接線 3 阻障膜 4 絕緣膜 5 銅種層 6 銅膜 7 接線凹槽 8 線保護膜 9 觸媒 10 連接孔 11 接線插塞 13 接線間故障沉積部 14 接線間短路位置 16 絕緣膜 17 蝕刻停止層 18 絕緣膜 本紙張尺度適用中準(CNS ) Α4^ ( 21〇χ297公羡):ΐ3 - " "—---— 494531 A7 B7 五、發明説明() 19 蝕刻停止層 20 Si〇, 21 氮化矽膜 22 開口 23 光阻 (請先閲讀背面之注意事項再填寫本頁) [較佳實施例的說明] (實施例1) 以下實施例將參考第1圖加以說明。元件係形成於矽 基材上,該基材具有200mm直徑,以形成一銅接線2b在一下 層(第la圖)。因此,形成有具有厚1微米之SiCh絕緣膜4(第 1 b圖)。接線凹槽7及連接孔1 0係藉由乾蝕刻加以形成(第 lc圖)。接線凹槽7係0.3微米寬,及連接孔10具有0.3微米 直徑。然後,Ta係藉由濺鍍被形成於具有50奈米之膜中,該 膜作爲阻障膜3(第Id圖)。然後,銅係被形成至150奈米的 厚度成爲一種層5(第le圖)。對於銅種層5,膜係被使用銅濺 鍍Ceraus ZX- 1000(日本真空有限公司)之長距濺鍍系統,以每 分200至400奈米之速度形成。基材係被浸於以下所示之電 鍍溶液中,並受到24 °C之溶液溫度電鍍及1安每平方公分之 電流密度5分鐘。銅係被內藏於接線凹槽7及連接孔1 0中, 以形成銅膜6。含磷銅係被使用作爲一陽極。 硫酸銅:〇.4mol/dm3 硫酸:2.0mol/dnr’ 氯離子:1.5 X 10·'mo 1/dm3 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -14 - 494531 A7 _ B7_ 五、發明説明(12 )
Microfab Cu2100:10 X l(T3dm3/dm3(由日本電鍍密封公 司之鍍銅添加劑)。 (請先閱讀背面之注意事項再填寫本頁) 然後,用IP E C之化學機械硏磨設備,一銘土分佈輪含1 至2%之過氧化氫,及一墊(羅德公司之IC 1000)進行化學機械 硏磨。硏磨係以190克每平方公分之硏磨壓力,進行直到阻 障膜3爲止,以分離接線導體並形成銅接線2(第lg圖)。然 後,係被淸洗於5重量百分比硫酸1分鐘,然後於純水中1分 鐘。 隨後,基材係被浸於以下電鍍溶液中,以形成線保護膜1, 並受到鈷爲主無電電鍍在以下之電鍍條件下(第lh圖):然後 基材以純水淸洗。 氯化鈷:0.1莫耳/dm3 檸檬酸鈉:0.3莫耳/dm3 對甲胺硼:0.06莫耳/dm3 鎢酸鈉:0.03莫耳/dm3 RE610:0.05g/dm3(由東和科學有限公司所製之表面劑) 電鍍條件: !本f .^_Ϊ?Λ4 岈 t ,-7,91:3 V ^-·£.卩 ^ ρΗ:9·5(由K〇H所調整)
溶液溫度:75 °C 電鍍時間:1 0分鐘 於上述程序中所生產之半導體裝置係以FIB(聚焦離子 束)加以處理。包含接線凹槽7及連接孔1 0之裝置的剖面係 以一掃描式電子顯微鏡(此後被簡稱爲”SEM”)加以觀察。可 以看出具有膜厚80奈米之鈷-鎢-硼合金係均勻地沉積於銅 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -15 - 494531 A7 —__B7_ 五、發明説明(13 ) 接線2之表面上。然而,於絕緣膜4上未看到鈷-鎢-硼合金之 沉積。因此,可以淸楚了解線保護膜1可以依據本發明之電 鍍方法,只形成於銅接線2上。 所取得之鈷合金係爲一歐格電子頻譜儀加以分析。可 以看出該膜係被爲一無電電鍍膜,其包含79原子百分比鈷 ,20原子百分心鎢及1原子百分比硼。 然後,半導體裝置係受到於2%氫及98 %氦氣體500 °C之 氣氛中3 0分鐘。表面係爲歐格電子頻譜儀所量測,但銅並未 在表面上檢測出。作爲接線材料之銅的擴散並未看到。於 熱處理前後,沒有接線電阻。由於銅氧化之接線電阻的增加 並未被看到。 因此,依據本發明之無電電鍍,作爲線保護膜i之鈷-鎢-硼合金係以選擇爲基礎被形成於銅接線2上。再者,線保護 膜1防止銅接線2之氧化及銅由銅接線2擴散入絕緣膜4,並 降低了於銅接線2之電阻增加。因此,可以取得高度可靠之 半導體裝置。 (參考例1) 以下顯示依據本發明之無電電鍍之鈷-鎢-磷化物合金膜 之線保護膜1的例子。 參考例1:次磷酸鈉係被使用作爲鈷-鎢-磷化合物電鍍溶 液作爲還原劑,使得電鍍反應並不會發生於銅上。電鍍並火 會直接執行於銅接線2上。電鍍需要觸媒9例如鈀被事先提 供於銅接線2上。作爲電鍍的預處理,以下鈀觸媒製程係被 -16- (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國ϋ家標準(CNS )八4祕(21〇><297公羡) 494531 A7 _— _B7_ 五、發明説明(14 ) 執行於具有銅接線2形成於其上之矽基材上。 氯化鈀:0.003莫耳/dm3 鹽酸:1 X 10·3莫耳/dm3 乙酸:0.5莫耳/dm3 氫氟酸:5 X 1〇·3莫耳/dm3 溫度:24°C 時間:1 0秒 於觸媒處理中,一平均大小50奈米之鈀係以絕緣方式被 沉積於半導體裝置的表面上。一旦被以純水淸洗約1分鐘 後,半導體裝置係被浸於如表1所示之電鍍溶液中並在相同 於實施例1之電鍍條件下受到鈷爲主無電電鍍。在鈷爲主 無電電鍍時,半導體裝置係被淸洗於純水中。 此半導體裝置之剖面係以SEM加以觀看,及鈷-鎢-磷化 物合金電鍍膜係被沉積於表面上。此鈷合金係爲無電電鍍 膜,其包含84原子百分比鈷,8原子百分比鎢及8原子百分比 磷化物。接線間故障沉積部13(第8圖)及接線間短路位置 14係被在半導體裝置的表面找到(第9圖),除了形成於銅接 線2之線保護膜1之外。同時,表面不規則增加。 然後,半導體裝置係回火於400 °C約30分鐘,於2百分比 氫及98百分比氦氣的氣氛中,以及6原子百分比銅係被檢測 於表面上。作爲接線材料的銅的擴散也被看到。再者,於力口 熱前後展現增加10%之接線電阻。 (實施例2至5) -17- (請先閲讀背面之注意事項再填寫本頁) 木纸張尺度適用中國國家標準(CNS ) A4規格(210X29*7公釐) 494531 A7 __B7__ 五、發明説明(15 ) 以下顯示其他之實施例2至5,其中鈷-鎢-硼合金係被形 成於銅接線2之表面上作爲線保護膜1。 於實施例2中,鈷爲主無電電鍍溶液係被作成如表中所 示之氨鹼,及沒有含鹼之電鍍溶液係被使用。電鍍條件係相 同於實施例1者。氨水係被用以備製酸性(pH)。 於實施例3中,銘爲主無電電鍍溶液具有如表1所示之 成份百分比。保護膜1係如於實施例1中被形成。於實施例 4中,銅接線2係被以無電電鍍形成,及線保護膜1係被形成 於銅接線2上,藉由鈷爲主無電電鍍。類似於實施例1,元件 係被形成於矽基材上,及銅種層5係被形成於接線凹槽7上 及連接孔10上(第le圖)。然後,基材係被浸於以下銅電鍍浴 中,用以形成銅膜6。 硫酸銅:0.4莫耳/dm3 伸乙基二胺四乙酸二鈉:〇·1莫耳/dm3 甲醛:0.03莫耳/dm3 2,2’-雙比定基:〇.〇〇〇2莫耳/dm3 聚乙二醇:0.03莫耳/dm3(平均分子量:600) 電鍍條件: pH:9.5(以氫氧化鈉調整)
溶液溫度:70 °C 隨後,化學機械硏磨係被執行,以分離接線導線。然後, 執行鈷爲主無電電鍍,如同於實施例1中之情形一般。 用於實施例5中之鈷爲主無電電鍍溶液係爲鹼性的,使 用鹼四甲銨,如於表1所示。其使用沒有含鹼金屬之電鍍溶 • 18- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(21〇x297公慶) 494531 A7 B7 五、發明説明(16 ) 液。電鍍條件係相同於實施例1者,假設四甲銨水被使用以 調配酸性(pH)的話。 鈷-鎢-硼合金係被均勻地沉積於生產於上述步驟中之實 施例2至5之半導體裝置之銅接線2上。鈷合金沉積並未於 絕緣膜4看到。因此,依據每一實施例中之電鍍,線保護膜1 可以只形成於銅接線2之表面上。 然後,實施例2至4之半導體裝置係被回火於400 °C,及 實施例5之半導體裝置係在2百分比氫及98百分比之氨氣 氛下,於500 °C中30分。 於這些實施例中,銅並未檢測於銅上,及銅的擴散成接線 材料並未看到。表1顯示於線保護膜1中以歐格電子顯微鏡 所量測之每一實施例的成份百分比。 (請先閲讀背面之注意事項再填寫本頁) ·£成‘7 .^?!Λ1 ,»7,:ar r 一 污旁>卞 £ .PVJ欠 -19- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 494531 明發 \ 五 I 銅擴散 未擴散 未擴散 未擴散 未擴散 未擴散 擴散6 原子% 保護膜厚 (奈米) 〇 S • 電鍍溶液 Q. • • • • • OO 一 一 一 〇〇 m oo ON 5Ξ υη οο ON oo (由東和科學公 司之表面劑) (g/dm3) 0.05 0.05 0.05 0.05 0.05 0.05 鎢酸 (莫耳/-/dm’) • • • 0.03 鎢酸銨 (莫耳/dm5) • 0.03 • • • 鎢酸鈉 (莫耳/dm) 0.03 0.03 ρ 0.03 0.03 0.03 次磷酸鈉 (莫耳/dm) • • • • 對甲胺硼 (莫耳/dm5) 0.06 0.06 0.06 0.06 0.06 • 檸檬酸 (莫耳/dm3) • • • • 檸懞酸氫二胺 (莫耳/dm1) • rn • • • 檸懞三鈉 (莫耳/dW) rn cn • rn 氯化鈷 (莫洱/dm1) 1 . 5 5 5 5 5 實施例1 實施例2 實施例3 實施例4 實施例5 參考例 (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -20- 494531 A7 _ B7 五、發明説明(18 ) 依據上述之步驟,一鈷·鎢·硼合金可以選擇地形成於銅 接線2上,作爲於實施例2至5中之線保護膜1,如同於實施例 1,以取得高可靠半導體裝置。再者,一線保護膜係使用電鍍 溶液加以形成,而沒有實施例5中之含鹼金屬。這已經成功 地避免由於此例如鈉或鉀之鹼金屬之污染。 (實施例6至13及參考例2至3) 於實施例6至1 3中,一線保護膜1係形成於示於表2中 之成份之百分比,及服務壽命測試係被進行。對於每一實施 例之半導體裝置,示於第2圖之接線層係被生產於四層中,藉 由重覆示於第11圖中之步驟1至8。於服務壽命測試中,接 線電阻之上升係於600小時及1 200小時後被量測。 接線形狀(a)線寬:0.3微米(b)膜寬:1.0微米(c)線長 :2.5mm 測試條件(a)溫度:175 °C(b)電流密度:3 X 106安每平方 公分。 表2顯示線保護膜1之成份百分比及服務壽命測試之結 果。表2顯示參考例2,其中一線保護膜未被形成,及參考例 3,其中鈷-鎢-磷膜係被形成爲線保護膜1,類似於參考例1。 -21 - (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 494531 A7 B7 五、發明説明(19 ) 服務壽命測試 I 銅擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 已擴散 回火前後間之接線電阻比(%) Γ 1200小時 2%或更低 cn 寸 寸 m WO 1 ! 600小時 1%或更低 1 Ή C<J CN m η 4 CO CS1 姑合金組成(原子%) PQ 1 '4 r Η CN 1—Η ,_·Η 1' Ή 無線保護膜層 〇 1 1 擊 1 1 1 1 9 " 1 Cu 1 1 1 1 1 1 1 1 οο cn 〇〇 On οο οο CTn 79.8 〇 Γ— οο ON Ο 1 i 匡 f ·Η CNJ 1丨·— cn ......·4 Γ<1 ㈣ 變 變 .舻 Μ s {_ H « (請先閲讀背面之注意事項再填寫本頁)
本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -22- 494531 A7 B7 五、發明説明(2〇 ) 實施例1 3之鈷·鎢-硼合金膜包含11百分比氧。此氧係 爲一不純成份,其當於形成線保護膜1時形成。當於其他實 施例中之更細分析時,碳,氯,硫,重金屬及其他雜質均被包含 。然而,接線電阻的上升係遠小於參考例2及3。再者,銅並 未於絕緣膜4中被檢出。再者,含此氧之鈷合金膜係有效於 作爲線保護膜1。 依據示於表2之結果,於實施例6至13中之鈷-鎢-硼合 金的線保護膜顯示一較參考例2及3爲小之接線電阻上升。 於絕緣膜4中未檢測出銅。因此,於實施例6至1 3中之線保 護膜1係穩定一長時間,並防止銅接線2之氧化及銅由銅接 線2擴散入絕緣膜4,,藉以取得一高可靠度之半導體裝置。 (實施例14至25) 於實施例14至25中,銅接線2係被形成於矽基材上,如 同於實施例1般。此基材係被浸於示於表3中之電鍍浴中, 並受到鈷爲主之無電電鍍。電鍍條件係相同於實施例1者 於實施例24中,低介電常數之碳氫化合物爲主之有機絕 緣膜材料係被使用作爲絕緣膜4。類似於實施例1,元件係 被形成於矽基材上。例如SiLK(杜邦化學之商標)之有機絕 緣膜係被旋塗於基材上至300奈米的厚度。此被熱處理並 硬化於400 °C之氮氣氛(N2)30分。SiLK(杜邦化學之商標 ),BCB(杜邦化學之商標),FLARE(阿來信號的商標),及 ν:Εί〇Χ(史馬克之商標)可以被使用作爲碳氫化合物爲主有機 -23- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X29*7公釐) 494531 A7 _____ B7五、發明説明(21 ) 絕緣膜材料,包含芳香族化合物。此製程之後,進行圖案化步 驟,以形成一接線凹槽7及連接孔1〇。如同於實施例1中,銅 接線2係被形成,及線保護膜1係被形成及淸洗。 具有80奈米膜厚之鈷合金係被均勻地沉積於實施例1 4 及24之半導體裝置之銅接線2之表面上。再者,於絕緣膜4 上未看到鈷合金沉積。因此,依據實施例14至23之電鍍製 程,線保護膜1可以只形成於銅接線2之表面上。如同於實 施例24之中,線保護膜1可以只形成於銅接線2之表面上,而 無關於絕緣膜4之類型。表3顯示每一實施例之線保護膜1 之成份的百分比。於實施例1 4及2 1中之回火溫度爲400 °C, 於實施例15至19,22及23之溫度爲450 °C,於實施例20及24 中爲500 °C。 (請先閲讀背面之注意事項再填寫本頁) 項再填六 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -24- 494531
A B 五、發明説明(22 ) 0sff 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 CQ CS CN 1/Ί CS1 r—i Τ—Η — — 一 — 1 1 1 1 1 ΟΝ r- 寸 OO CU 1 1 1 1 Ο 〇Ν 1 1 1 1 1 Η—1 1 1 1 CN 1 1 1 1 1 cn 1 0J 1 1 1 1 1 CN 1 1 1 1 〇 S 1 〇 1 1 1 1 1 1 cn 1 1 U m 1 1 1 1 1 1 Csl 1 1 1 κη ON 〇〇 〇〇 Ό as ON oo g oo ON 三氯化鉻:0.1莫耳/dm3 鉬酸二鈉:0.1莫耳/dm3 高銶酸銨:0.03莫耳/dm3 硝酸鉈:0.01莫耳/dm3 次磷酸:0.1莫耳/dm3 陡§ * « Ο CN Ο Ο 銮盔 5 w W Μ Mg O ^ 〇鍇 鍫翁 S § « « S窆 〇 111 E s ^ ^ 11 鍫鍫 •nil? uu ε g § W ? c〇 O o o rEZ *tA3 <m 鍫鍫 •nil? xEL 鎢酸鈉:0.03莫耳/dm3 --------·裝-- (請先閲讀背面之注意事項再填寫本頁)
、1T τ EP/3S0 Ό19ΗΗερ/ί!Μ90ο1Εέ1Μ ep/jrMrorszlill^ml: ερ/ίπτΜ lo^AJs i H^g/s oo ON CM g Ϊ i Ϊ m ρ 翠 囊 變 班 a ㈣ u -¾ 1¾ 1¾ in 木纸張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) -25- 494531 Α7 Β7 五、發明説明(23) (請先閱讀背面之注意事項再填寫本頁) 依據上述步驟生產之實施例14至2 5之半導體裝置係 被回火於40(TC,450°C,及500°C,於22百分比氫及98百分比 氦之氣氛中30分鐘。 於回火於400°C後,於每一實施例之半導體裝置表面上 並未檢出銅。於示於表3之回火中,作爲接線材料銅的擴散 並未看到。這明顯可看出實施例14至23之線保護膜1具 有較實施例1之線保護膜1爲低之熱電阻,但於400t之加 熱溫度之形成銅接線2之製程中,防止銅擴散。再者,於400 °C之熱溫度前後接線電阻並沒改變。已經確認沒有由於銅 的氧化造成之接線電阻上升。 上述討論明顯看出,當於本實施例中之無電電鍍法被使 用時,銘-鎢-硼合金作爲銅接線2之線保護膜1可以以選擇 方式形成於銅接線2上。另外,銅的氧化及擴散可以被防止, 藉以取得高可靠度之半導體裝置。 (實施例25至35) 經濟部智慧財產局員工消費合作社印製 於實施例25至35中,半導體裝置係被產生,其中線保護 膜1係被形成於表4中之成份百分比中。然後,相同於實施 例6之服務壽命測試係被進行。於每一實施例中之半導體 裝置具有相同於實施例6中之半導體裝置之結構(第4圖)。 於實施例25中,低介電常數之有機絕緣膜係被使用作爲 示於第4圖之半導體裝置之絕緣膜4。所用之有機絕緣膜材 料爲由杜邦化學之SiLK(其介電常數係爲約2.65)。 -26 - 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 494531 A7 B7 五、發明説明(24 ) 服務壽命測試 銅擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 未擴散 £ 1200小時 cn \〇 寸 寸 r- oo cn CN cn m 寸 1M] t^IuT Μ m 600小時 ψ i m C<l CN CN cn 1 < r—H CNl 1 1 _< CNl 鈷合金組成(原子%) PQ < i CN Csl ν/Ί csl < i i t i «i ,1 1 < cu 1 1 I 1 1 o 〇 1 1 1 1 oo 1 1 1 1 1 ON r- OO 1 1 1 1 csl 1 1 1 1 1 m οΰ 1 1 1 1 1 1 CN 1 1 1 ο 1 1 o 1 1 1 1 1 1 m 1 1 m 1 1 1 1 1 1 Csl 1 1 5S On oo oo un ON σ> oo g oo 實施例25 實施例26 實施例27 實施例28 實施例29 實施例30 實施例31 實施例32 實施例33 麵例34 實施例35 (請先閲讀背面之注意事項再填寫本頁) >裝. 訂 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -27 - 494531 A7 B7 五、發明説明(25 ) 表4之結果顯不於接線電阻上並未上升及銅未於半導 體裝置之絕緣膜4中檢出,該半導體裝置中,包含(1)鈷,(2)鉻, 鉬,鎢,銶,鉈及磷之至少之一及(3)硼之鈷合金膜係被形成作 爲銅接線2之線保護膜1。因此,實施例26至35之線保護膜 1係適用以長時間,及銅接線2之氧化及銅由銅接線2擴散入 絕緣膜4可以被避免。而可以獲得高可靠度之半導體裝置 〇 (實施例36至38及參考例4) 於上述實施例中,含⑴鈷,(2)鉻,鉬,鎢,銶,銳,及磷之至少 之一,及(3)硼係之鈷合金係被形成爲銅接線2之線保護膜1 。以下說明描述用於一阻障膜3之鈷合金膜之例子。 於實施例36之半導體裝置中,銘-鎢-硼合金係被使用作 爲一阻障膜3。於實施例36中,元件形成係被執行如於實施 例1中於矽基材上,以形成接線凹槽7及連接孔10(第lc圖) 。一作爲觸媒層之具有厚5奈米之鈷膜係以濺鍍法被形成 於接線凹槽7及連接孔1 〇上。此基材係被浸入於示於表5 中之鈷無電電鍍溶液中,並用以形成於實施例1中之線保護 膜1 。其係受到鈷無電電鍍,以形成鈷無電電鍍膜作爲阻障 膜3 °當線保護膜1被形成於實施例1中時,電鍍條件係相 同。於本實施例中,鈷-鎢-硼合金係藉由無電電鍍形成爲阻 障膜。本發明並未限定於此方法;潑鍍或化學氣相沉積法可 以使用。 然後,銅接線2係如同實施例丨藉由電鍍被形成(第lg圖 • 28- (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適财關家料(CNS )〜胁(21()><297公慶) 494531 A7 ____ B7___ 五、發明説明(26 ) (請先閲讀背面之注意事項再填寫本頁) )。然而,於實施例1中完成之銅種層之形成於本實施例中並 不需要。阻障膜3係用以作爲銅電鍍之電力饋送層,銅係被 直接鍍於阻障膜3上。然後,對阻障膜3進行化學機械硏磨, 如同於實施例1般,以分離接線導線。同時,銅接線2及下層 鈷無電電鍍膜係被確定以密實黏著,以忍受化學機械硏磨。 淸洗後,氮化矽(SiN)係被濺鍍形成至50奈米的厚度,作爲於 銅接線2上之線保護膜1。 於實施例37之半導體裝置中,鈷-鎢-硼合金不只被用於 阻障膜3同時也用於線保護膜1。於實施例36中,銅接線2 被形成,及進行化學機械硏磨。然後,銘-鎢-硼合金之線保護 膜1(60奈米厚)係被如實施例1中被使用。 於實施例38中,阻障膜3係被以用於實施例5中之鈷爲 主無電電鍍溶液加以形成。以下顯示電鍍條件: pH値:8.5(由四甲銨所調整) 溶液溫度:60 °C 電鍍時間:五分鐘胃 於參考例4中,一半導體裝置係被產生,其中阻障膜3係 由鈷-鎢-磷膜所作成。 一具有厚度50奈米(用於實施例36及37)之鈷-鎢-硼合 金膜及40奈米(用於實施例38)係被均勻地形成於依據上述 程序製程之實施例36至38之半導體裝置的接線凹槽7及連 接孔10之側壁及底面上。銅接線2係被觀察於100位置,未 看到孔隙。接線凹槽7及連接孔10係被看到完全被塡充以 銅。鈷合金沉積係未於絕緣膜4看到。因此,由鈷-鎢-硼合 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -29 - 494531 A7 B7 五、發明説明(27 ) 金所作成之阻障膜3之均勻形成可以依據實施例36至38之 電鍍程序形成。 然後,每一實施例之半導體裝置係被回火於5〇〇它30分 鐘,於2百分比氫及98百分比氦氣中。於每一實施例中,均沒 有在表面上檢出銅。未看到接線材料的銅的擴散。因此,銘· 鶴-棚合金係被作爲銅接線2之阻障膜3。 然後,服務壽命測試係進行於實施例3 6至3 8及參考例4 之半導體裝置上,如於實施例6之例子。每一半導體裝置具 有四層,如於第2圖所示。表5顯示每一實施例之阻障層3 之成份的百分比及接線可靠度之估計結果。 接線形狀U)線寬:0.1微米(b)膜寬:1·〇微米,(c)線長 2.5 測試條件(a)溫度Μ75 °C (b)電流密度:3 X 106安每平方 公分 (請先閲讀背面之注意事項再填寫本頁) ¥ % 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -30- i 494531 A7 B7 五、發明説明(28 1 [l I 銅擴散 未擴散 未擴散 未擴散 已擴散 阻障膜厚 〇 1 服務壽命測試 回火前後間之接線電阻比(%) 1200小時 2%或更低 2%或更低 CN 600小時 1%或更低 1%或更低 CNl CN 鈷合金組成(原子%) CO 1 4 \ τ· < 〇 1 塞 1 CU 1 1 1 oo un CN oo 3 ON ON VO s 實施例36 實施例37 實施例38 參考例4 裝 訂 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 31 494531 A7 _____B7_ 五、發明説明(29 ) (請先閲讀背面之注意事項再填寫本頁) 因此,由銅接線2來之銅擴散入絕緣膜4可以爲阻障膜3 所避免。實施例36至38之半導體裝置係特徵於長穩定度及 高可靠性。阻障層3具有較傳統使用,例如氮化鈦,氮化鉅,及 氮化鎢之氮化物金屬,高熔點金屬,例如鉅及鎢或其合金之膜 爲低之電阻。所以,於連接孔1 0之底部及其下之銅接線2間 之連接電阻可以比以前更小,及半導體裝置之接線電阻可以 降低。此阻障膜3可以用作爲用於電鍍銅之電力饋送層,銅 種層並不需要。這完成了銅接線2的形成、 於實施例36中,銘層係被濺鍍形成爲觸媒層。除了濺鍍 外,銘層也可以藉由濕方法形成。當一鈀層係以濕法形成,則 阻障膜3可以被形成於實施例36中。當除了鈷-鎢-硼合金 外,用於線保護膜1中之鈷層被使用爲實施例2至35中之阻 障膜3時,來自銅接線2之銅擴散入絕緣膜4可以被避免。 因此,可以取得高可靠度之半導體裝置。 (實施例39) 如於第5圖所示,實施例39之半導體裝置係被提供以作 爲層間之鈾刻停止層1 7及1 9之絕緣膜。如於第6圖所示,倉虫 刻停止層1 9可以只被提供於接線之頂端。蝕刻控制係藉由 提供蝕刻停止層加以完成。以下描述如何參考第7圖加以 生產。 第7圖顯示於第5或6圖之半導體裝置之接線之形成步 驟,使用雙層嵌入法。元件形成係形成於砂基材1 〇 a上作爲 絕緣膜,及具有厚度600奈米之第一絕緣膜18係形成於基材 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -32 - 494531 A7 B7 五、發明説明(3〇 ) (請先閲讀背面之注意事項再填寫本頁) 上(第10a圖),其中下層接線2b係被形成(第10b圖)。SiLK( 介電常數約2.65)係被旋塗於第一絕緣膜16上,及熱處理及 硬化係被執行於氮(N2)氣氛中,以約400 °C之溫度,30分。 然後,第一蝕刻停止層17係形成於第一絕緣膜16上(第 l〇c圖)。具有50奈米厚之甲基矽氧烷(介電常數約2.8)係藉 由電漿CVD形成於蝕刻停止層17上。此步驟後藉爲第二絕 緣膜18及第二蝕刻停止層19係被以相同方式形成(於第10d 圖)。第二絕緣膜18爲具有400奈米厚之SiLK,及第二蝕刻 停止層19係爲具有50奈米厚之甲基矽氧烷。
Si⑴膜20(50奈米)及氮化矽膜21(50奈米)係被形成於 第二蝕刻停止層1 9上。氮化矽膜2 1係使用光阻罩以電漿蝕 刻作出圖案(第10e圖)。然後,開口 22係以乾蝕刻,使用另一 光阻23加以形成(第10f圖)。 第二絕緣膜18係被氮,氫及混合氣體穿孔22與光阻23 加以蝕刻。隨後,氮化矽膜21係被遮罩,及SiCh膜20,甲基矽 氧院膜1 9,及第一蝕刻停止膜1 7係受到電漿蝕刻,使用 CM^CC^Ar,及〇2混合氣體。然後,接線凹槽7(0.2微米寬)及 連接孔10(直徑0.2微米)係藉由以氮及氫之混合氣體加以蝕 刻(第1 0g圖)。於此時,第一蝕刻停止膜1 9係爲蝕刻停止的 位置。 隨後,阻障膜3之形成係藉由濺鍍(第1 Oh圖),種層5之 形成,及銅接線2之形成係藉由電鍍銅(或銅接線2藉由無電 電鍍銅直接形成於阻障膜3上)及化學機械硏磨,及線保護膜 1之形成係被形成。當化學機械硏磨時,餘刻係停止於第二 本紙乐尺度適用中國國家標準(CNS ) A4規格(210X297公釐) · 33 - 494531 A7 _B7____ 五、發明説明(31 ) 蝕刻停止層1 9上。 阻障膜3及/或線保護膜1係以鈷合金膜加以形成,該合 金膜包含(1)鈷,(2)鉻,鉬,鶴,銶,銳,及磷之至少之一,及(3)硼, 如同於其他實施例般。 無機絕緣膜或有機絕緣膜均可以使用作爲絕緣膜,但有 機絕緣膜係較佳的。無機絕緣膜係較佳由具有例如SiO:,甲 基矽氧烷,倍半氧化物氫氧化物及甲基聚矽氧烷氫氧化物之 矽氧烷鍵之材料所作成,並可以藉由塗覆法及電漿CVD法作 成。無機絕緣膜可以由低介電常數之碳氫爲主有機絕緣材 料作成,其包含例如SlLK(杜邦化學之商標),BCB(杜邦化學之 商標),FLARE(阿來信號的商標),及VELOX(史馬克之商標)之 芳香族化合物。蝕刻停止層可以是由SiCh作成爲無機絕緣 膜,甲基矽氧烷,倍半氧化物氫氧化物,甲基聚矽氧烷,及其他 含矽氧烷鍵,氮化矽及碳化矽之材料。絕緣膜及蝕刻停止層 可以由這些材料之組合作成。爲了改良半導體裝置之接線 系統,較佳使用具有較傳羞使用Si〇2(介電常數約4.3)或氮化 矽(介電常數約7.0至9.0)爲低之介電常數的材料。 £ I :才 i 如於第6圖所示,當接線凹槽7被形成時,於蝕刻停止位 置中之有奈米程度之差。已經確認若蝕刻停止層1 9係只提 供於接線層之頂端時,則於服務壽命測試上沒有問題發生。 於依據上述生產方法所生產之半導體裝置中,銅接線2 之氧化及擴散可以藉由線保護膜1及阻障膜3所防止一長時 間,及於銅接線2之電阻增加可以被降低,藉以確保一高可靠 度。特別是,當鈷合金膜被使用作爲線保護膜1時,相較於高 -34- (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準(CNS ) A4規格(210X29*7公釐) 494531 A7 B7 五、發明説明(32 ) 介電常數之氮化矽被使用時,接線間之電容可以降低約10% 。這降低了信號傳送延遲。接線系統之效率係藉由使用低 介電常數之有機絕緣膜加以改良。 爲了連接連接孔10底部及其下之銅接線2b,絕緣線保護 膜係依據傳統方法所去除(見第1 0d圖)。再者,若線保護膜 保留,則連接故障可能依據傳統方式發生。若導電鈷合金膜 被使用作爲保護膜1,則電連接可以確保,而不必去除線保護 膜1。這使形成連接孔10中,容易蝕刻連線,而改良半導體裝 置可靠度。再者,銘合金膜具有較銅爲高之電阻。若於連接 孔1 0底部上之線保護膜1被至少部份去除,如於第1 1及1 2 圖所示,則有可能降低於下層銅接線2b及銅接線2間之連接 的電阻,而改良接線系統效率。更明確地說,於連接孔10之 底部上之鈷合金被分解並藉由在接線凹槽7及連接孔10形 成後,如於第7g圖所示,浸於重量百分比2之硫酸中加以去除 。於上層上之銅線係被形成,如於其他實施例般,結果,建立 於下層之銅線2b及銅線2間之電連接經阻障膜3,如於第1 1 圖所示。這係成功地降低施加至接線插塞1 1之電阻。 於被提供有銅接線之半導體裝置中,一覆蓋形成於絕緣· 膜中之銅接線之上方之線保護膜及一包圍該銅接線之側及 底部之阻障膜係被覆蓋以鈷合金膜,其包含(1)鈷,(2)鉻,鉬,鶴 ,銶,銳,及磷之至少之一,及(3)硼。然後,作爲接線的銅的氧 化及擴散可以被防止,藉以取得銅接線及元件的高可靠度。 再者,一線保護膜可以被形成,而不使用鈀,結果,由於鈀之增 加線阻的問題可以避免。 -35- (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 494531 A7 ___ B7 五、發明説明(33 ) 若鈷合金膜係被使用作爲線保護膜,則線保護膜可以以 選擇方式,只形成在銅接線上。同時,若阻障膜係被導電姑合 金膜所形成,則銅可以直接電鍍在阻障膜上,而不必電力饋送 層,藉以解決形成孔隙的問題並免除形成一種層之情形。 36 (請先閲讀背面之注意事項再填寫本頁} 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐)

Claims (1)

  1. 494531 A8 B8 C8 D8 六、申請專利範圍 1.一種半導體裝置,包含: (1) 多層銅線形成於一絕緣膜中, (請先閲讀背面之注意事項再填寫本X ) (2) —線保護膜覆蓋該銅線的頂部,及 (3) —阻障膜,包圍該銅接線的側及底部; 該半導體裝置特徵在於該線保護膜及阻障膜的至少之 一係由鈷合金膜及硼所形成,該鈷合金膜包含鉻,鉬,鎢,錬,銳 及磷之至少之一。 2·如申請專利範圍第丨項所述之半導體裝置,其中: 多數層之銅線係形成於絕緣膜中, 接線保護膜及阻障膜係被覆蓋以鈷合金膜,該膜包含(1) 鈷,(2)鉻,鉬,鎢,銶,銳及磷之至少之一,及⑶硼,及 該在上層上之銅線係經由該阻障層電氣連接至在下層 上之銅線。 3. 如申請專利範圍第1或2項所述之半導體裝置,其中: 該絕緣膜具有3或更少之介電常數。 4. 如申請專利範圍第1或2項所述之半導體裝置,其中 該鈷合金膜具有100奈米或更低之厚度,並包含 經濟部智慧財產局員工消費合作社印製 50至95原子百分比鈷, 1至40原子百分比之鉻,鉬,鎢,銶,銳及磷之至少之一,及 0.1至10原子百分比之硼。 5. 如申請專利範圍第1或2項所述之半導體裝置,其中: 多數層之銅線係形成於絕緣膜中, 接線保護膜及阻障膜係被覆蓋以鈷合金膜,該膜包含(1) 鈷,(2)絡,鉬,鎢,銶,蛇及碟之至少之一,及(3)硼,及 本纸張尺度逋用中國國家梂率(CNS ) A4規格(210X297公釐) -37 - 494531 A8 B8 C8 _____ D8 六、申請專利範圍 該在上層上之銅線係經由該鈷合金電氣連接至在下層 上之銅線。 (請先閱讀背面之注意事項再填寫本頁) 6.如申請專利範圍第1或2項所述之半導體裝置,其中 該作爲蝕刻停止層之絕緣膜係進一步形成在線保護膜所形 成之區域以外之絕緣膜的表面上。 7·如申請專利範圍第1或2項所述之半導體裝置,其中 該多數層之銅線係形成於絕緣膜中,一接線保護膜及阻障膜 係被覆蓋以鈷合金膜,該膜包含(1)鈷,(2)鉻,鉬,鎢,銶,銳及磷 之至少之一,及(3)硼,及該在上層上之銅線之至少一部份係 經由該阻障層電氣連接至在下層上之銅線。 8.如申請專利範圍第1項所述之半導體裝置,其中該鈷 合金並未包含鈀。 9·一種半導體裝置的生產方法,其中該半導體裝置包含: (1) 多層銅線形成於一絕緣膜中, (2) —線保護膜覆蓋該銅線的頂部,及 (3) —阻障膜,包圍該銅接線的側及底部; 經濟部智慧財產局員工消費合作社印製 其中至少線保護膜及阻障膜的至少之一係實質上藉由 無電電鍍由鈷合金膜及硼所形成,該鈷合金膜包含鉻,鉬,鎢, 銶,銳及磷之至少之一。 10·—種半導體裝置生產方法,其中該半導體裝置包含: (1) 多層銅線形成於一絕緣膜中, (2) —線保護膜覆蓋該銅線的頂部,及 (3) —阻障膜,包圍該銅接線的側及底部; 該半導體裝置生產方法更特徵在於 本紙張尺度逋用中國國家梂準(CNS ) A4規格(210X297公瘦)----- 494531 B8 C8 D8 六、申請專利範圍 #具有形成絕緣膜的步驟,該絕緣膜作爲在絕緣膜表面 上形成有銅接線之蝕刻停止層,及 該線保護膜及/或阻障膜係由無電電鍍法加以形成,該銘 合金膜包含(1)鈷,(2)鉻,鉬,鶴,鍊,銳及磷之至少之一,及(3)硼 〇 11·如申請專利範圍第9或10項所述之半導體裝置生產 方法,其中該銅接線係由無電電鍍作成。 12·如申請專利範圍第9或10項所述之半導體裝置生產 方法,其中該鈷合金膜具有100奈米或更低之厚度,並包含 50至95原子百分比鈷, 1至40原子百分比之鉻,組,鎢,銶,鉈及磷之至少之一,及 0.1至10原子百分比之硼。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度逋用中國國家揲準(CNS ) A4«l格(210X297公釐) -39 ·
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