TW468247B - Damascene wiring structure and semiconductor device with damascene wirings - Google Patents

Damascene wiring structure and semiconductor device with damascene wirings Download PDF

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Publication number
TW468247B
TW468247B TW089126464A TW89126464A TW468247B TW 468247 B TW468247 B TW 468247B TW 089126464 A TW089126464 A TW 089126464A TW 89126464 A TW89126464 A TW 89126464A TW 468247 B TW468247 B TW 468247B
Authority
TW
Taiwan
Prior art keywords
winding
hole
layer
metal
inlaid
Prior art date
Application number
TW089126464A
Other languages
English (en)
Chinese (zh)
Inventor
Satoshi Otsuka
Akira Yamanoue
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TW468247B publication Critical patent/TW468247B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW089126464A 2000-04-14 2000-12-12 Damascene wiring structure and semiconductor device with damascene wirings TW468247B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000113286A JP3819670B2 (ja) 2000-04-14 2000-04-14 ダマシン配線を有する半導体装置

Publications (1)

Publication Number Publication Date
TW468247B true TW468247B (en) 2001-12-11

Family

ID=18625279

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089126464A TW468247B (en) 2000-04-14 2000-12-12 Damascene wiring structure and semiconductor device with damascene wirings

Country Status (5)

Country Link
US (1) US6373136B2 (https=)
EP (1) EP1146558B1 (https=)
JP (1) JP3819670B2 (https=)
KR (1) KR100669929B1 (https=)
TW (1) TW468247B (https=)

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JP2002222858A (ja) * 2001-01-25 2002-08-09 Mitsubishi Electric Corp 半導体装置およびその製造方法
US7224063B2 (en) * 2001-06-01 2007-05-29 International Business Machines Corporation Dual-damascene metallization interconnection
JP4587604B2 (ja) 2001-06-13 2010-11-24 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4948715B2 (ja) * 2001-06-29 2012-06-06 富士通セミコンダクター株式会社 半導体ウエハ装置およびその製造方法
JP4193206B2 (ja) * 2001-07-25 2008-12-10 セイコーエプソン株式会社 半導体薄膜の製造方法、半導体装置の製造方法、半導体装置、集積回路、電気光学装置及び電子機器
JP4929437B2 (ja) * 2001-08-03 2012-05-09 富士通セミコンダクター株式会社 集積回路の配線レイアウト方法
JP2003257970A (ja) 2002-02-27 2003-09-12 Nec Electronics Corp 半導体装置及びその配線構造
JP2003258085A (ja) 2002-02-27 2003-09-12 Fujitsu Ltd 配線構造及びその形成方法
JP2004031439A (ja) 2002-06-21 2004-01-29 Renesas Technology Corp 半導体集積回路装置およびその製造方法
NO317845B1 (no) * 2002-11-29 2004-12-20 Thin Film Electronics Asa Mellomlagsforbindelser for lagdelte elektroniske innretninger
AU2003266560A1 (en) 2002-12-09 2004-06-30 Yoshihiro Hayashi Copper alloy for wiring, semiconductor device, method for forming wiring and method for manufacturing semiconductor device
US20040173803A1 (en) * 2003-03-05 2004-09-09 Advanced Micro Devices, Inc. Interconnect structure having improved stress migration reliability
JP4068497B2 (ja) * 2003-04-24 2008-03-26 株式会社東芝 半導体装置およびその製造方法
JP4230334B2 (ja) 2003-10-31 2009-02-25 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
US9318378B2 (en) * 2004-08-21 2016-04-19 Globalfoundries Singapore Pte. Ltd. Slot designs in wide metal lines
JP2006170923A (ja) * 2004-11-16 2006-06-29 Matsushita Electric Ind Co Ltd 半導体装置評価装置、半導体装置の評価方法および半導体評価デバイスのシミュレータ
JP4731456B2 (ja) 2006-12-19 2011-07-27 富士通セミコンダクター株式会社 半導体装置
US7586132B2 (en) * 2007-06-06 2009-09-08 Micrel, Inc. Power FET with low on-resistance using merged metal layers
JP2011023487A (ja) * 2009-07-14 2011-02-03 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
KR101035258B1 (ko) * 2010-07-20 2011-05-18 주식회사도담엠에스 멀티 보드
CN102593069A (zh) * 2011-01-13 2012-07-18 奇景光电股份有限公司 接合垫结构以及集成电路芯片
JP5904070B2 (ja) * 2012-09-13 2016-04-13 富士通セミコンダクター株式会社 半導体装置の製造方法
JP6255728B2 (ja) * 2013-06-17 2018-01-10 富士通セミコンダクター株式会社 半導体装置、半導体装置の製造方法及び設計プログラム
JP6565509B2 (ja) * 2015-09-08 2019-08-28 セイコーエプソン株式会社 半導体装置及びそれを用いた電子機器
KR102606765B1 (ko) * 2018-02-07 2023-11-27 삼성전자주식회사 비아 플러그를 갖는 반도체 소자 및 그 형성 방법
JP7097139B2 (ja) * 2018-07-26 2022-07-07 京セラ株式会社 配線基板
US11600519B2 (en) * 2019-09-16 2023-03-07 International Business Machines Corporation Skip-via proximity interconnect

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0724305B2 (ja) * 1987-04-15 1995-03-15 ロ−ム株式会社 半導体装置
JPH02192146A (ja) * 1989-01-20 1990-07-27 Toshiba Corp 半導体装置
JPH05152299A (ja) 1991-04-15 1993-06-18 Hitachi Ltd 配線構造体
JP2811126B2 (ja) * 1991-05-02 1998-10-15 三菱電機株式会社 半導体集積回路装置の配線接続構造およびその製造方法
US5461260A (en) 1994-08-01 1995-10-24 Motorola Inc. Semiconductor device interconnect layout structure for reducing premature electromigration failure due to high localized current density
US5602423A (en) * 1994-11-01 1997-02-11 Texas Instruments Incorporated Damascene conductors with embedded pillars
US5635418A (en) * 1995-03-23 1997-06-03 Micron Technology, Inc. Method of making a resistor
US5834845A (en) * 1995-09-21 1998-11-10 Advanced Micro Devices, Inc. Interconnect scheme for integrated circuits
JPH09213696A (ja) 1996-02-02 1997-08-15 Hitachi Ltd 半導体装置
KR100215847B1 (ko) * 1996-05-16 1999-08-16 구본준 반도체 장치의 금속 배선 및 그의 형성 방법
US5920790A (en) * 1997-08-29 1999-07-06 Motorola, Inc. Method of forming a semiconductor device having dual inlaid structure
US6093632A (en) * 1998-12-07 2000-07-25 Industrial Technology Research Institute Modified dual damascene process
JP2000277519A (ja) * 1999-03-23 2000-10-06 Toshiba Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP1146558B1 (en) 2016-06-01
US6373136B2 (en) 2002-04-16
JP3819670B2 (ja) 2006-09-13
KR100669929B1 (ko) 2007-01-17
KR20010096529A (ko) 2001-11-07
JP2001298084A (ja) 2001-10-26
EP1146558A3 (en) 2003-11-05
EP1146558A2 (en) 2001-10-17
US20010030365A1 (en) 2001-10-18

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