TW501233B - Dual damascene process utilizing a low-k dual dielectric - Google Patents

Dual damascene process utilizing a low-k dual dielectric Download PDF

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TW501233B
TW501233B TW90115158A TW90115158A TW501233B TW 501233 B TW501233 B TW 501233B TW 90115158 A TW90115158 A TW 90115158A TW 90115158 A TW90115158 A TW 90115158A TW 501233 B TW501233 B TW 501233B
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mask
layer
insulating layer
dielectric
etched
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TW90115158A
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Chinese (zh)
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Michael Stetter
Erdem Kaltalioglu
Andy Cowley
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Infineon Technologies Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of fabricating an integrated circuit with a dual dielectric structure and utilizes a dual damascene process to fabricate metal interconnection layers. The dual dielectric structure consists of a first insulating layer of conventional dielectric material, and a second insulating layer of a second dielectric material with a low dielectric constant (low-k dielectric material). The first dielectric, material is used in regions of the integrated circuit where the superior mechanical properties of conventional dielectric materials will result in maintaining the reliability and mechanical properties of the integrated circuit. The second dielectric material is used in regions of the integrated circuit where the low dielectric constant will result in improved speed of the integrated circuit and reduced electrical coupling between conductors in the integrated circuit. The fabrication of the dual dielectric structure is integrated with a dual damascene metallization process.

Description

501233 A7 B7 五、發明説明（1 ) 發明範4 本發明係關於以多級的導電互連所製造之積體電路，其 所使用之介電（或絕緣）材料經製造而提供低介電常數値； 更特定地説，本發明係關於使用雙重金屬鑲嵌製程以製造 多級互連，如此所製之結構。 發明背景 自從積體電路發明伊始，積體電路的性能及密度已提升 了多個數量級。此提升緣於諸多因素，包括：積體電路製 造設備有所創新及改良；積體電路結構中引進了新而更爲 複雜的材料。由於改良，而能製造愈來愈細的特徵，積體 電路的密度已有所提升，而電路性能（速度）的限制因素也 隨之改變。尤其，隨著金屬導體寬度及厚度以及導體間的 橫向間隔減小，每單位導體長度的電阻率已有所提高。類 似地，隨著絕緣（介電）層的厚度減少，各導體間每單位面 積下的電容已有所提高。結果，積體電路速度性能的限制 因素漸趨爲金屬導體之形成材料的電阻率，以及導體周圍 絕緣材料的介電常數。 第一個因素，金屬導體之形成材料的電阻率，已因導體 材料由原本全面使用的鋁改變爲銅，而獲處理。 第二個因素，導體周圍絕緣材料的介電常數，已因漸多 使用了比通用之二氧化矽或氮化矽有較低介電常數（或低 k材料或介電質）的絕緣材料，而獲處理。較低介電常數 材料一般有兩個使用途徑，目前猶在評估中，或於市售產 品中有限地使用。其一係使用有機材料以取代無機氧化矽 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 裝 訂501233 A7 B7 V. Description of the invention (1) Inventive scope 4 The present invention relates to an integrated circuit manufactured with multi-level conductive interconnections. The dielectric (or insulating) materials used are manufactured to provide a low dielectric constant.値; More specifically, the present invention relates to a structure made by using a dual damascene process to manufacture a multilevel interconnect. BACKGROUND OF THE INVENTION Since the invention of integrated circuits, the performance and density of integrated circuits have increased by several orders of magnitude. This improvement is due to many factors, including: innovation and improvement of integrated circuit manufacturing equipment; and the introduction of new and more complex materials into the integrated circuit structure. As a result of the improvements and the ability to manufacture increasingly finer features, the density of integrated circuits has increased, and the limiting factors of circuit performance (speed) have also changed. In particular, as the width and thickness of metal conductors and the lateral spacing between conductors have decreased, the resistivity per unit conductor length has increased. Similarly, as the thickness of the insulating (dielectric) layer decreases, the capacitance per unit area between conductors has increased. As a result, the limiting factors of the speed performance of integrated circuits have gradually become the resistivity of the material forming the metal conductor and the dielectric constant of the insulating material surrounding the conductor. The first factor, the resistivity of the material used to form the metal conductor, has been dealt with as the conductor material changed from aluminum, which was originally used in its entirety, to copper. The second factor, the dielectric constant of the insulating material around the conductor, has been gradually used because of the lower dielectric constant (or low-k material or dielectric) of the insulating material than the general silicon dioxide or silicon nitride, And get processed. Lower dielectric constant materials are generally used in two ways and are currently under evaluation or have limited use in commercially available products. One is the use of organic materials to replace inorganic silica. -4- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding.

線 或氮化矽。第二個途徑係使用含空隙或氣泡的無機材料。 此二種使用低k介電質的途徑都有某些固有的弱點或缺 點。其一爲，材料比起所要取代的傳統材料一般來説有較 不合宜的機械性質。已知目前可取得之介質材料比起 所要取代的材料來説，係'才目當柔軟(其有較低的彈性模 數），而有較低的伸展及壓縮強度，有較低的熱傳導性， 且有較高的熱膨脹係數。 ^低的彈性模數以及較低的伸展及壓縮強度導致機械不 穩足性結構，在受溫度交替時會移動且破裂，而受到操作 (如接合線）相關之機械力時會破損。 當積體電路溫度在操作期間或因周圍溫度升高而升高， 則低k ;丨％貝材料之較咼熱膨脹係數致使金屬通孔在伸展 應力下將不同級的導體互連。此則傾向於拉開積體電蟢通 孔中的導體，A引起斷續或失效的互連，導致較低的積體 電路可靠性。在習知結構中，當積體電路溫度升高，則通 孔中的導體處於壓縮應力之下。 此外，供蝕刻通孔開口（穿過介電材料）用之可取方法係 以通用的氧化矽某些特定性質，來對通孔蝕刻製程做必要 的控制。特定地説，it用的氧化梦姓刻製程所產生的副產 品係沉積在通孔被蝕刻部位的側壁上，使該側壁鈍化以保 護其免於額外的蝕刻。蝕刻製程完成時，可用簡單的灰化 (ashmg)製程來移除此等鈍化副產品，其中鈍化材料經氧 化成粉末狀物質，而可於清除操作中移除。 有必要提供一種結構，以及一種製造該結構之方法，容 501233 A7 B7 五、發明説明（3 ) 許積體電路設計者利用低k材料合宜的低介電常數，而同 時減輕此等材料不合宜的機械性質的效應。 發明概述 本發明係指涉一種積體電路結構，及一種使用雙重金屬 鑲嵌敷金屬製程以製造積體電路結構之方法，其在可利用 二氧化矽的優越機械及化學性質所在的結構區域内，容許 使用習知的二氧化矽介電材料；而在可利用低介電常數以 提供高速操作之電路，且低k介電材料的低劣機械性質不 致降低積體電路機械性質或可靠性所在的結構區域内，容 許使用低k介電材料。 特定地説，習知的氧化矽介電質係使用於將不同級的敷 金屬互連之通孔結構附近，像是接合塾區域，而彼處結構 或會遭受高機械應力。低k介電材料則使用於其餘的積體 電路區域，其中低介電常數降低了導體與地之間以及個別 導體之間的電容，結果乃減小了導體間的耦合。 本發明係整合入通常稱爲「雙重金屬鑲嵌」製程的通用 製程序列。雙重金屬鑲嵌製程序列乃是用以界定一導電互 連級之方法，其中導電金屬線之界定，並不藉金屬導體之 圖型接線或蝕刻，而係在一絕緣層中界定渠溝，再將金屬 導體沉積入此等渠溝。金屬導體寬度係由已界定於絕緣材 料中的渠溝所決定。此界定金屬導體圖型之方法優於較傳 統之方法，因爲絕緣材料比積體電路製造中的典型金屬導 體能更容易而精確地蚀刻。在該雙重金屬鑲嵌製程中，係 於圖型化並蚀刻出渠溝（金屬導體接而將沉積於其中）後， -6- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)Wire or silicon nitride. The second approach is to use void- or bubble-containing inorganic materials. Both of these approaches using low-k dielectrics have some inherent weaknesses or deficiencies. One is that materials generally have less desirable mechanical properties than traditional materials to be replaced. It is known that currently available dielectric materials are softer than the materials to be replaced (they have lower elastic modulus), and have lower tensile and compressive strength, and lower thermal conductivity. And has a high thermal expansion coefficient. ^ Low elastic modulus and low tensile and compressive strength result in mechanically unstable structures that move and rupture when subjected to temperature alternations and break when subjected to mechanical forces associated with operations such as bonding wires. When the temperature of the integrated circuit increases during operation or due to an increase in ambient temperature, the k is low; the relatively high thermal expansion coefficient of the% shell material causes the metal vias to interconnect conductors of different levels under tensile stress. This tends to pull away the conductors in the integrated cell vias, and A causes intermittent or failed interconnections, resulting in lower integrated circuit reliability. In the conventional structure, when the temperature of the integrated circuit increases, the conductor in the through hole is under compressive stress. In addition, the preferred method for etching through-hole openings (through dielectric materials) is to use certain specific properties of general-purpose silicon oxide to make the necessary control of the through-hole etching process. In particular, the by-products produced by the oxidized dream process used for it are deposited on the sidewalls of the etched portion of the through hole, and the sidewall is passivated to protect it from additional etching. When the etching process is completed, a simple ashmg process can be used to remove these passivation by-products, in which the passivation material is oxidized to a powdery substance and can be removed in a cleaning operation. It is necessary to provide a structure and a method for manufacturing the structure, including 501233 A7 B7. V. INTRODUCTION TO THE INVENTION (3) The designers of integrated circuits use low dielectric constants suitable for low-k materials, while at the same time alleviating the unsuitable machinery Effect of nature. SUMMARY OF THE INVENTION The present invention relates to an integrated circuit structure and a method for manufacturing an integrated circuit structure using a dual metal damascene metallization process, which is within the structural region where the superior mechanical and chemical properties of silicon dioxide can be used. Allows the use of conventional silicon dioxide dielectric materials; while low-k dielectric materials can be used to provide high-speed circuits, and the poor mechanical properties of low-k dielectric materials do not reduce the mechanical properties or reliability of integrated circuits Within this area, low-k dielectric materials are allowed. In particular, the conventional silicon oxide dielectrics are used in the vicinity of via structures that interconnect metallizations of different levels, such as joint regions, and the structures there may be subject to high mechanical stress. Low-k dielectric materials are used in the rest of the integrated circuit area, where the low dielectric constant reduces the capacitance between the conductor and ground and between individual conductors, resulting in reduced coupling between the conductors. The present invention is integrated into a general-purpose process sequence commonly referred to as a "dual metal damascene" process. The dual metal damascene process sequence is a method for defining a conductive interconnect level. The definition of conductive metal lines does not rely on the pattern wiring or etching of metal conductors. Instead, the trenches are defined in an insulating layer, and then the Metal conductors are deposited into these trenches. The width of the metal conductor is determined by the trenches already defined in the insulating material. This method of defining the pattern of a metal conductor is better than the more traditional method because the insulating material is easier and more accurate to etch than the typical metal conductors used in integrated circuit manufacturing. In this double metal damascene process, after patterning and etching out trenches (metal conductors will be deposited in it), -6- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm (Centimeter)

裝 訂Binding

線 在既已2定的渠溝内部區域中圖型化通孔。再蝕刻出此等 ，孔，牙透至底下的互連層或電路元件。然後以互連金屬 填充通孔及渠溝。 7 '來看，本發明係指涉一種使用雙重金屬鑲嵌製 t，而在半導體主體頂表面上面形成一互連級以製造積體 兒路<方去，其中有一絕緣體在該金屬導體互連級底下而 側向延伸於該導體以外，係一具第一介電常數之第一介電 材料所製；還有一絕緣體位於金屬導體側面，係一具第二 介電常數（異於第-介電常數）之第二介電材料所製。該方 法包含步驟：在一半導體主體（其上欲形成一互連級）上 面’沉積-第一介電材料所製之第一絕緣層，$而在第— 絕緣層上面1成—第二介電材料所製之第二絕緣芦 第二介電材料所製之第二絕緣層上面，沉積一第一罩暮材 料所製之第-罩幕層，以及_第二罩幕材料所製之第二罩 幕層，其中第-及第二罩幕材料係經選取而彼此有蚀 性上I互選性，以致至少有-種㈣第-罩幕材料之姓刻 劑不會姓刻第二罩幕材料，且至少有—種蚀刻第二 料之蝕刻劑不會蝕刻第—罩幕材料；在第二罩幕層中界A 並蝕刻一終將界定金屬導體位置及特徵之開口，以一4 = 蝕刻Μ第一罩幕材料之蝕刻劑蝕刻該第二罩幕材科；在二 -罩幕層中界定並蝕刻一終將界定一通孔 ： 金屬導體或電路元件）位置及尺寸之開口，以一不备、 孩第二罩幕材料之蚀刻劑㈣該第—罩幕材料；用2刻 第二罩幕層做爲蝕刻罩幕，繼續做穿過第二絕緣層2通2Lines pattern through-holes in the internal area of the existing trench. Then, the holes and teeth are etched to the underlying interconnect layer or circuit element. Vias and trenches are then filled with interconnect metal. 7 'Looking at it, the present invention refers to a method of using a double metal damascene to form an interconnect level on the top surface of a semiconductor body to make an integrated circuit, in which an insulator is interconnected on the metal conductor. It is made of a first dielectric material with a first dielectric constant and extends laterally beyond the conductor at the bottom of the stage; there is also an insulator on the side of the metal conductor with a second dielectric constant (different from the first-dielectric Dielectric constant) made of a second dielectric material. The method comprises the steps of: depositing a first insulating layer made of a first dielectric material on a semiconductor body (on which an interconnection level is to be formed), and 10% on a first-insulating layer-a second dielectric On the second insulating layer made of electric material and the second insulating layer made of the second dielectric material, a first mask layer made of the first mask material and a first mask layer made of the second mask material are deposited. The second cover layer, in which the first and second cover materials are selected to be corrosive and mutually selectable, so that at least one of the first and second cover materials will not engrav the second cover. Materials, and at least one etchant that etches the second material will not etch the first mask material; the boundary A in the second mask layer and an opening that will eventually define the location and characteristics of the metal conductor, with a 4 = The etchant that etched the first mask material etched the second mask material section; defined and etched in the two-mask layer one will eventually define a through hole: metal conductor or circuit element) position and size of the opening, with a Unavailable, etchant for the second mask material—the first mask material; use 2 carved second mask Layer serving as an etching mask, continue through the second insulating layer 2 pass 2

的蝕刻製程，以一不會蝕刻第一罩幕材料之蝕刻劑蝕刻該 第二介電材料，並在第一絕緣層頂表面停止蝕刻；用第二 、’、邑緣層做爲罩桊，蚀刻而穿過第一絕緣層以延伸該開口， 止於半導體主體表面，而同時蝕刻了第一罩幕層的曝露部 份；用第一及第二罩幕層做爲罩幕，蝕刻而穿過第二絕緣 層’至第一絕緣層表面’而同時蝕刻了半導體主體表面上 任何保護的罩蓋層之任何曝露部份，並曝露在通孔開口底 邪之金屬導體或電路元件的頂表面；在半導體主體上沉積 一金屬導體層，以致接觸任何底下的金屬導體或電路元件 t頂表面，以填充先前開出的通孔開口且填充第二絕緣層 中先前界足的開口，並過填該在第二罩幕級頂表面之級上 方的開口；以及，平面化半導體主體頂表面，以移除第一 罩幕層頂表面上方之所有金屬導體材料，並移除第二罩幕 層。 由附圖及申請專利範圍項目所做之下述更詳細說明，本 發明將獲更好的理解。 圖式簡單説明 圖1 7F出用本發明方法所製造之一積體電路結構的截面 視圖；以及 圖2-圖7示出整個製造過程中各時刻之積體電路結構， 該等圖式毋須成比例。 圖式未必依實際尺寸。 詳細説明 、圖1不出依據本發明一示範實施例之積體電路結構丨〇的 -8 - 本紙張尺度適用中國國冢標準(CNS) A4規格 B7 五、發明説明（6 簡單截面目。結構1〇包含_半導體主體η，纟具有一頂 表面13。在半導體主體12中及/或上所製造的電晶體及其 他裝置(未示出)將以習知技術而連接一互連結構的元件。 具有頂表面15之絕緣層14在半導體主體12之頂表面。 上形成。一具有頂表面17之導體16及一具有頂表面“之 絕緣層18在絕緣層丨4之頂表面15上形成。雖未示出，但 層1 6可選擇性地通過層i 4而接觸主體丨2的若干部份及/ 或其中的擴散。絕緣層18爲一具有頂表面21之硬罩幕層 2〇所罩蓋。導體16、絕緣層18及硬罩幕20可用習知的金 屬蝕刻製程、一習知的金屬鑲嵌製程、一習知的雙重金屬 鑲嵌製程’或以本發明之新穎製程（討論於下）來形成。導 體16及硬罩幕20爲具有頂表面23之罩蓋層22所覆蓋。一 導體30，包含部份3以及36抑，其部份刊⑽接觸導體16及 邵份36a。一虛線36aaa被廓畫於導體36之部份36a&36aa 之間。導體邵份36a係供用爲積體電路各部位間的互連。 導體部份36a有一頂表面36t、一底表面36b，以及側表面 36c。導體邵份36aa有側表面36s。一絕緣層2 4有一頂表面 25而圍繞導體部份36aa，且位於導體部份36a之底表面 3 6b之下，外延而覆蓋罩蓋層22之頂表面23。一絕緣層 26有頂表面27，且位置鄰近於導體部份36a之側表面 3 6c。一罩蓋層28有頂表面29，且覆蓋絕緣層26之頂表面 27 〇 下文中説明依據本發明之用以製造圖1所示結構}〇之方 法0 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) A7Etching process, the second dielectric material is etched with an etchant that does not etch the first mask material, and the etching is stopped on the top surface of the first insulation layer; Etching through the first insulating layer to extend the opening, stopping at the surface of the semiconductor body, and simultaneously etching the exposed portion of the first mask layer; using the first and second mask layers as the mask, etching and penetration Any exposed portion of any protective cover layer on the surface of the semiconductor body is etched through the second insulation layer 'to the surface of the first insulation layer' and exposed to the top surface of the metal conductor or circuit element of the via hole bottom ; Depositing a metal conductor layer on the semiconductor body so as to contact the top surface of any underlying metal conductor or circuit element t to fill a previously opened via hole opening and a previous boundary foot opening in the second insulating layer and overfill The opening above the level of the top surface of the second cover stage; and, planarizing the top surface of the semiconductor body to remove all the metal conductor material above the top surface of the first cover layer, and removing the second cover layerThe invention will be better understood from the following more detailed description made with the accompanying drawings and patented scope items. The drawings briefly illustrate the cross-sectional view of an integrated circuit structure manufactured by the method of the present invention in FIGS. 17F; and FIG. 2 to FIG. 7 show the integrated circuit structure at various moments in the entire manufacturing process. proportion. The drawing may not be based on actual size. Detailed description, Fig. 1 does not show the integrated circuit structure according to an exemplary embodiment of the present invention. -8-This paper size is applicable to China National Tomb Standard (CNS) A4 specification B7. 5. Description of the invention (6 simple cross section. Structure 10 includes a semiconductor body η, and has a top surface 13. Transistors and other devices (not shown) fabricated in and / or on the semiconductor body 12 will connect elements of an interconnected structure using conventional techniques. An insulating layer 14 having a top surface 15 is formed on the top surface of the semiconductor body 12. A conductor 16 having a top surface 17 and an insulating layer 18 having a top surface are formed on the top surface 15 of the insulating layer 1-4. Although not shown, the layer 16 can selectively contact portions of the main body 2 and / or diffusion through the layer i 4. The insulating layer 18 is a hard cover curtain layer 20 having a top surface 21. The cover 16. The conductor 16, the insulating layer 18, and the hard cover 20 may use a conventional metal etching process, a conventional metal damascene process, a conventional dual metal damascene process, or a novel process of the present invention (discussed below). )。 The conductor 16 and the hard cover 20 are The top surface 23 is covered by a cover layer 22. A conductor 30 includes portions 3 and 36, and a portion thereof contacts the conductor 16 and the portion 36a. A dotted line 36aaa is drawn on the portion 36a of the conductor 36 & Between 36aa. The conductor component 36a is used for interconnection between various parts of the integrated circuit. The conductor portion 36a has a top surface 36t, a bottom surface 36b, and a side surface 36c. The conductor component 36aa has a side surface 36s. The insulation layer 24 has a top surface 25 surrounding the conductor portion 36aa, and is located below the bottom surface 36b of the conductor portion 36a, and extends to cover the top surface 23 of the cover layer 22. An insulation layer 26 has a top surface 27, And is located adjacent to the side surface 36c of the conductor portion 36a. A cover layer 28 has a top surface 29 and covers the top surface 27 of the insulating layer 26. The following description is used to make the structure shown in FIG. 1 according to the present invention} 〇Method 0 -9- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) A7

A7A7

層2 8材料，而 率蝕刻層3 〇材 3 〇材料之蝕刻劑不以任何有意義比率蝕刻 蝕刻層2 8材料之蝕刻劑不以任何有意義比 料。 圖4示出已在硬罩幕層3〇中界定並蝕刻出一開口32之德 的積體電路結構10。_口32繼而將爲金屬導體所填充， 以形成圖1所示之導體36a。用以蝕刻層3〇材料之蝕刻劑 未冒蝕刻任何有意義份量的層28材料；且蝕刻製程止二 =靠近層28之頂表面29。爲在一抗光蝕材料（未示出）界 足一開口，所使用的是習知的微影技術；該抗光蝕材料於 姓刻製程完成後，已接而被移除。. 圖5 π出已界定並蚀刻出一開口 3 4之後的積體電路結構 1 〇，其係用合適的蝕刻劑材料，穿過罩蓋層2 8再向下穿 過低k絕緣層26，而止於習知絕緣層24之頂表面25。開 3 4下的區面應爲將以金屬填充的通孔。爲在一抗光姓 材料（未示出）界定一開口，所使用的是習知的微影技術，· 該抗光蚀材料係用以界定罩蓋層28中蚀刻的開口；且抗 光蚀材料於蚀刻製程完成後，已接而被移除。用以银刻低 k絕緣層2 6之蝕刻劑係經選取而有選擇性，不致蝕刻罩蓋 層2 8也不蝕刻習知絕緣層2 4之材料。 圖6所示之積體電路結構1 〇，係蝕刻製程已完成開口 3 4 深度之延伸，穿過習知的絕緣層2 4而下至罩蓋層2 2之頂 表面2 3。該經延伸的開口 3 4係識別爲3 4 &。蝕刻劑係經 選取而選擇性地蝕刻絕緣層2 4材料，且也蚀刻罩蓋層2 8 材料以延伸開口 3 2向下而至低k絕緣層2 6之頂表面2 7， -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)The layer 2 8 material does not etch the material of the layer 3 30 material. The etchant of the material does not etch at any meaningful ratio. The layer 28 material of the etchant does not etch at any meaningful ratio. Fig. 4 shows the integrated circuit structure 10 which has defined and etched an opening 32 in the hard mask layer 30. The mouth 32 will then be filled with a metal conductor to form the conductor 36a shown in FIG. The etchant used to etch the material of layer 30 does not etch any significant amount of material of layer 28; and the etching process is only close to the top surface 29 of layer 28. To make an opening in a photoresistive material (not shown), a conventional lithography technique is used; the photoresistive material has been removed after the last engraving process is completed. Figure 5 shows the integrated circuit structure 10 after an opening 34 has been defined and etched, which is made of a suitable etchant material, through the cover layer 28 and then through the low-k insulating layer 26, It stops at the top surface 25 of the conventional insulating layer 24. The area under opening 3 4 should be a through hole to be filled with metal. To define an opening in a photoresistive material (not shown), a conventional lithography technique is used. The photoresist is used to define the etched opening in the cover layer 28; and photoresist The material was removed after the etching process was completed. The etchant used to etch the low-k insulating layer 26 with silver is selected and selective, and will not etch the cover layer 28 or the conventional insulating layer 24 material. The integrated circuit structure 10 shown in FIG. 6 is an extension of the depth of the opening 3 4 of the etching process, passes through the conventional insulating layer 2 4 and goes down to the top surface 23 of the cover layer 2 2. The extended opening 3 4 is identified as 3 4 &. The etchant is selected to selectively etch the insulating layer 2 4 material, and also etch the cover layer 2 8 material to extend the opening 3 2 down to the top surface of the low-k insulating layer 2 6 2 7, -11-this Paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

裝 訂Binding

線 501233 A7 _______B7 五、發明説明（^~) 而不蚀刻罩蓋層22或低k絕緣層26之材料，如此乃造成開 口 32a 〇 圖7所π之積體電路結構j 〇，係蝕刻製程已完成開口 32a之L伸，牙過低k絕緣層2 6而下至習知的絕緣層2 4之 頂表面25，以形成開口32aa。另附帶施行蝕刻而移除在開 口 34a底部的罩蓋層22，以造成開口 34“。金屬層16之頂 表面1 7乃曝露於延伸的開口 34aa底部。 圖1所示之積體電路結構丨〇，係圖7結構已接受一習知 的雙重金屬鑲嵌製程（該製程由一標準的金屬線性填充、 一晶種層之沉積，與金屬鍍敷所組成），繼之以一化學機 械研磨（CMP )而平面化積體電路結構丨〇。硬罩幕層3 〇係 以C ΜP製私移除。該結構例示，開口 34犯經金屬填充而 形成導體36aa，且開口32aa經金屬填充而形成導體36&。 如圖1所示，通孔34aa既填充有金屬冗⑽且位於金屬導 體16與金屬導體36a之間，其附近的積體電路1〇範圍内之 介電質部份係由習知的介電材枓24所組合。金屬導體 36aa兩側之任一側36c的積體電路i 〇部份，則由低^介電 材料2 6所組合。 容易理解，所説明的特定實施例僅係例示本發明之基本 原理’而在不脱離本發明精神及新穎原理之下亦可設想其 他各種實施例。此外容易理解，特定的製程步驟及該製程 步驟之序列僅係例示本發明之基本原理，而在不脱離本發 明精神及新穎原理之下亦可設想其他各種製程步驟，也可 修正該製程步驟之序列。舉例來説，所説明之施行於一個 -12-Line 501233 A7 _______B7 V. Description of the Invention (^ ~) The material of the cover layer 22 or the low-k insulating layer 26 is not etched, which results in the opening 32a 〇 The integrated circuit structure π in FIG. 7 is an etching process The L extension of the opening 32a is completed, and the teeth pass through the low-k insulating layer 26 and down to the top surface 25 of the conventional insulating layer 24 to form the opening 32aa. In addition, the cover layer 22 at the bottom of the opening 34a is removed by etching to create the opening 34 ". The top surface 17 of the metal layer 16 is exposed at the bottom of the extended opening 34aa. The integrated circuit structure shown in Figure 1 丨〇, the structure of Figure 7 has accepted a conventional dual metal damascene process (the process consists of a standard metal linear filling, a seed layer deposition, and metal plating), followed by a chemical mechanical polishing ( CMP) and a planar integrated circuit structure. The hard cover layer 30 is removed by CMP. This structure illustrates that the opening 34 is filled with metal to form a conductor 36aa, and the opening 32aa is formed with metal filling. Conductor 36 & As shown in FIG. 1, the through hole 34aa is filled with metal redundancy and is located between the metal conductor 16 and the metal conductor 36a. The dielectric portion within the range of the integrated circuit 10 near it is determined by Xi. The known dielectric material 24 is combined. The integrated circuit i 0 part of either side 36c on either side of the metal conductor 36aa is combined by the low-dielectric material 26. It is easy to understand that the specific embodiment described Merely to illustrate the basic principles of the present invention 'and Various other embodiments can be conceived without departing from the spirit and novel principle of the present invention. In addition, it is easy to understand that the specific process steps and the sequence of the process steps are merely illustrative of the basic principles of the present invention, without departing from the spirit of the present invention and Under the novel principle, various other process steps can be conceived, and the sequence of the process steps can be modified. For example, the illustrated implementation is performed in a -12-

501233 A7 B7 五、發明説明（10 ) 製程步驟中的各種蚀刻製程，也可分開而施行於一序列的 各別製程步驟中；類似地，所説明之施行於一序列的各別 製程步驟中的各種蚀刻製程，也可施行於單一個整合製程 步驟中。此外，在各種罩幕及絕緣層中所指定的材料，也 可替之以各種材料及材料種類。還有，雖然本結構及製造 該結構之方法係在製造矽積體電路的文脈中説明，本方法 也可應用來製造各種裝置及電路中使用矽以外之半導體材 料的類似結構；也可應用來製造被動互連結構，像是印刷 接線板、軟性（flexible )互連電路及積體電路封裝結構。 -13- 本纸張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）501233 A7 B7 V. Description of the Invention (10) The various etching processes in the process steps can also be performed separately in a series of individual process steps; similarly, the illustrated operations are performed in a series of individual process steps. Various etching processes can also be performed in a single integrated process step. In addition, the materials specified in various screens and insulation layers can be replaced with various materials and material types. Also, although this structure and the method for manufacturing the structure are described in the context of manufacturing silicon integrated circuits, this method can also be applied to manufacture similar structures using semiconductor materials other than silicon in various devices and circuits; it can also be applied to Fabricate passive interconnect structures, such as printed wiring boards, flexible interconnect circuits, and integrated circuit packaging structures. -13- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

申請專利範圍 一種利用雙重金屬鑲嵌製程而在半導體主體頂表面上面 形成一互連級以製造積體電路之方法，其中有一絕緣體 在居至屬導體互連級底下而側向延伸於該導體以外，係 —具第一介電常數之第一介電材料所製；還有一絕緣體 垃於金屬導體側面，係一具第二介電常數（異於第一介 兒常數第二介電材料所製，該方法包含步驟： 斤在一半導體主體（其上欲形成一互連級）上面，沉積一 第介電材料所製之第一絕緣層，進而在第一絕緣層上 形成一第二介電材料所製之第二絕緣層； 在第二介電材料所製之第二絕緣層上沉積一第一罩幕 材料所製之第一罩幕層，以及一第二罩幕材料所製之第 二罩幕層，其中第一及第二罩幕材料係經選取而彼此有 蝕刻特性上之互選性，以致至少有一種蝕刻第一罩幕材 ，之蝕刻劑不會蝕刻第二罩幕材料，且至少有一種蝕刻 第一罩幕材料之蝕刻劑不會银刻第一罩幕材料； 在第二罩幕層中界定並蝕刻一終將界定金屬導體位置 及特徵之開口，以一不會蝕刻該第一罩幕材料之蝕刻劑 蝕刻該第二罩慕材料； 在第一罩幕層中界定並蝕刻一終將界定一適孔開口 (至底下的金屬導體或電路元件）位置及尺寸之開口，〆 一不會蝕刻該第二罩幕材料之蝕刻劑蝕刻該第:罩2 料； w 用第一及第二罩幕層做爲蝕刻罩幕，繼續做穿過第二 絕緣層之通孔的蝕刻製程，以一不會蝕刻第—罩幕材^ -14- 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐 (請先閱讀背面之注意事項再填寫本頁) -丨農 ----^---------. 經濟部智慧財產局員工消費合作社印製 501233 A8 B8 C8 D8The scope of the patent application is a method for forming an integrated circuit on the top surface of a semiconductor body by using a dual metal damascene process to manufacture an integrated circuit, in which an insulator extends laterally beyond the conductor below the interconnecting level of the conductor, System—made of a first dielectric material with a first dielectric constant; there is an insulator on the side of the metal conductor, and a system with a second dielectric constant (different from the first dielectric material made of the second dielectric material, The method includes the steps of: depositing a first insulating layer made of a first dielectric material on a semiconductor body (on which an interconnection level is to be formed), and forming a second dielectric material on the first insulating layer; A second insulating layer made of the second layer; a first mask layer made of a first mask material and a second mask made of a second mask material are deposited on the second insulating layer made of the second dielectric material The mask layer, wherein the first and second mask materials are selected to have mutual selectivity in etching characteristics, so that at least one of the first mask materials is etched, and the etchant will not etch the second mask material, and At least An etchant that etches the first mask material will not silver etch the first mask material; define and etch an opening in the second mask layer that will eventually define the location and characteristics of the metal conductor, so that the first mask material will not be etched The second mask material is etched by the etchant of the mask material; the first mask layer is defined and etched to define an opening that will eventually define the location and size of a suitable hole opening (to the underlying metal conductor or circuit component), one An etchant that does not etch the second mask material will etch the first: mask 2; w Use the first and second mask layers as the etching mask, and continue the etching process through the through hole of the second insulation layer The first cover film is not etched ^ -14- Private paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm (please read the precautions on the back before filling this page)-丨 农- --- ^ ---------. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 501233 A8 B8 C8 D8 申請專利範圍 經濟部智慧財產局員工消費合作社印製 之蝕刻劑蝕刻該第二介電材拉 ^ 停止蝕刻； #抖’並在第一絕緣層頂表面 用第二絕緣層做爲罩幕，餘刻而穿過第'絕緣 伸該開口，止於半導體主體丟； 把表面，而同時蝕刻了第一置 幕層的曝露部份； 币 卓 用第一及第二罩幕層做爲餘刻罩幕，蚀刻而穿過 絕緣層，至第：絕緣層表面，而同時蚀刻了半導體主體 表面上任何保遵的罩蓋層之任何 、 ㈢仕仃曝路邵份，並曝露在通 孔開口底部之金屬導體或電路元件的頂表面； I 在半導體主體上沉積-金屬導體層，以致接觸任 下的金屬導體或電路元件之頂表面，以填充先的 通孔，口且填充第二絕緣層中先前界定的開口，並過： 該在第二罩幕級頂表面之級上方的開口；以及 β 、 平坦化半導體主體頂表面，以移除 罢首a 、 吵除罘一罩幕層頂表面 上万之所有金屬導體材料，並移除第二罩幕層。 2. 如申清專利範圍第1項之方法.，其中歹筮人 ^ Τ《罘一介電材料鱼 弟二絕緣層之對應特性相比，有相當之高硬度、高_ 模數、咼熱傳導性及低熱膨脹係數。 3. 如申請專利範圍第丨項之方法，其中該第二介電材料 較該第一介電材料爲低之介電常數。 '有 4. 如申請專利範圍第i項之方法，其中該第一 二氧化矽。 “材料爲 '如申請專利範圍第1項之方法，其中該第二介電材料係 從已知爲有機介電質或聚合物之材料種類所選取。 系 -15- ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 訂.丨 A8 B8 C8 D8Scope of patent application: The etchant printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs etched the second dielectric material and stopped etching; # tremble; and used the second insulating layer as a cover on the top surface of the first insulating layer. The opening is extended through the first insulation to stop the semiconductor body; the surface is etched at the same time as the exposed part of the first curtain layer; Yuanzhuo uses the first and second cover layers as the remaining cover. Curtain, etched through the insulating layer to the first: the surface of the insulating layer, and at the same time etched any compliant cover layer on the surface of the semiconductor body, and exposed the road surface to the bottom of the opening of the through hole. The top surface of a metal conductor or circuit element; I deposits a metal conductor layer on the semiconductor body so as to contact the top surface of any metal conductor or circuit element to fill the first through hole, fill the opening and fill the second insulation layer previously. Define the opening and pass: the opening above the level of the top surface of the second curtain stage; and β, planarize the top surface of the semiconductor body to remove the striker a, eliminate the top surface of the curtain layer Place Metallic conductive material, and removing the second mask layer. 2. As described in the method of item 1 of the patent scope, in which the person ^ "T", a dielectric material, and the corresponding characteristics of the insulation layer, has a relatively high hardness, high modulus, and thermal conductivity. And low thermal expansion coefficient. 3. The method according to item 丨 of the patent application, wherein the second dielectric material has a lower dielectric constant than the first dielectric material. 'Yes 4. The method according to item i of the patent application scope, wherein the first silicon dioxide. "The material is the method according to item 1 of the scope of patent application, wherein the second dielectric material is selected from the types of materials known as organic dielectrics or polymers. -15- ^ Paper size applies Chinese national standards (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Binding. A8 B8 C8 D8 申請專利範圍 6·Π =範圍第1項之方法，其中該第二介電材料係 乂之下列'1¾'物户斤扭；^ U 土 、 、.冗…功 類選取其一：低“匕學氣相 1乳切，㈣、碳、氟與氫之混合群組。 7. U專利範圍第1項之方法，其中該第-罩幕材料爲 &二申請專利範圍m之方法，其中該第二罩幕材料爲 9·:申請專利範圍第1項之方法，其中該第二罩幕材料爲 利範圍第1項之方法，其中該第-絕緣層之餘 罘罩幕層曝露邵份之蝕刻係分開但接續操作。 η·如申請專利範圍第”頁之方法，其中該第二绝緣層 刻與半導體主體表面上任何保護的罩蓋層曝露部份之 刻係分開但接續操作。 ^--------訂---------^9 (請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 -16 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Patent application scope 6 · Π = The method of the first item in the scope, in which the second dielectric material is the following '1¾' property owner; ^ U soil,,...... Learn the gas phase 1 milk cut, a mixed group of tritium, carbon, fluorine and hydrogen. 7. The method of the U patent scope item 1, wherein the-mask material is the & 2 method of patent scope m application, where the The second cover material is 9: The method of applying for the first item of the patent scope, wherein the second cover material is the method of the first scope, wherein the remaining insulation layer of the-insulating layer is exposed to Etching is a separate but continuous operation. Η · As in the method on page "of the patent application, wherein the second insulating layer is etched separately from the exposed portion of any protective cover layer on the surface of the semiconductor body, but is continued. ^ -------- Order --------- ^ 9 (Please read the notes on the back before filling out this page} Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -16 This paper size applies China National Standard (CNS) A4 specification (210 X 297 mm)
TW90115158A 2000-06-21 2001-06-21 Dual damascene process utilizing a low-k dual dielectric TW501233B (en)

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