TW464927B - Metal bump with an insulating sidewall and method of fabricating thereof - Google Patents

Metal bump with an insulating sidewall and method of fabricating thereof Download PDF

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Publication number
TW464927B
TW464927B TW089117464A TW89117464A TW464927B TW 464927 B TW464927 B TW 464927B TW 089117464 A TW089117464 A TW 089117464A TW 89117464 A TW89117464 A TW 89117464A TW 464927 B TW464927 B TW 464927B
Authority
TW
Taiwan
Prior art keywords
metal
patent application
insulating layer
scope
item
Prior art date
Application number
TW089117464A
Other languages
English (en)
Inventor
Ming-Yi Lai
Yung-Fen Shie
Shang-Gung Tsai
Jing-Huen Luo
Original Assignee
Unipac Optoelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unipac Optoelectronics Corp filed Critical Unipac Optoelectronics Corp
Priority to TW089117464A priority Critical patent/TW464927B/zh
Priority to US09/764,207 priority patent/US6958539B2/en
Priority to JP2001246861A priority patent/JP3671192B2/ja
Application granted granted Critical
Publication of TW464927B publication Critical patent/TW464927B/zh
Priority to US10/656,248 priority patent/US7041589B2/en

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  • Wire Bonding (AREA)

Description

464927 發明說明 本發明係有關一種金屬凸塊（bump)及其製作方法，特 別有關於一種具有絕緣侧壁之金屬凸塊及其製作方法。— 將晶片裝配在玻璃上（chip on glass, COG)是一種電’ 連接積體電路（integrated circuit, 1C)的先進技術，具 有量輕、型小、成本低、耗電少等優點，已經被採用於各 種顯示面板的製作上’例如：需要1 -2個晶片之小尺寸（小 於4吋）顯示面板的電話機顯示面板與複印機、需要3〜12個 晶片之中尺寸（4-11吋）顯示面板的攝影機與航空系統、大 尺寸（大於Π吋）顯示面板的筆記型電腦等等。 對於液晶顯示器（liquid crystal display, LCD)組 件而§ ，驅動IC與玻璃基板之間的電連結性會影響其品 質與可靠度。目前最廣泛用來將晶片黏貼至LCD玻璃基板 上的材料為異向性導電薄膜（anisotropic conductive film，ACF) ’是由厚度為15-35 //in的絕緣黏性薄膜以及直 徑為3-15 的導電粒子所構成’其中絕緣黏性薄膜可為 熱塑型材料、熱固型材料、或是熱塑型材料與熱固型材料 之混合’導電粒子可為碳纖維、金屬（鎳、銲錫）或是塗佈 Ni/Au金屬之塑膠球’而導電粒子的分布均勻性會影響到 ACF的電連結品質與可靠度。一般而言，ACF分成兩種類 型’一種是黏性薄臈中的導電粒子表面上覆蓋有絕緣層， 導電粒子的直徑約為5 μπι，當導電粒子受到擠塵變形時 會使絕緣層破裂，則裸露之導電粒子可以用來作為晶片上 的金屬凸塊與玻璃基板上的連接墊之間的電連接橋樑。4曰 由於在製程上無法確保絕緣層是否會破裂，也就是不能;
第5頁 4 6 4 9 2。. ' 五、發明說明（2) 保導電粒子的電連接效果，因此現在大多改用另一種雙層 結構的ACF。雙層結構的ACF之其中一層薄膜包含有直徑3S 从m的導電粒子’另一層薄膜中則沒有導電粒子，係利用 沒有覆蓋絕緣層之導電粒子直接產生電連接效杲。不過， 當兩相鄰金屬凸塊之間的導電粒子過於擁擠時，導電粒子 拫容易橫向連結兩金屬凸塊，進而發生短路的現象。 請參考第Ϊ圖，第:IA圖係顯示習知LCD組件之玻璃基板 的佈局上視圖，第1B圖係顯示第1A圖所示之預定位置之佈 局上視圖’第1C圖係顯示晶片之佈局上視圖。習知LCJ)組 件之玻璃基板10包含有一第—區域12用來放置薄膜電晶體 (thin film transistor，TFT)之陣列，一第二區域 14 包 含複數個預定位置1 5用來放置資料I c晶片，以及一第三區 域16包含有複數個預定位置15用來放置掃描IC晶片。玻璃 基板10上之每一個預定位置15上包含有複數個第一連接墊 18 ’而資料1C晶片或是掃描1C晶片20表面上設有複數個第 二連接墊2 2，係與每一個第一連接墊1 8相對應。 請參考第2A圖至第2D圖，第2A圖至第2D圖係顯示習知 將晶片20與玻璃基板1〇連結之方法的示意圖，其中第2A圖 係顯示沿第1B圖之切線2-2所示之剖面示意圖，第2B圖係 顯示沿第1C圖之切線2, -2’所示之剖面示意圖。習知將晶 片20與玻璃基板1〇連結之方法，如第2a圖所示，係先於玻 璃基板10表面上黏貼一ACF 24，使其覆蓋住第一連接墊18 表面。另外，如第2B圖所示，於晶片20表面之第二連接墊 22上製作一金屬凸塊26。然後，如第2C圖所示，將晶片20
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表面朝下放置於玻璃基板10之預定位置ί5上， 金屬凸塊26對準每一個預定位置15上的連捿塾丨'8使其每一 ACF 24的粘著性以及向下施加的壓力’可以將晶° ^ 地粘著在玻璃基板10上，後續可再進行熱處理製程將^/ 24固化。如此一來，被壓夾在金屬凸塊26頂部與第一連接 墊18表面的導電粒子25可以用來作為電連接橋樑。但是， 如第2D圖所示，存在於相鄰之金屬凸塊26之間的導電粒子 25很多’而且製程上無法控制導電粒子25的分佈情形因 此兩金屬凸塊26之間的導電粒子25很有可能呈現橫向連結 而發生知:路的現象。尤其當金屬凸塊26的尺寸設計錯誤或 疋對準第一連接墊18產生誤差時’會使相離之金屬凸塊26 之間的距離過窄，則導電粒子2 5更容易呈現橫向連結兩金 屬凸塊26 ’會大幅降低lcd產品的品質與可靠度。 有鏗於此，本發明之目的係在於提出一種具有絕緣側 壁之金屬凸塊及其製作方法，以防止ACF中的導電粒子橫 向連結相鄰之金屬凸塊。 本發明提出一種用來連接一非導體基板與一晶片之複 數個金屬凸塊’包含有至少一第一金屬凸塊以及至少一第 二金屬凸塊，其中第一金屬凸塊之侧壁之第一預定區域係 與第二金屬凸塊之側壁之第二預定區域相鄰。第一金屬凸 塊包含有一第一絕緣層，係至少覆蓋於第一金屬凸塊之侧 壁之第—預定區域上，可以用來隔絕第一金屬凸塊與第二 金屬凸塊相鄰之區域。 圖式簡單說明
第7頁 4 6 4 9 2 /
五、發明說明（4) 為讓本發明之上述目的 懂’下文特舉一較佳實施例 明如下： 第1A圖係顯示習知LCD I 圖。 、特徵、和優點能更明顯易 ’並配合所附圖式，作詳細說 件之玻璃基板的佈局上視 屬凸塊的製作方法的 圖係顯示第U圖所示之預定位置之佈局上視圖。 第ic圖係顯示晶片之佈局上視圖。 A 2D圖係顯不習知將晶片與玻璃基板連結之方法 第3A圖係顯示本發明之金屬凸塊的上視圖。 第3B圖係顯不沿第3A圖之切線3-3所示之金屬凸塊連 接玻瑞基板與晶片的剖面示意圖。 屬凸塊連 第4A〜4F圖係顯示第3圖所示之金 示意圖。 第5A〜5F圖係顯示第3圖所示之金屬凸塊的另一 方法的示意圖。 裡裂b 第6A圖係顯示本發明另一實施例之金屬凸塊 圖。. ^
第6B圖係顯示沿 接玻璃基板與晶片的 [符號說明] 第6A圖之切線6-6所示之金屬凸塊連 剖面示意圖。
30~玻璃基板； 34〜晶片； 38〜ACF ; 32〜第一連接墊； 36〜第二連接墊； 39〜導電粒子；
第8頁 五、發明說明（5) 4 2〜金屬凸塊； ;422、第二金屬凸塊 4 4〜絕緣層； 442〜第二絕緣層； 46~金屬層； 5〇~第二凹槽； ;522〜第二預定區域 40〜保護層； 421〜第一金屬凸塊 43〜凹槽； 441〜第一絕緣層； 45〜光阻層； 48〜第一凹槽； 521〜第一預定區域 較佳實施例說明： 第一實施例 請參考第3圖’第3A圖係顯示本發明之金屬凸堍42的 上視圖’第3B圖係顯示沿第3A圖之切線3-3所示之金屬凸 塊42連接玻璃基板3〇與晶片34的剖面示意圖。本發明金屬 凸塊42係用來連接一玻璃基板3〇之第一連接塾μ與一晶片 34之第二連接墊36。金屬凸塊42係形成於晶片34之第二連 接墊36上，且金屬凸塊42之周圍侧壁上覆蓋有一絕緣層 44，可以用來隔離相鄰之金屬凸塊42。當晶片34表面朝下 放置於玻璃基板30之預定位置上，並使金屬凸塊42對準預 疋位置上的第一連接塾32時’藉由黏貼於玻璃基板3〇表面 上之一ACF 38的粘著性，可以將晶片34緊緊地粘著在玻璃 基板30上。如此一來，被壓夾在金屬凸塊42頂部與第一連 接墊32表面的導電粒子39可以用來作為電連接橋樑。由於 本發明金屬凸塊42之周圍侧壁上設置有絕緣層44，因此即 使存在於相鄰之金屬凸塊42之間的導電粒子39呈現橫向連 結’相鄰之金屬凸塊42之間會被絕緣層44隔絕而不會發生
^^492 五、發明說明（6) 短，的現象。對於晶片34上密集排列第二連接墊36的區域 而言，本發明金屬凸塊42可以有效避免導電粒子39所產生-的短路現象，進而大幅提昇LCD組件的品質與可靠度。 請參考第4圖，第4圖係顯示第3圖所示之金屬凸塊42 的製作方法。如第4A圖所示，晶片34表面上包含有裸露之 第二連接墊36以及一保護層40，第二連接墊36係為一種鋁 金屬墊，而保護層40係由氮化物所構成，用來保護晶片34 上製作完成之積體電路。本發明方法是先於晶片34表面上 形成一光阻層45，然後利用微影製程與蝕刻製 屬凸塊42的圖案，將位於第二連接塾36表面上 去除，以形成一凹槽43，>第化圖所示n，如第4 戶:示，於晶片34表面上沉積一金屬層46，以使金屬層“填 滿凹槽43，後續可以將光阻層45表面上的金屬㈣ 並 切平金屬層46的表面。跟著，如第4D圖所示，將 阻層45完全去除，而殘留之金屬層46係用來作為 42。然後，如第4E圖所示，於晶片34表面上沉積由：： 石夕或氮化發所構成之絕緣層44 ’使絕緣層44覆蓋住: 子触刻（reactive i〇n etch,川）==利用反應性離 =製程，去除位於金屬凸塊42頂部與晶片 u j 層只保留位於金屬凸塊42之侧壁上 ;= 作完成第3圖所示之金屬凸塊42。 ^ ^ 言奮參考第5®，第5圖係、顯示第3圖所示之金屬 的另一種製作方法。如第5A圖所示，本發明另一種方法是
第10頁 464927 -—---------___...'— 五、發明說明（7) 先於晶片34表面上形成光阻層45，然後利用微影製程與第 一餘刻製程定義出金屬凸塊42的圖案’將位於第二連接塾 36表面上之光阻層45以及第二連接墊36周圍之保護層4〇表-面上之光阻層45去除，以形成一第一凹槽48 ’如第5B圖所 示。跟著’如第5C圖所示，於晶片34表面上沉積絕緣層 44，以使絕緣層44填滿第一凹槽48。接著，如第5D圖所 示’進行一第二蝕刻製程’去除位於第二金屬墊36表面以 及第一凹槽48底部上的絕緣層44，只保留位於第一凹槽48 之側壁上的絕緣層4 4，以形成一第二凹槽5 0。後續如第5 E 圖所示，於晶片34表面上沉積金屬層46並使金屬層46填滿 第二凹槽50，再將光阻層45表面上的金屬層46去除並切平 整個金屬層46的表面。最後’如第5F圖所示，去除殘留之 光阻層45，使殘留之金屬層46之侧壁覆蓋著絕緣層44，便 製作完成第3圖所示，之金屬凸塊42 β 第二實施例 只要絕緣層44能夠達到隔離相鄰之金屬凸塊42的目 的’絕緣層44可以只覆蓋住金屬凸塊42之側壁上的特定區 域’而不需完全覆蓋住金屬凸塊42之周圍侧壁。請參考第 6圖，第6Α圖係顯示本發明另一實施例之金屬凸塊42的上 視圖，第6Β圖係顯示沿第6Α圖之切線6-6所示之金屬凸塊 42連接玻璃基板30與晶片34的剖面示意圖。本發明另一實 施例中’晶片34表面上之複數個金屬凸塊42包含有至少一 第一金屬凸塊421以及至少一第二金屬凸塊422，其中第一 金屬凸塊421之侧壁之第一預定區域521係與第二金屬凸塊
第頁 464927 五、發明說明（8) 塊422相鄰之第一預定區域521與第 422之侧壁之第二預定區域522相鄰.為了使第一預定區域 521與第二預定區域522之間產生隔離，可以於第一金屬凸 塊421之側壁之第一預定區域521上覆蓋一第一絕緣層 一 441，而第二金屬凸塊422之側壁之第二預定區域522上則 不需製作絕緣層。對於第二金屬凸塊4 2 2之側壁之其他區 域而言，則可以依據隔絕效果的需求，選擇性地形成一°第 二絕緣層422。如此一來，第一金屬凸塊421與第二金屬凸 域522之間 只要藉由第:絕緣層441就可以達到隔離的效果，即使存 2第塊421與第二金屬凸塊422之間的導電粒子 39呈現検向，也不會發生短路的現象，對於提昇產品 的品質與可靠度有报大的幫助。 阳發:月ί以較佳實施例揭露如上，然其並非罔以 L :習此項技藝者，在不脫離本發明之精 二 園：备可作更動與潤飾’因此本發明之保護範圍 當視後附之中請專利範圍所界定者為準，月之仔^圍
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Claims (1)

  1. 464927_ 六、申請專利範圍 1. 一種用來連接一非導體基板與一晶片之複數個金屬 凸塊，該複數個金屬凸塊包含有： 至少一第一金屬凸塊，其包含有一第一絕緣層係至少 覆蓋於該第一金屬凸塊之側壁之第一預定區域上；以及 至少一第二金屬凸塊，該第二金屬凸塊之側壁之第二 預定區域係與該第一金屬凸塊之侧壁之第一預定區域相 鄰。 2. 如申請專利範圍第1項所述的複數個金屬凸塊，其 中該第一絕緣層係完全覆蓋於該第一金屬凸塊之周圍側壁 上。 3. 如申請專利範圍第1項所述的複數個金屬凸塊，其 中該第二金屬凸塊包含有一第二絕緣層，係至少覆蓋於該 第二金屬凸塊之侧壁之第二預定區域上。 4. 如申請專利範圍第3項所述的複數個金屬凸塊，其 中該第二絕緣層係完全覆蓋於該第二金屬凸塊之周圍側壁 上。 5. 如申請專利範圍第1項所述的複數個金屬凸塊，其 中該非導體基板表面上設有複數個第一金屬墊，且該晶片 表面上設有複數個與該複數個第一金屬墊相對應之第二金 屬墊。 6. 如申請專利範圍第5項所述的複數個金屬凸塊，其 中每一金屬凸塊係設置於該第一金屬墊以及相對應之該第 二金屬墊之間。 7. 如申請專利範圍第6項所述的複數個金屬凸塊，其
    0664-5628TWF,ptd 第13頁 4 6 4 9 2 I 六、申請專利範圍 中該非導體基板與該晶片之間設有一異方性導電薄膜 (anisotropic conductive film’ ACF)，係填滿相鄰之金 屬凸塊之間的空隙。 8. 如申請專利範園第1項所述的複數個金屬& | 中該第一絕緣層係由二氧化矽或氮化矽所構成。 9. 如申請專利範圍第1項所述的複數個金屬凸地 中該非導體基板係為一玻璃基板。 ’ 其 其 10· —種金屬凸塊的製作方法，包括有： (a)提供一晶片’該晶片表面上設有複數個金屬塾 (b)分別於該複數個金屬墊上製作複數個金屬凸 其1ί7該複數個金屬凸塊包含有：至少一第一金屬’ 塊，其包含有一第一絕緣層係至少覆蓋於該第一凸 之側壁之第一預定區域上；以及至少一第二金屬凸塊凸塊 該第二金屬凸塊之侧壁之第二預定區域係與該第一思且 塊之側壁之第一預定區域相鄰。 兔屬凸 11. 如申請專利範圍第10項所述的方法，其中 絕緣層係完全覆蓋於該第一金屬凸塊之周圍侧壁上' 一 12. 如申請專利範圍第u項所述的方法，其 金屬凸塊的製作方法包括有： 孩第一 (a) 於該晶片表面上形成一光阻層； (b) 進行一蝕刻製程’將位於該金屬墊表面 層去除，以形成一凹槽； 之先® (c)於該凹槽内填滿一金屬層；
    _
    )664-5628TWF.ptd
    第14頁 464927 六、申請專利範圍 (d) 將殘留之光阻層完全去除； (e) 於該晶片表面上沉積該第一絕緣層，使該第一絕 緣層覆蓋住該金屬層之表面；以及 (f) 進行一非等向性乾蝕刻製程，去除位於該金屬層 頂部與該晶片表面之絕緣層，並保留位於該金屬層之側壁 之絕緣層。 1 3.如申請專利範圍第丨2項所述的方法，其中該金屬 層係由金屬（Au)所構成。 14.如申請專利範園第12項所述的方法，其中該第一 絕緣層係由二氧化矽或氮化矽所構成。 1 5,如申請專利範圍第1 2項所述的方法，其中該非等 向性乾钱刻製程係為一反應性離子姓刻（r e a c t i v e i ο η etch，RIE)方法。 1 6.如申請專利範圍第11項所述的方法，其中該第一 金屬凸塊的製作方法包括有： (a) 於該晶片表面上形成一光阻層； (b) 進行一第一蝕刻製裎’將位於該金屬墊表面以及 I周圍之光阻層去除，以形成一第一凹槽； (c) 於該晶片表面上沉積該第一絕緣層，以使該第— 絕緣層形成於於該第一凹槽之侧壁與底部； (d) 進行一第二蝕刻製程’以去除位於該金屬墊表面 以及該第一凹槽之底部上的第一絕緣層，並保留位於該第 一凹槽之側壁之第一絕緣層’以形成一第二凹槽； (e) 於該第二凹槽内填滿一金屬層；以及
    464927 六、申請專利範圍 ------—一 (f)去除殘留之光阻層。 17. 如申請專利範圍第16項所述的方法，其中該金屬 層係由金屬（Au)所構成。 18. 如申請專利範圍第16項所述的方法，其中該第一 絕緣層係由二氧化矽或氮化矽所構成。 19. 如申請專利範圍第10項所述的方法，其中該金屬 凸塊係用來將該晶片連接至一非導電基板上。 20. 如申請專利範圍第19項所述的方法’其中該非導 體基板與該晶片之間設有一異方性導電薄膜（anisotropic ,+ . f . , β相鄰之金屬凸塊之間的 conductive film, ACF)，係填满 @ 空隙。
    664-5628HF.ptd 第16頁
TW089117464A 2000-08-29 2000-08-29 Metal bump with an insulating sidewall and method of fabricating thereof TW464927B (en)

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JP2001246861A JP3671192B2 (ja) 2000-08-29 2001-08-16 絶縁層付角柱状バンプ及びそのバンプを用いたチップオングラス製品並びにｉｃチップ表面への絶縁層付角柱状バンプの製造方法
US10/656,248 US7041589B2 (en) 2000-08-29 2003-09-08 Metal bump with an insulating sidewall and method of fabricating thereof

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8692390B2 (en) 2011-02-18 2014-04-08 Chipbond Technology Corporation Pyramid bump structure
TWI449140B (zh) * 2010-06-02 2014-08-11 Taiwan Semiconductor Mfg 積體電路裝置及封裝組件

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
KR100455387B1 (ko) * 2002-05-17 2004-11-06 삼성전자주식회사 반도체 칩의 범프의 제조방법과 이를 이용한 ｃｏｇ 패키지
WO2004051732A1 (en) * 2002-11-29 2004-06-17 Infineon Technologies Ag Attachment of flip-chips to substrates
JP2007531247A (ja) * 2003-07-16 2007-11-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 側壁用絶縁体を有する金属バンプ及びこのような金属バンプを有するチップを製造する方法
US8604613B2 (en) * 2003-11-14 2013-12-10 Industrial Technology Research Institute Electronic assembly having a multilayer adhesive structure
US7960830B2 (en) * 2003-11-14 2011-06-14 Industrial Technology Research Institute Electronic assembly having a multilayer adhesive structure
US20060157869A1 (en) * 2003-11-19 2006-07-20 Industrial Technology Research Institute Semiconductor substrate with conductive bumps having a stress relief buffer layer formed of an electrically insulating organic material
US20050104225A1 (en) * 2003-11-19 2005-05-19 Yuan-Chang Huang Conductive bumps with insulating sidewalls and method for fabricating
KR100632472B1 (ko) * 2004-04-14 2006-10-09 삼성전자주식회사 측벽이 비도전성인 미세 피치 범프 구조를 가지는미세전자소자칩, 이의 패키지, 이를 포함하는액정디스플레이장치 및 이의 제조방법
JP5085012B2 (ja) * 2004-04-14 2012-11-28 三星電子株式会社 バンプ構造を含む半導体素子及びその製造方法
US7253089B2 (en) * 2004-06-14 2007-08-07 Micron Technology, Inc. Microfeature devices and methods for manufacturing microfeature devices
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US7465654B2 (en) 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
TWI262347B (en) * 2004-08-02 2006-09-21 Hannstar Display Corp Electrical conducting structure and liquid crystal display device comprising the same
US7452803B2 (en) 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7547969B2 (en) 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
TWI393226B (zh) 2004-11-04 2013-04-11 Taiwan Semiconductor Mfg 基於奈米管之填充物
CN1901161B (zh) * 2005-07-22 2010-10-27 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
US7397121B2 (en) 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
US20070238222A1 (en) * 2006-03-28 2007-10-11 Harries Richard J Apparatuses and methods to enhance passivation and ILD reliability
JP4768491B2 (ja) * 2006-03-30 2011-09-07 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
TWI346826B (en) * 2006-10-26 2011-08-11 Taiwan Tft Lcd Ass Bonding structure and method of fabricating the same
TWI334183B (en) * 2007-02-15 2010-12-01 Chipmos Technologies Inc Conductive structure for a semiconductor integrated circuit and method for forming the same
US9093322B2 (en) * 2007-07-13 2015-07-28 Intel Mobile Communications GmbH Semiconductor device
US9524945B2 (en) 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
US8377816B2 (en) * 2009-07-30 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming electrical connections
US8841766B2 (en) 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
TW201121006A (en) * 2009-12-03 2011-06-16 Hannstar Display Corp Connection structure for chip-on-glass driver IC and connection method therefor
US8610270B2 (en) 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8441124B2 (en) 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
TWI419284B (zh) * 2010-05-26 2013-12-11 Chipmos Technologies Inc 晶片之凸塊結構及凸塊結構之製造方法
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
JP5663607B2 (ja) * 2011-02-10 2015-02-04 パナソニックＩｐマネジメント株式会社 半導体装置
JP5664392B2 (ja) * 2011-03-23 2015-02-04 ソニー株式会社 半導体装置、半導体装置の製造方法、及び配線基板の製造方法
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
US10049893B2 (en) * 2016-05-11 2018-08-14 Advanced Semiconductor Engineering, Inc. Semiconductor device with a conductive post
JP7046351B2 (ja) 2018-01-31 2022-04-04 三国電子有限会社 接続構造体の作製方法
JP7185252B2 (ja) 2018-01-31 2022-12-07 三国電子有限会社 接続構造体の作製方法
JP7160302B2 (ja) * 2018-01-31 2022-10-25 三国電子有限会社 接続構造体および接続構造体の作製方法
US20210159198A1 (en) * 2019-11-24 2021-05-27 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
CN110930879B (zh) * 2019-11-25 2020-11-10 武汉华星光电半导体显示技术有限公司 一种显示装置

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6444049A (en) * 1987-08-12 1989-02-16 Fujitsu Ltd Electrode for flip chip bonding
JPH02220863A (ja) 1989-02-23 1990-09-04 Minolta Camera Co Ltd プリンタ装置
JP2928822B2 (ja) * 1990-02-02 1999-08-03 カシオ計算機株式会社 半導体装置およびその接続方法
JPH04196434A (ja) * 1990-11-28 1992-07-16 Seiko Epson Corp 半導体装置の製造方法
JPH068599A (ja) 1992-06-29 1994-01-18 Brother Ind Ltd 印字装置
JPH06232211A (ja) * 1993-02-03 1994-08-19 Casio Comput Co Ltd Ｉｃチップの接続構造およびその接続方法
JPH0872486A (ja) 1994-08-31 1996-03-19 Akihiro Aoki 縮尺スケール
US5578527A (en) * 1995-06-23 1996-11-26 Industrial Technology Research Institute Connection construction and method of manufacturing the same
KR0157905B1 (ko) * 1995-10-19 1998-12-01 문정환 반도체 장치
KR100225398B1 (ko) 1995-12-01 1999-10-15 구자홍 반도체 범프의 본딩구조 및 방법
US6232563B1 (en) * 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
KR0171099B1 (ko) 1995-11-25 1999-02-01 구자홍 반도체 기판 범프 및 그 제조방법
KR100232678B1 (ko) * 1996-12-18 1999-12-01 구본준 돌기가 형성된 범프 및 그 제조방법
JP3328157B2 (ja) * 1997-03-06 2002-09-24 シャープ株式会社 液晶表示装置
US5783465A (en) * 1997-04-03 1998-07-21 Lucent Technologies Inc. Compliant bump technology
US6683384B1 (en) * 1997-10-08 2004-01-27 Agere Systems Inc Air isolated crossovers
US6157079A (en) * 1997-11-10 2000-12-05 Citizen Watch Co., Ltd Semiconductor device with a bump including a bump electrode film covering a projecting photoresist
TW366548B (en) * 1998-04-18 1999-08-11 United Microelectronics Corp Trench bump block and the application of the same
KR100347762B1 (ko) * 1999-12-15 2002-08-09 엘지전자주식회사 베어칩 반도체 집적회로 및 회로기판 패턴의 직접 접합 방법
JP2001244289A (ja) * 1999-12-24 2001-09-07 Seiko Epson Corp 半導体装置およびその製造方法
JP4663165B2 (ja) * 2001-06-27 2011-03-30 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2004134653A (ja) * 2002-10-11 2004-04-30 Sharp Corp 基板接続構造およびその基板接続構造を有する電子部品の製造方法
US7088004B2 (en) * 2002-11-27 2006-08-08 International Rectifier Corporation Flip-chip device having conductive connectors
JP3964319B2 (ja) * 2002-12-20 2007-08-22 セイコーインスツル株式会社 半導体装置
JP4115832B2 (ja) * 2002-12-27 2008-07-09 東芝松下ディスプレイテクノロジー株式会社 半導体素子及び液晶表示パネル
US7242097B2 (en) * 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US20050082670A1 (en) * 2003-09-11 2005-04-21 Nordson Corporation Method for preapplying a viscous material to strengthen solder connections in microelectronic packaging and microelectronic packages formed thereby

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI449140B (zh) * 2010-06-02 2014-08-11 Taiwan Semiconductor Mfg 積體電路裝置及封裝組件
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US9685372B2 (en) 2010-06-02 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming Cu pillar bump with non-metal sidewall spacer and metal top cap
US8692390B2 (en) 2011-02-18 2014-04-08 Chipbond Technology Corporation Pyramid bump structure

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