TW398045B - Method for mounting semiconductor element to circuit board, and semiconductor device - Google Patents

Method for mounting semiconductor element to circuit board, and semiconductor device Download PDF

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Publication number
TW398045B
TW398045B TW087116280A TW87116280A TW398045B TW 398045 B TW398045 B TW 398045B TW 087116280 A TW087116280 A TW 087116280A TW 87116280 A TW87116280 A TW 87116280A TW 398045 B TW398045 B TW 398045B
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TW
Taiwan
Prior art keywords
semiconductor element
circuit board
item
mounting
insulating adhesive
Prior art date
Application number
TW087116280A
Other languages
English (en)
Inventor
Yoshihiko Yagi
Hiroyuki Otani
Original Assignee
Matsushita Electric Ind Co Ltd
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Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Application granted granted Critical
Publication of TW398045B publication Critical patent/TW398045B/zh

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    • H—ELECTRICITY
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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Landscapes

  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Description

A7 B7 五、發明説明（ 本發明所屬之技術領域 ，發明係有關於一種將半導體元件上之突起電極與電 路基板上的電極，以電氣性連接所使用之電路基板的半導 體凡件安裝方法，以及於該安裝方法上可使半導體元件安 裝在電路基板之半導體裝置。 習知技藝 習知之於半導體元件上的球形結合法塊形形成方法， 以及半導體元件之接合方法，在美國專利第4 661，丨92號 公報上有所公佈，現對該方法作說明。 如在第2 5圖所示，對於從毛細管丨5之前端所出來之Au 金屬絲16的前端16a，從放電電極π外加數千伏特之高電 壓。藉此，於放電電極17與金屬絲前端i6a於放電電流流 通之間，金屬絲16從其前端16a變成為高溫而熔融，乃生 成如在第26圖所示之金球18。如在第27圖所示，由毛細管 15將金球18固定在半導體元件3之電極3&上，以形成塊形 底部19 ’接著’如在第28圖所示，將毛細管往上方拉上去 。其次’在塊形底部19之上部將毛細管15作翻面，並將金 屬絲16固定於塊形底部19而予切斷，乃形成為塊形2〇。 其次，如上述將有形成塊形20之半導體元件3，如在 第29圖所示，將其押壓形成為平坦面之工作台14上，而形 成將塊形20之前端部平坦化之塊形2〇。接著，如在第3〇圖 所示，將具有平坦化之塊形20之半導體元件3接觸於有塗 佈導電性接著劑6之工作台5上，而將導電性接著劑6移轉 於上述平坦化之塊形20上。然後，如在第31圖所示，將在 本紙張尺度ϋ用中阀國家樣冷（rNS ) Λ4規格（210X297公梦_ > (对先閲讀背面之注意事項再填寫本頁) -IX.. *vs -4- A7 B7 五、發明説明（2 ) 塊形20上有轉移導電性接著劑6之半導體元件3，與電路基 板1上丨之電極2作位置對正並予固定而進行電氣性連接。 如上述，於習知，半導體元件3舆電路基板丨之接合， 僅以轉移至半導體元件3之塊形2 〇的導電性接著劑6進行。 因此，半導體元件3與電路基板丨之接合，僅具有半導體元 件3之塊形20的前端面積之接合強度，並且，為降低體積 電阻值，其接著劑量較少，因此，導電性接著劑6之強度 弱小到1〜2.0 g/Ι接合部。是故，因電路基板丨之變形或導 電性接著劑6於硬化時之應力，而使接合部產生裂紋，乃 有連接電阻值上昇或開啟不良之課題存在。 本發明之目的 本發明係欲解決上述之課題所進行，並以提供於半導 體元件與電路基板之接合上，可提高連接可靠度、亦能提 高連接強度，並且，使連接電阻值降低並穩定的電路基板 之半導體元件安裝方法，以及以該安裝方法使半導體元件 安裝在電路基板之半導體裝置為目的β 解決課題之本發明裝置 經漓部中央標枣局只J消资合作社印3;! Λ-----Γ 訂 - * ,13, (讀先閲讀背面之注意事項再填寫本頁} 於本發明第1態稱之半導體元件的安裝方法，係最少 亦在電路基板與半導體元件相互之相對面的任一方，設置 作硬化之同時亦作收縮之絕緣性接著劑，並且，使上述電 路基板上之電極與上述半導體元件上的突起電極相對應而 作位置對正，再將上述電路基板及上述半導體元件上相互 之上述相對面，以上述絕緣性接著劑作連結，而後，將上 述絕緣性接著劑硬化，而使上述電路基板上之上述電極及 本紙張尺度1¾則，肖_:料.（) Λ4規格(21GX 297公楚) " ^濟部中"標牟局兵-x消贽合作社印繁 A7 B7 五、發明説明（3 ) 上述半導體元件上之上述突起電極，以上述絕緣性接著劑 之上述收縮作電氣性連接，並且，將上述半導體元件與上 述電路基板固定為連結狀態，為其特徵。 本發明之第2態樣之半導體裝置，係以上述第丨態樣之 安裝方法使半導體元件安裝在電路基板，為其特徵。 上述第1態樣之電路基板的半導體元件安裝方法，以 及依據上述第2態樣之半導體裝置，即，使用絕緣性接著 劑連接半導體元件及電路基板，因之，與習知之僅以半導 體元件之突起電極與電路基板之電極的連接之場合相比， 即，其半導體元件與電路基板可連接為較強固。因此，於 半導體元件之突起電極與電路基板之電極上的連接電阻值 以及其偏差就變成較小，並且，其連接強度亦強化、穩定 、可靠度高之接合就能獲得。 本發明之實施態樣 現參照圖面說明本發明第1實施例，於電路基板上的 半導體元件之安裝方法，以及以該安裝方法使半導體元件 安裝在電路基板之半導體裝置。又，在各圖面上對於同一 構成部份就附加同一符號（號碼）。 在第1圖’於本第1實施例’乃表示以半導體元件之安 裝方法而使半導體元件3安裝在電路基板ι〇丨之半導體裝置 100。為形成如是之半導體裝置1〇〇用的上述安裝方法，就 說明如下。 與參照第25圊至第29圖說明習知之半導體元件的場合 同樣’在半導體元件103之電極103a有形成為突起電極 本紙張尺料财g[家料(CNS >八4祕（210X297公釐）'' (諳先聞讀背面之注意事項再填寫本Η} 士. 衣- ·1 丁 、-° * 6 - A7 ______________B7
五 '發明説明（4 ) " — "" " 一 --*---I 之堤形，而該突起電極1〇4乃被押壓在工作台之平坦面， · 使f前端部份平坦化之同時，從半導體元件1〇3之表面起 的高度亦予均-化。又，突起電請之材料，以Au、Ni L. j 、A卜Cu、或著以銲錫（錫與錯之合金）形成較為適宜。突 | - | 起電極1〇4之形成方法，以電錄或如上述習知的使用金屬 、丨 絲之球形結合法均可，並形成方法並不限定。 | | 如是之半導體元件103，於第2圖及第2G圖上之步驟（ I j ;圖面内乃以S」表不）ι所示，係將突起電極1〇4之前端 讀（滅
部份接觸於在工作台之平坦面上所塗佈之導電性接著冑 # I 1〇6’即可在上述前述部份上轉移導電性接著劑⑽{ 接著劑106 ’以具有銀、金等之導電性的填料就可，巾 { 於材質上並不限定。 f '
另方面，在本實施例，於電路基板101上，乃如在第3 I
圖及第20圖上之步驟2所示，於形成上述半導體裝置⑽之 J 時，在與半導體元件103所相對之相對面101a内，在與上 |
述突起電極104相連接之電極1〇2不接觸之位置上，塗佈熱 I
硬化性之絕緣性接著劑1〇7。該絕緣性接著劑1〇7之具體性 J 經湞部中次榡隼而Θ-Τ·-消阶合作社印¾
材質為’環氧系樹脂H系樹脂、聚_胺系樹脂等，卩 I 熱可使其收縮、硬化者即可，而不予限定。又，如將後㉛ 'j ，為與突起電極104之導電性接著劑1〇6於同一工程上進行 -j 硬化及收縮，因此，上述絕緣性接著劑1〇7，以6〇〜2〇〇它 | 之範圍，而上述環氧系樹脂之場合ul2(rc之溫度為最適 j 且，並以15分〜2小時之範圍的時間，而最好以丨小時之時 j 間進行加熱。將半導體元件103載置在電路基板101上之時 j 本紙张尺颇則，酬賴4V ( -7- A7 B7 經濟部中央樣率局負工消费合作社印¾ 五、發明説明（5 ) ’電路基板101上之絕緣性接著劑1 〇7，由於有必要與附著 在半導趙元件103之相對面l〇3b之上述相對面1〇ia及上述 相對il03b相連結，因此，若絕緣性接著劑ι〇7為液體狀 之時’就如第3圖所示，電路基板ιοί上乃有必要形成為凸 狀。因此，絕緣性接著劑107為液體狀之時，其具有4〜3〇〇 Pas之範圍，而最好為30 pas之值的黏性為宜。 在本實施例上之說明’乃將塗佈或附著絕緣性接著劑 Ϊ07之半導體元件103，採用1晶片狀者為例，惟，並不限 定於此’以切斷為1晶片之前的晶圓亦可以。 由環氧樹脂所成之絕緣性接著劑107之物性值之一實 用例表示如下。絕緣性接著劑107之硬化條件為，以i2〇〇c 加熱30分鐘。熱膨脹係數為29Xl(T6t：、揚氏模量（縱彈性 模量）為10_5 GPa、玻璃轉移點溫度為ii3°c、接著強度為 88.28 N、硬化應力為 882.6 X 106Pa。 又’上述絕緣性接著劑1 〇 7於硬化、收縮之時，對半 導體元件103所附加之硬化應力，有損傷半導體元件1 之 可能性。上述硬化應力，將隨半導體元件1〇3之厚度、尺 寸、配線材質及線寬、以及電路基板1〇1之厚度、尺寸、 材質，而變化’但’以1〇 mm四方、0_4 mm厚度之石夕半導 體元件，與0.8 mm之玻璃環氧樹脂之電路基板的場合， 上述硬化應力為392.3 X 106〜1176.8X106 pa時，就不會損 傷半導體元件。即，使用於硬化、收縮之時，對半導體元 件103及電路基板ιοί，會產生如是之範圍内的硬化應力之 絕緣性接著劑107 ’就能防止對半導體元件1 〇3及電路基板 本紙張尺度適用中國國家標卒（rNS ) Λ4規格（210X：297公釐） ---------裴---_--Γ訂 (誚先閱讀背而之注意事項再填寫本頁) A7 _________B7_ 五、發明説明（6 ) 101之損傷。 其次’如在第20圖上之步驟3所示，將半導體元件103 之突4電極104對電路基板1〇1之電極102作位置對正，再 依導電性接著劑106而將突起電極104配置在電路基板！01 上之電極102。由於該位置對正，使絕緣性接著劑} 07在半 導體元件103與電路基板1〇1之間，介在於電路基板1〇1之 相對面10la與半導體元件1〇3之相對面l〇3b之間並連結雙 方。 接著，稱為並行硬化工程之如第20圖上的步驟4所示 ’上述半導體元件103及上述電路基板1〇1，即，以加熱並 硬化上述絕緣性接著劑107及上述導電性接著劑106，之硬 化爐，或以附有加熱之絲而最少亦可加熱上述半導體元件 103及上述電路基板ιοί之任一方的加熱活工具，將導電性 接著劑106及絕緣性接著劑1〇7，以同—工程作硬化並如第 1圖所示，形成為半導趙裝置100。此時，由於上述導電性 接著劑10 6及絕緣性接者劑1 〇 7之硬化，乃使電路基板丨〇 1 與半導體元件103並非為暫固定而使其真正固定。 於上述硬化爐之加熱溫度，於上述環氧系樹脂之場合 ，在本實施例為120±10。(：，並以同條件硬化導電性接著劑 106及絕緣性接著劑107 » 於上述步驟4，導電性接著劑1〇6及絕緣性接著劑1〇7 之硬化時間，乃使絕緣性接著劑1〇7比導電性接著劑1〇6先 予硬化、收縮。其理由為，若將導電性接著劑1〇6先予硬 化之場合，突起電極104與電路基板1〇1上之電極1〇2，以 本紙張尺度適用中國围家標卑（CNS〉Λ4規格（2丨0X297公趁） 装-----Γ訂 (誚先閱讀背而之注意事項再填寫本頁) -9- A7 ---------B7 五、發明説明（7 ) " -- • . -II---- I"— — II _ I 丁 ./ί. (1S先閲讀背面之注意事項再填寫本頁) 非接合之狀態硬化之時’以其後之絕緣性接著劑ι〇7的硬 化、f縮上，不能改善上述非接合之狀態之故。而上述硬 化“之具趙例，有下列之場合，即，硬化溫度為戰 之時’絕緣性接著齊!107以25分鐘硬化、收縮，而導電性 接著劑106以40分鐘硬化，硬化溫度為12代之時，絕緣性 接著劑107以20分鐘硬化、收縮，而導電性接著劑_以35 -^^^化；硬化溫度為15代之時，絕緣性接著劑1〇7以1〇 分鐘硬化、收縮，而導電性接著劑1〇6以2〇分鐘硬化。 為在如是之時刻使絕緣性接著劑1〇7比導電性接著劑 106較早硬化、收縮，以及在先硬化、收縮之絕緣性接著 劑107，為使突起電極104與電路基板1〇1上之電極ι〇2確實 接合，並且，對半導體元件1〇3不會產生裂痕等之損傷， 絕緣性接著劑107乃採用上述之物性值。又，為使硬化時 間有偏差，乃使絕緣性接著劑1 〇7之凝膠時間及硬化時間 比導電性接著劑106為較早，並且，由於絕緣性接著劑1〇7 之硬化、收縮而不予損傷半導體元件1〇3，乃作絕緣性接 著劑107之硬化條件的低溫化。於上述絕緣性接著劑1〇7及 上述導電性接著劑1 〇 6之上述凝膠時間及硬化時間之差異 ’乃起因於兩者之成份的不同。即’上述絕緣性接著劑丨〇7 係其所含有之接著劑成份起硬化，惟，上述導電性接著劑 106係所謂之BCA含有溶劑成份，而以揮發該溶劑成份作 乾燥固定化。如是，有無上述溶液成份B成為產生上述凝 膠時間及硬化時間之差異的要因之一。 加於半導體元件1〇3及電路基板ιοί之硬化應力，即， 本紙张尺度適用中國國家標?f ( CNS ) Λ4規格（210Χ297公t ) -10- A7 _________Β7· 五、發明説明（8 ) ~ 内部應力，乃隨硬化溫度而變化。例如，於l〇〇〇c、3〇分 鐘為490.3 \10-6卩3;於120。〇、30分鐘為882.6父106匕；
I n n n n n n n n I ^ n n n n K D T I · Ί ，-" (誚先閱讀背而之注意事項再填寫本頁) 於150°C ' 15分鐘為1520.0X 1〇6 Pa。因此，有必要使上述 硬化時間具有偏差，並且，將上述硬化應力位於392.3 X 1 〇6 〜1 176.8 X 106 Pa。 如是，半導體元件103及電路基板101，不僅以導電性 接著劑106並亦以絕緣性接著劑1〇7作連接，是故，雖因電 路基板101與半導體元件103之熱膨脹率差，或電路基板1〇1 之變形，而對於突起電極104與電路基板ιοί之電極102的 連接部份所作用之應力，就因絕緣性接著劑1〇7之硬化、 收縮而減低’使電路基板101與半導體元件103之連接強度 ’較習知為強’因此’使突起電極104與電路基板1〇1之電 極102的連接阻抗值及其偏差變成較小，並且，能獲得半 導體元件103與電路基板1〇1之連接強度較強而穩定，及可 靠度高之接合。 在上述之說明，因製造工程之簡化等理由，乃將絕緣 性接著劑107塗佈於電路基板101上，惟，亦能塗佈在半導 體元件103之相對面1 〇3b、或電路基板1 〇 1之相對面1 〇 13及 半導體元件103之相對面i〇3b的雙面。 在上述之說明，如在第1圖所示，絕緣性接著劑107於 半導體元件103與電路基板ιοί之間，僅塗佈於1處，但， 並不限定於此’其可隨半導體元件1〇3之面積的增大化， 如在第5圖及第6圖所示，如在半導體裝置115、116之場合 ，將絕緣性接著劑107塗佈在多數處。如是，可使絕緣性 本紙张尺度適川中國囤家標卒（（:，NS ) Μ規格（210X 297公赞） " -11- 經滴部中央標準局兵Τ,消t合作社印纪 A7 _________B? 五、發明説明（9 ) 接著劑107之塗佈位置有2處以上，乃能將1次之塗佈量減 少以降低塗佈量之偏差，並能塗佈一定量之絕緣性接著劑
I 107，因此，在電路基板101上安裝半導體元件103之時， 能將絕緣性接著劑10 7不擴展於電路基板1 ο 1之電極丨0 2。 如在第1圖、第5圖及第6圖所示，在半導體元件1〇3與 電路基板101相連接之時，若配置為絕緣性接著劑1〇7不附 著在半導體元件103之電極103a及電路基板1〇1之電極1〇2 的任一方時’乃具有如下之功效。即，安裝於電路基板1〇1 後’判明半導體元件103為不良時，由於絕緣性接著劑1 〇7 未附著在電路基板101上之電極102之故，若絕緣性接著劑 107為上述環氧系樹脂之時，就將上述不良半導體元件以 玻璃轉移點以上之溫度的約200〜230。(：作加熱，可使絕緣 性接著劑107軟化並減弱接合強度，乃可將絕緣性接著劑 107從電路基板1 〇 1剝離，並能約以15秒鐘可將半導體元件 103從電路基板1〇1去除。因此，電路基板ι〇1能再度使用 ’乃肖b發揮再度將良品之半導體元件103安裝之功效。 雖然’無法獲得如上述之功效，但，絕緣性接著劑〗07 亦可如在第4圖所示之半導體裝置no之場合，配置為附著 在電路基板101之電極102’或在半導體元件1〇3之電極1〇3 a 及電路基板101之電極102。 在上述之說明，絕緣性接著劑1〇7係採用液體狀為其 例，但’成形為顆粒狀或薄膜狀之接著劑亦可以。將絕緣 性接著劑107作成薄膜狀或顆粒狀，即，能降低絕緣性接 著劑107之供給量的不均，並能供給一定量之絕緣性接著 本紙張尺度適用中國國家標净（（:NS ) Λ4现格（210X297公瘦） (讀先閱讀背而之注意事項再填寫本頁) ,ιτ -12- 經滴部中"桴準局β工消於合作社印5:, A7 ----------Β7· 五、發明説明（10 ) ~ 劑 107。 此時’顆粒狀或薄膜狀之絕緣性接著劑107由下述之
I 理由可知’其平面形狀上之縱橫比以1以上之矩形或橢圓 形狀者為佳。即’如將後述，半導體元件1 〇3與電路基板丨〇 1 以絕緣性接著劑107固定之後，如在第丨4圖所示，在半導 體元件103與電路基板101之間隙注入第1封止用樹脂16卜 上述第1封止用樹脂161，如在第21圖及第22圖所示，從半 導體元件103之侧端面及其近傍部份2〇6對上述間隙，如箭 頭201所示，沿一方向注入之場合，在箭頭2〇1之注入方向 上的絕緣性接著劑107之後端部份2〇2會發生氣泡，而產生 空隙部份。為去除如是之氣泡的發生，乃將絕緣性接著劑 107配置為對於上述注入方向成為流線形，並將絕緣性接 著劑107配置為沿著對於上述箭頭2〇 1之上述注入方向為直 交之直交方向的縱方向尺寸203，與沿著上述注入方向之 絕緣性接著劑107之橫方向的尺寸2〇4之比，成為！以上之 平面形狀。 該縱橫比為1以上之條件，絕緣性接著劑1〇7於上述之 液體狀的場合’對於塗佈部份之平面形狀亦能適用。又， 將半導體元件103載置於電路基板1〇1上時，電路基板1〇1 上之顆粒狀或薄膜狀之絕緣性接著劑1〇7，由於有必要接 觸於半導體元件1〇3之相對面l〇3b，是故，從電路基板 之相對面101a起之顆粒狀或薄膜狀之絕緣性接著劑1〇7的 高度’乃是上述接觸為可行之高度。上述顆粒及薄膜之平 面形狀尺寸為’例如在第1圖所示之半導體元件1〇3之電極 本紙張尺度谪用中國囤家標舉（rNS ) Λ4规格（210X 297公f ) -. n n^i ^^^1 In . . · /· (翱先閱讀背而之注意事項再填寫本頁) -13- A7 B7 五、發明说明（11 ) ---------.衣-- (請先閱讀背而之注意事項再填寫本頁) 103a、103b間之尺寸未滿的大小，其厚度為對應半導體元 件103與電路基板1〇1之間的尺寸之2〇〜2〇〇em，而稍為 超過若干之尺寸大小。 又，使用顆粒狀或薄膜狀之絕緣性接著劑1 〇7之場合 ，亦有下述之功效。即，如上述，如在第20圖步驟2及步 驟3所示，使用液狀之絕緣性接著劑1〇7之時，絕緣性接著 劑107之塗佈動作，及對電路基板1〇1上之半導體元件1〇3 之封裝動作，乃在別工程實行。而對於顆粒狀或薄膜狀之 絕緣性接著劑107為固體狀之故，因之，可實行上述封裝 動作，並且可將顆粒狀或薄膜狀之絕緣性接觸劑1〇7配置 在電路基板101與半導體元件1〇3之間。
-I— 1^1 i - HH 在上述之說明，乃直接將絕緣性接著劑1〇7附著在半 導體元件103之相對面l〇3b，但，如下述說明，在半導體 元件103之相對面l〇3b ’即’首先，例如作成以環氧系樹 脂所成之絕緣性樹脂153的半導體元件150，然後，再以絕 緣性接著劑107連接半導體元件15〇及電路基板1(H亦可以 。即，如在第8圖所示，在半導體元件103之電極1〇3a上形 成突起電極104之後，將半導體元件1〇3固定在旋轉台151 上。然後’將絕緣樹脂153塗佈在半導體元件1〇3之相對面 103b上之大的中央部份，並將旋轉台151沿著箭頭方向旋 轉。由於此，如在第9圖所示，絕緣樹脂153乃因遠心刀而 擴散’使半導體元件103之相對面l〇3b及突起電極1〇4周邊 之電極103a就被絕緣樹脂所覆蓋，而突起電極1〇4之前端 部份乃露出在絕緣樹脂153上。然後，將絕緣樹脂153硬化 本紙張尺度適用中國國家標率（CNS ) Λ4規格（210X297公f ) -14 - 对漓部中决桴?1,-局只工消費合作权印於 A7 ----- B7 五、發明説明（" 硬化後，如在第10圖及第11圖所示，將突起電極1 〇4之 前端部份押住在具有平坦面之基材152，使突起電極1〇4之 前端部成為平坦之面，並且，作為接合面而予露出。以後 ，如上述，又如在第12圖及第13圖所示，將導電性接著劑 106設在突起電極1〇4之前端部，並且，在半導體元件15〇 與電路基板101之間，配置絕緣性接著劑1〇7，而使半導體 元件150與電路基板101連接。又，如在第13圖所示將所作 成之半導體裝置令為半導體裝置155。 如是’由於在半導體元件103之相對面i〇3b上形成絕 緣樹脂153，即，絕緣樹脂153就保護半導體元件1〇3上及 突起電極104周邊之電極l〇3a，並且，安裝於電路基板1〇1 上之後耐濕性亦十分優越，乃有防止半導體元件1〇3之電 極l〇3a的腐蝕之功效。又，依據上述半導體裝置155，於 半導體元件103與電路基板1〇1之連接後，在電路基板1〇1 與半導體元件103之間隙部份，具有能予免除絕緣性樹脂 之注入、硬化的工程之功效。 對於上述絕緣樹脂1 53，亦能使用不含控制該絕緣樹 脂153之熱膨脹的二氧化矽等之材料，但，若含有之場合 ’由於其大約相等於絕緣性接著劑107之成份，因此，於 絕緣樹脂153與絕緣性接著劑1〇7之介面部份，能減低應力 之發生。 彳 於上述之各個半導體裝置100、110、115、116、155 ’對半導體元件與電路基板之間隙，例如，在第14圖所示 ’或在第20圖上之步驟5所示，注入第！封止用樹脂16ι。 本紙張尺度適则，賴緖.if ( ('NS ) Λ4規格（2I0X297公楚） (請先閱讀背而之注意事項再填寫本Π )
-15- Α7 Β7 五、發明説明（13 ) 而如上述’對於半導體裝置155不進行上述第1封止用樹脂 161之上述注入亦可以。針對該第1封止用樹脂ι61之注入 動作i以半導體裝置1〇〇為例作下述說明。 上述注入方法之一為，如在第14圖所示，以號碼2〇6 表示。係以樹脂注入裝置171從半導體裝置1〇〇上之側端面 及其近傍部份之一處注入第1封止用樹脂161之方法。 而最佳之方法為，如在第15圖所示，在以排氣裝置172 可使内部設定為減壓狀態之作業室173内，配置半導體裝 置100之後’以排氣裝置172使作業室173内成為減壓狀態 。於該減壓下，以樹脂供給裝置174並如箭頭所示，在半 導體裝置100之側端面及其近傍部份2〇6，沿著半導體裝置 100之4邊，在電路基板101上塗佈第1封止用樹脂161。塗 佈完了之後，將作業室173内回復為大氣壓狀態。 另方面’由沿著半導體裝置1〇〇之4邊所塗佈的第1封 止用樹脂161所密封之半導體元件103與電路基板1〇1.之間 隙部份，乃仍然處在上述減壓狀態下，因此，沿著上述4 邊所塗佈之第1封止用樹脂161，因其壓力差乃如在第16圖 所示’將侵入至上述間隙内而使上述間隙填充第1封止用 Μ脂161。於此’第1封止用樹脂161之塗佈量’係以該第1 封止用樹脂161之填充，而封止半導體元件1〇3與電路基板 101之間隙’以能防止水份之流入、防止腐钱、緩和熱應 變之應力、確保接合部之可靠度（信賴性）之程度的量。 依據該注入方法，其比於大氣壓中從半導體元件1〇3 之側端面及其近傍部份2 〇 6塗佈注入絕緣性之封止用樹脂 本紙張尺度適扣中國國家標肀（（、NS ) Λ4规格（210X 297公f ) 0' I I - 1 I n I I I - I 1 - I n (請先閱讀背而之注意事項再填寫本頁} -16- 經滴部中次標準局货工消费合作社印繁 A7 ^-________ B7 五、發明説明（I4 ) 的方法’能以更短時間將封止用樹脂注入於上述間隙。又 ，於半導體元件103之尺寸為15 xl5mm以上之大型的場合 ’亦k容易以短時間注入封止用樹脂。 對於如上述’第1封止用樹脂16丨填充於其上述間隙之 半導體裝置而言，如在第17圖所示，如同覆蓋該半導體裝 置之整面，而設置可有效發散於該半導體裝置所產生之熱 量的，例如，熱傳導率為0.2〜2W/mk之範圍，最好有1 w/mk 以上之熱傳導率的放熱性樹脂163亦可以。又，雖不設置 上述放熱性樹脂163，惟，在第1封止用樹脂161中含有傳 熱性良好之例如，將氧化鋁等之金屬作成填充物狀，亦能 提昇半導體元件103之放熱性。而在上述填充物若使用金 屬之場合’為消除因填充物而生之導電性，乃使用施予樹 脂封套之填充物。 替代如上述之封止用樹脂注入方法，乃如在第丨8圖及 第19圖所示，例如，以第2封止用樹脂162覆蓋半導體裝置 1〇〇 ’亦能封止半導體元件103。而第2封止用樹脂162有薄 膜狀或液體狀者’在第18圖表示液體狀之場合，而第19圖 表示薄膜狀之場合。作具體性說明，即，在處於減壓下之 上述作業室173内’加熱半導體裝置1〇〇之後，以第2封止 用樹脂162覆蓋半導體元件103之整面。然後，將作業室173 回復為大氣壓，使第2封止用樹脂162硬化而進行半導體裝 置100之封止。 由於此，其比在大氣壓中而從半導體元件103之側端 面及其近傍部份206注乂塗佈絕緣性之封止用樹脂之方法 本紙張尺度適州肀國國家標肀（（，奶）/\4規格（2丨0\297公釐） ---------I I - f , (請先閱讀背而之注意事項再填寫本頁) '11
A7 BT 好滴部中"標準局αζ-τ·消贤合竹私印繁 五、發明説明（l5) ’能以更短時間作塗佈或作薄板請帖，並且，半導體元件 103之尺寸雖然增大’亦能有所對應之功效。 “使用上述之第1封止用樹脂161之場合同樣，設置放 熱性樹脂163或在第2封止用樹脂162内含有上述氧化銘等 之填充物亦可以。 又，上述第1封止用樹脂161及上述第2封止用樹脂162 ’以環氧系或丙烯（亞克力）系，而最好以含有環氧成份之 材料所構成者為佳。又，上述第丨封止用樹脂161及上述第 2封止用樹脂162並不限定於熱硬化性樹脂，而以熱可塑性 樹脂亦可以。 於上述之半導體裝置1〇〇、11〇、115、116、155，突 起電極104與電路基板1〇1上之電極102，係介著導電性接 著劑106作連接，但，導電性接著劑1〇6不一定有其必要性 。在第23圖，表示不使用導電性接著劑1〇6而僅以絕緣性 接著劑107固定半導體元件1〇3與電路基板ιοί之半導體裝 置211。即’如上述，由於絕緣性接著劑ι〇7具有收縮性， 是故，當半導體元件1〇3與電路基板1〇ι由絕緣性接著劑1〇7 所連接之時，半導體元件103與電路基板1〇1乃互相拉引， 而使突起電極104與電路基板1〇1上之電極1〇2接觸，乃能 作電氣性連接。 如上述，雖僅以絕緣性接著劑1〇7固定,半導體元件丨〇3 與電路基板101之時’突起電極丨〇4與電路基板101上之電 極102，介著絕緣性接著劑107確實作連接，但，為增加連 接之可靠度’即’如前述說明，併用導電性接著劑1 為 本紙張尺廋诮用中囤囤家標彳（（’NS ) Λ4規格（210Χ297公漦） — ————— — ————————— ^ I n I n I It τ . ί 彳 (誚先閲讀背而之注意事項再填寫本頁) -18- A7 B7
五、發明説明（l6 ) ("先閱讀背而之注意事項再填寫本頁) 在上述之說明，半導體元件103係採用平板狀之場合 為例但，本實施態樣之安裝方法並不限定於此，而如在 第24圖所示，對於球狀之半導體元件213亦可適用，而使 用本實施態樣之安裝方法亦能作成將上述球狀之半導體元 件安裝在電路基板之半導體裝置215。 本發明，乃參照所添附之圖面而針對適宜之本實施，熊 樣作充分之記載，但，對於熟練該技術之人員而言，可了 解尚有種種之變形或修正。不過，如是之變形或修正，若 非在於所添附之本發明申請專利範圍之外者均應包含在 本發明之t乙事，應有所理解。
,1T 圖式之簡單說明 本發明之該等及其他之目的與特徵，由所添附之圖面 與最佳實施態樣所關連之下述說明即可了解。該圖面共有 第1圖係表示本發明實施態樣之半導體裝置構造的截 面圖； 第2圖係表示在第i圖所示之半導體裳置製作工程的一 工程圖’其表示半導體元件之突起電極轉移導電性 之狀態； 第3圖係表示在第旧所示之半導體|置製作工__ 工程圖’其表示電路基板上塗佈絕緣性接著劑之狀圖、 第4圖係表示在第旧所示之半導體裝置之變形例的截 面圖； 本紙張尺料财關雜彳格（2“ -19- A7 B7 五、發明説明（17 ) 第5圖係表示在第〗圖所示之半導體裝置的其他變形例 之截面圖； ^ 6圖係表示在第丨圖所示之半導體裝置的又另一變形 例之截面圖； 第7圖係表示在第丨圓所示之半導體裝置上去除半導 體元件部份之狀態； 第8圖係表示在第！圖所示之半導體裝置的變形例上之 半導體裝置的製作工程上之一工程； 第9圖係表示在第丨圖所示之半導體裝置的變形例上之 半導體裝置製作工程上之一工程，為第8圖上之其次工程 9 第1〇圖係表示在第1圖所示之半導體裝置的變形例上 之半導體裝置製作工程上之一工程，為第9圖上之其次工 程； 第π圖係表示在第1圖所示之半導體裝置的變形例上 之半導艎裝置製作工程上之一工程，為第10圖上之其次工 程； 第12圖係表示在第1圖所示之半導體裝置的變形例上 之半導體裝置製作工程上之一工程，為第U圖上之其次工 程； 第13圖係表示在第1圖所示之半導體裝置的變形例上 之半導體裝置的截面圖； 第14圖係表示對於在第1圖所示之半導體裝置注入封 止用樹脂之狀態； 本紙張尺度適用中國國家標肀（CNS ) Λ4規格（210X 297公釐） ---------Λ-- -- /ί,ί Λ-\ (請先閱讀背面之注意事項再填寫本頁)
、1T -20- 經漓部中次標準扃負工消費At作.社印絮 A7 _____B7 五、發明説明（a) ~~~ 第15圖係表示對於在第丨圖所示之半導體裝置注入封 止用樹脂用之裝置的構成； ^16圖係表示對於在第1圖所示之半導體裝置進行封 止用樹脂注入之狀態； 第17圖係表示將有注入封止用樹脂之第丨圖所示的半 導體裝置，以放熱性樹脂復蓋之狀態的載面圖； 第18圖係表示對於在第1圖所示之半導體裝置，有注 入第1封止用樹脂之狀態的截面圖； 第19圖係表示對於在第1圖所示之半導體裝置，有注 入第2封止用樹脂之狀態的截面圖； 第20圖係表示於本發明之實施態樣上，半導體元件在 電路基板上之安裝方法的動作工程之流程圖： 第21圖係表示將封止用樹脂沿著一方向注入於第^圖 所示之半導體裝置之場合，其矩形狀之絕緣性接著劑之配 置狀態的平面圖； 第22圖係表示將封止用樹脂沿著一方向注入於第1圖 所示之半導體裝置之場合，其橢圓狀之絕緣性接著劑之配 置狀態的平面圖； 第23圖係表示本發明實施態樣之半導體裝置上之其他 構造，為不使用導電性接著劑之場合的構造之截面圖； 第24圖係表示本發明實施態樣之半導體裝置上之其他 構造，為使用球狀之半導體元件之場合的構造之截面圖； 第25圖係表示在半導體元件之電極上形成突起電極之 形成工程中之一工程’乃表示毛細管前端部； 氺紙張尺度適州中國國家標肀（CNS ) Λ4規格（2I0X297公釐） ---------於-- (邡先閱讀背而之注意事項再填寫本頁) 訂 -21 - A7 —---------- BT_ —_ 五、發明説明（I9 ) 第26圖係表示在半導體元件之電極上形成突起電極之 形成工程中之一工程’乃表示在毛細管前端形成球形之狀 態；1 第27圖係表示在半導體元件之電極上形成突起電極之 形成工程中之一工程，乃表示在第26圖所示之球形壓著在 半導體元件上之電極的狀態； 第28圖係表示在半導體元件之電極上形成突起電極之 形成工程中之一工程，乃表示在半導體元件上之電極上形 成上述突起電極之狀態； 第29圖係表示在半導體元件之電極上形成突起電極之 瓜成工程中之一工程，乃表示將上述突起電極之高度作均 一化之狀態； 第30圖係表示在半導體元件之電極上形成突起電極之 形成工程中之-工程，乃表示將導電性接著劑轉移至上述 突起電極之狀態。 第31圖係表示習知之半導體裝置。 ----------我— (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中泱摞準局β-τ-消费合作私印絮 I標 |家 一03 一國 I中 用 度 尺 一張 紙 ί本
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I釐 公 7 9 2 X -22- 經消部中决標準局兵工消贤合作私印製 A7 B7 五、發明説明（2〇) 元件標號對照 1...電路基板 103b·.·半導體元件之相對面 2·.·電路基板之電極 104·.·突起電極 3…半導體元件 106…導電性接著劑 3a…半導體元件之電極 107…絕緣性接著劑 5，14…工作台（平坦面） 150，155.··半導體裝置 6...導電性接著劑 151…旋轉工作台 15…毛細管 152…基材（平坦面） 16... Au 線 153…絕緣樹脂劑 16a._.Au線之前端 161…第1封止用樹脂劑 17…放電電極（焊鎗） 162…第2封止用樹脂劑 18...金球 163…放熱性樹脂劑 19...塊形底部 172…排氣裝置 20…塊形（平坦化） 173…作業室 100 ， 100 ， 115 ， 116". 174·.·樹脂供給裝置 半導體裝置 201...箭頭 101···電路基板 202·.· 107之後端部 101a…電路基板之相對面 203.·· 107之縱方向尺寸 102…電路基板之電極 204··. 107之橫方向尺寸 103…半導體元件 206…半導體裝置100之侧 103 a…半導體元件之電極 端面及其近傍部份 ·>- ί ^^1 In In ^^1 1^1 ^ J- 方 、va• . / (誚先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標率（CNS ) Λ4規格（210X297公釐） ' -23-

Claims (1)

  1. '申請專利範圍 A8 B8 C8 D8· 1，一種電路基板的半導體元件安裝方法，其程序在於包 含有： 設置絕緣性接著劑，係最少亦在電路基板及半導 體元件上的互相之相對面的任一方設置，而硬化之同 時亦作收縮者； 位置對正，係使上述電路基板上之電極與上述半 導體元件上之突起電極能相對應； 連結，係以上述絕緣性接著劑，使上述電路基板 及上述半導體元件上的相互之上述相對面連結； 硬化，係將上述絕緣性接著劑硬化； 電氣性連接，係將上述電路基板上之上述電，極， 與上述半導體元件上之上述突起電極，由上述絕緣性 接著劑之上述收縮作電氣性連接；及 固定’係將上述半導體元件與上述電路基板固定 為連結狀態。 2·如申請專利範圍第1項所記載之電路基板的半導體元件 安裝方法，其中， 上述絕緣性接著劑設置於將上述半導體元件與上 述電路基板相連結之狀態下，對於上述電路基板上之 電極及上述半導體元件上之突起電極的任一方，均不 接觸之位置。 3·如申請專利範圍第2項所記載之電路基板的半導體元件 安裝方法，其中， 上述絕緣性接著劑之配置可在上述相對面之多數 本紙張U剌標準（CNS )八4胁（210X297公釐) --_---^-----本-- -f. * ** (請先閲讀背面之注^'項再填寫本頁) -^9' Γ 麵濟部中夬棣率局貝工消費合作社印装 -24- 經濟部中央梂率局貝工消費合作衽印製 Α8 Β8 C8 D8· 六、申請專利範圍 處所進行。 4. 如申Μ專利範圍第丨項所記載之電路基板的半導體元件 安裝方法，其中， 上述絕緣性接著劑為薄膜狀或顆粒狀。 5. 如申吻專利範圍第4項所記載之電路基板的半導體元件 安裝方法，其程序包含有： 配置絕緣性接著劑，係最少亦配置在上述電路基 板及上述半導體元件上的相互之相對面上之任一方； 及 對正位置，係使上述電路基板上之上述電極，與 上述半導體元件上之上述突起電極能相對應。 6. 如申請專利範圍第丨項所記載之電路基板的半導體元件 安裝方法，在配置上述絕緣性接著劑之前的程序含有 塗佈絕緣樹脂，係除上述半導體之上述突起電極 與上述相對面之上述電路基板上的上述電極之連接部 份之外，最少亦保護上述半導體元件上之電極之用； 及 設置絕緣性接著劑’係於上述絕緣樹脂硬化之後 設置。 7. 如申請專利範圍第6項所記載之電路基板的半導體元件 安裝方法，其上述絕緣樹脂之塗佈程序含有： 滴下絕緣樹脂’係將絕緣樹脂滴下在固定於旋轉 工作台上之上述半導體元件的上述相對面上之大約為 家梂準(CNS )八4胁(210X297公釐) " n H^I mu. ί ^^^1 (m —m I 1^1 nn nn waJ _ /3,:¾ (請先閲讀背面之注$項再填寫本頁) -25- Α8 Β8 --—~~ ____D8' 申請專利細 ~ ~ 中央部份；及 %轉工作台，係將上述工作台旋轉而進行塗佈。 8.如申請專利範圍第i項所記載之電路基板的半導體元件 安裴方法，其中， 當上述電路基板與上述半導體元件固定之後，從 在上述電路基板上之上述半導體元件的側端面及其近 傍部份，將第1封止用樹脂劑注入於上述電路基板與上 述半導體元件之間隙。 • ^申請專利範圍第8項所記載之電路基板的半導體元件 裝方法其中，上述絕緣性接著劑之配置特徵在於 具有： (請先閲讀背面之注意事項再填寫本頁) 趣濟部中央榡準局貝工消費合作社印製 顆粒狀或薄膜狀； 矩形狀或橢圓狀之平面形狀，係上述第1封止用樹 脂劑從上述侧端面及其近傍部份沿著-方向，注入於 上述電路基板與上述半導體元件之上述間隙時，乃 有該形狀；及 縱橫比為1以上，係沿著直交於上述第1封止用π 曰劑之上A #向的注入方向之直交方向的上述絕緣 性接著劑之縱方向的尺寸，對沿著上述注入方向之橫 方向之尺寸的比值。 申請專利範圍第8項所記載之電路基板的半導體元件 文裝方法，其中，上述第1封止用樹脂劑注入於上述 路基板與上述半導體元件之間隙的程序含有.· 固定’係將上述電路基板與上述半導體元件固 訂 具 樹 電 定 本紙張用中關家轉（CNS ) A4i)y^ ( 2"^~297公着- 26 夂、申請專利範圍 置於·下’係將上述電路基板與上述半導體元 件置於比大氣壓為低之減壓下； 塗佈密封，係在該減壓下沿著上述半導體元件之 侧端面及其近傍部份，而對該半導體元件之全周塗佈 上述第I封止用樹脂劑，以密封上述間隙； "回復大氣屢，係密封之後將上述電路基板與上述 半導體元件回復為大氣壓；及 k入間隙内’係回復為大氣壓後由其氣壓差而將 塗佈在上述側端面及其近傍部份之上述^封止用樹脂 劑侵入至上述間隙内。 如申請專㈣15第8項所記狀電路基板的半導體元件 安裝方法，其中， ;主入上述第1封止用樹脂劑之後，以放熱性樹脂覆 蓋上述半導體元件。 12·如申凊專利範圍第！項所記載之電路基板的半導體元件 鯉濟部中央榡準局負工消費合作社印袋 女裝方法，其中，以上述第2封止用樹脂劑進行封止之 程序含有： 固疋，係將上述電路基板與上述半導體元件固定 減壓’係於該固定之後將上述電路基板與上述半 導體件置於比大氣壓為低之減壓環境下； 覆蓋，係於該減壓下以第2封止用樹脂劑覆蓋上述 半導體元件； 本紙張 )爾(2ΐ^ϋΓ) -27- 經濟部中央標準局男Η消費合作社印裝 A8 B8 C8 _______ D8* 六、申請專利範圍 回復大氣壓，係於該覆蓋之後將上述電路基板與 上述半導體元件回復為大氣壓；及 封止’係回復為大氣壓之後以上述第2封止用樹脂 劑進行封止上述半導體元件於上述電路基板上。 13. 如申請專利範圍第12項所記載之電路基板的半導體元 件安裝方法’其中，上述第2封止用樹脂劑為熱軟化性 樹脂’其封止程序含有： 加熱’係於上述減低下以上述第2封止用樹脂劑覆 蓋上述半導體元件之時，乃加熱上述第2封止用樹脂劑 ;及 硬化’係回復為上述大氣壓而硬化第2封止用樹脂 劑。 14. 如申請專利範圍第12項所記載之電路基板的半導體元 件安裝方法，其中， 依上述第2封止用樹脂劑封止上述半導體元件之後 以放熱性樹脂覆蓋上述第2封止用樹脂劑。 5.如申清專利範圍第丨2項所記載之電路基板的半導體元 件安裝方法，其中， 上述第2封止用樹脂劑為薄膜狀。 16.如申請專利範圍第12項所記載之電路基板的半導體元 件安裝方法，其中， 上述第2封止用樹脂劑為液狀。 =U利圍第丨項所記載之電路基板的半導體元件 女裝方法，其程序包含有： ----- (請先閲讀背面之注項再填寫本頁)
    -28- 申請專利範圍 設置絕緣性接著劑，係最少亦在上述電路基板及 上述半導體元件上相互之上述相對面之任一方設置； 设置導電性接著劑，係設置在上述半導體元件上 之突起電極； 硬化，係以並行硬化工程進行硬化上述絕緣性接 著劑及上述導電性接著劑；及 電氣性連接，係介著上述導電性接著劑而使上述 電路基板上之上述電極與上述半導體元件上之上述突 起電極作該連接。 18.如申请專利範圍第3項所記載之電路基板的半導體元件 安裝方法，其程序包含有： 设置絕緣性接著劑，係最少亦在上述電路基板及 上述半導體元件上相互之上述相對面之任一方設置； 設置導電性接著劑，係設在上述半導體元件上之 突起電極； 硬化，係以並行硬化工程進行上述絕緣性接著劑 及上述導電性接著劑之硬化；及 電氣性連接，係介著上述導電性接著劑而使上述 電路基板上之上述電極，與上述半導體元件上之上述 突起電極作該連接。 19·如申請專利範圍第8項所記載之電路基板的半導體元件 t裝方法，其程序包含有： 没置絕緣性接著劑，係最少亦在上述電路基板及 上述半導體文件上相互之上述相對面的任一方設置； 本紙張尺^ 經濟部中央梂準局員工消費合作社印氧 A8 B8 C8 D8' 六、申請專利範圍 設置導電性接著劑，係設在上述半導體元件上之 突起電極； 硬化，係以並行硬化工程進行上述絕緣性接著劑 及上述導電性接著劑之硬化；及 電氣性連接，係介著上述導電性接著劑而使上述 電路基板上之上述電極與上述半導體元件上之上述突 起電極作該連接》 20.如申請專利範圍第12項所記載之電路基板的半導體元 件安裝方法，其程序包含有： 設置絕緣性接著劑，係最少亦在上述電路基板及 上述半導體元件上相互之相對面的任一方設置； 设置導電性接著劑，係設在上述半導體元件上之 突起電極； 硬化，係以並行硬化工程進行上述絕緣性接著劑 及上述導電性接著劑之硬化；及 電氣性連接，係介著上述導電性接著劑而使上述 電路基板上之上述電極與上述半導體元件上之上述突 起電極作該連接。 U•如申請專利範圍第17項所記載之電路基板的半導體元 件安裝方法，其中， 為使上述電路基板上之上述電極，與上述半導體 元件上之上述突起電極的接合確實進行，於上述並行 硬化工程上’上述絕緣性接著劑與上述導電性接著劑 之硬化動作，乃在上述導電性接著劑硬化之前，使上 本紙張财關家揉準（〇叫入4祕（210\297公着
    (請先閲讀背面之注^¢,項再填寫本頁) 訂 -30- 經濟部中央樣準局男工消費合作社印製 A8 B8 C8 *----------P8_ 、申請專利範圍 述絕緣性接著劑硬化、收縮。 22. 如申請專利範圍第1項所記載之電路基板的半導體元件 安裝方法，其中， 為防止因上述絕緣性接著劑之硬化、收縮而損傷 上述半導趙元件及上述電路基板，乃定由上述絕緣性 接著劑之硬化、收縮，而作用於上述半導體元件及上 述電路基板之硬化應力為，392 3 ><1〇6〜1 176 8 ><i〇6pa Ο 23. 如申請專利範圍第丨項所記載之電路基板的半導體元件 安裝方法，其中， 上述突起電極以Au、Ni ' A卜Cu、或銲錫（錫與 紹之合金）所形成。 24·如申請專利範圍第丨項所記載之電路基板的半導體元件 安裝方法，其中， 上述絕緣性接著劑為熱硬化性。 25. 如申請專利範圍第丨項所記載之電路基板的半導體元件 安裝方法，其中， 上述絕緣性接著劑係由環氧系樹脂、硅酮系樹脂 、或聚合酮胺系樹脂所成。 26. 如申請專利範圍第17項所記載之電路基板的半導體元 件安裝方法，其中， 上述導電性接著劑係由含有銀或金之導電性填充 物所成。 、 27. —種半導體裝置，其係利用申請專利範圍第丨項所記載 (請先閲讀背面之注意事項再填寫本頁) ,ιτ
    A8 B8 C8 D8. 申請專利範圍 之半導體元件安裝方法，使半導體元件安裝在電路基 板。 28. —種半導體裝置，其係利用申請專利範圍第η項所記 載之半導體元件安裝方法，使半導體元件安裝於電路 基板。 29. —種半導體裝置，其係利用申請專利範圍第Η項所記 載之半導體元件安裝方法，使半導體元件安裝在電路 基板。 30· —種半導體裝置，其係利用申請專利範圍第2〇項所記 載之半導體元件安裝方法，使半導體元件安裝在電路 基板。 Γ ： ,於 (請先閱讀背面之注f項再填寫本頁) 、1T 經濟部中央樣率局負工消費合作社印製 本紙張尺度逋用中國國家標準（CNS ) Α4規格（210X297公釐） -32-
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US6651320B1 (en) 2003-11-25
DE69831101D1 (de) 2005-09-08
KR100395444B1 (ko) 2003-08-21
CN1138460C (zh) 2004-02-11
EP1175138A3 (en) 2002-03-13
EP1020104B1 (en) 2002-11-27
DE69831100T2 (de) 2006-06-08
WO1999018766A1 (en) 1999-04-15
EP1020104A1 (en) 2000-07-19
EP1175138A2 (en) 2002-01-23
CN1271509A (zh) 2000-10-25
DE69831101T2 (de) 2006-06-08
DE69809787T2 (de) 2003-09-18
EP1175138B1 (en) 2005-08-03
DE69831100D1 (de) 2005-09-08
EP1194030B1 (en) 2005-08-03
EP1194030A1 (en) 2002-04-03
KR20010024320A (ko) 2001-03-26

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