DE69831100D1 - Montagemethode für Halbleiterbauteile auf einer Leiterplatte - Google Patents

Montagemethode für Halbleiterbauteile auf einer Leiterplatte

Info

Publication number
DE69831100D1
DE69831100D1 DE69831100T DE69831100T DE69831100D1 DE 69831100 D1 DE69831100 D1 DE 69831100D1 DE 69831100 T DE69831100 T DE 69831100T DE 69831100 T DE69831100 T DE 69831100T DE 69831100 D1 DE69831100 D1 DE 69831100D1
Authority
DE
Germany
Prior art keywords
circuit board
printed circuit
semiconductor devices
mounting method
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69831100T
Other languages
English (en)
Other versions
DE69831100T2 (de
Inventor
Yoshihiko Yagi
Hiroyuki Otani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69831100D1 publication Critical patent/DE69831100D1/de
Publication of DE69831100T2 publication Critical patent/DE69831100T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04Mounting of components, e.g. of leadless components
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Die Bonding (AREA)
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DE69809787D1 (de) 2003-01-09
US6651320B1 (en) 2003-11-25
DE69831101D1 (de) 2005-09-08
KR100395444B1 (ko) 2003-08-21
CN1138460C (zh) 2004-02-11
EP1175138A3 (de) 2002-03-13
EP1020104B1 (de) 2002-11-27
DE69831100T2 (de) 2006-06-08
WO1999018766A1 (en) 1999-04-15
EP1020104A1 (de) 2000-07-19
EP1175138A2 (de) 2002-01-23
CN1271509A (zh) 2000-10-25
DE69831101T2 (de) 2006-06-08
DE69809787T2 (de) 2003-09-18
EP1175138B1 (de) 2005-08-03
EP1194030B1 (de) 2005-08-03
EP1194030A1 (de) 2002-04-03
KR20010024320A (ko) 2001-03-26
TW398045B (en) 2000-07-11

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