TW202133279A - 具有雙側成型的系統級封裝 - Google Patents

具有雙側成型的系統級封裝 Download PDF

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TW202133279A
TW202133279A TW110118107A TW110118107A TW202133279A TW 202133279 A TW202133279 A TW 202133279A TW 110118107 A TW110118107 A TW 110118107A TW 110118107 A TW110118107 A TW 110118107A TW 202133279 A TW202133279 A TW 202133279A
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substrate
conductive
opening
sealant
mold
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TW110118107A
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TWI794819B (zh
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梁悳景
金用敏
崔宰赫
高麗贊
李喜秀
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新加坡商星科金朋有限公司
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Abstract

一種半導體裝置係包含一基板，其係具有一穿過該基板而被形成的開口。一第一電子構件係被設置在該第一開口的一覆蓋區之外的該基板之上。一第二電子構件係相對該第一電性構件地被設置在該基板之上。一第三電子構件係相鄰該第一電子構件地被設置在該基板之上。該基板係被設置在一模具中，其係包含該模具的一在該基板的一第一側邊之上的第二開口。該模具係接觸在該第一電子構件以及該第三電子構件之間的該基板。一密封劑係沉積到該第二開口中。該密封劑係流動通過該第一開口，以覆蓋該基板的一第二側邊。在某些實施例中，一模具膜係被設置在該模具中，並且一在該基板上的互連結構係被嵌入在該模具膜中。

Description

具有雙側成型的系統級封裝
本發明係大致有關於半導體裝置，並且更具體而言係有關於具有雙側成型的系統級封裝裝置。
半導體裝置係常見於現代的電子產品。半導體裝置係在電性構件的數量及密度上變化。離散的半導體裝置一般包含一種類型的電性構件，例如是單一發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器、或是功率金屬氧化物半導體場效電晶體(MOSFET)。積體半導體裝置通常包含數百個到數百萬個電性構件。積體半導體裝置的例子係包含微控制器、微處理器、以及各種的信號處理電路。
半導體裝置係執行廣範圍的功能，例如是信號處理、高速的計算、發送及接收電磁信號、控制電子裝置或機械系統、轉換太陽光成為電力、以及產生用於電視顯示器的視覺影像。半導體裝置係見於娛樂、通訊、電力轉換、網路、電腦、以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備中。
半導體製造的一項目標是用以產生更小的半導體裝置。更小的裝置通常消耗更低的功率，具有更高的效能，並且可以更有效率地加以產生。此外，更小的半導體裝置係具有一更小的覆蓋區，此係更小的終端產品所期望的。一更小的半導體晶粒尺寸可以藉由在前端製程中的產生具有更小的更高密度的主動及被動構件的半導體晶粒之改善來加以達成。後端製程可以藉由在電互連及封裝材料上的改善來產生具有一更小的覆蓋區的半導體裝置封裝。
製造商亦希望簡化複雜的封裝類型的形成、或是用一利用現有設備的較簡單的方式來執行先進的封裝所需的步驟。簡化該封裝製程以及利用現有的設備係容許先進的半導體封裝能夠在較低的成本下加以形成，因此節省製造商以及最終到一終端產品的消費者的金錢。雙側成型的一項挑戰是需要用到兩個不同的模具、以及設置該雙重成型製程所需的額外的資本支出。
因此，對於一種更簡單且更有成本效益的雙側成型製程係存在著需求。
根據本發明之一個態樣，其提供一種製造半導體裝置之方法，其係包括：提供一基板，其係包含一穿過該基板而被形成的第一開口；在該基板之上設置一第一電子構件；在該基板之上設置一第二電子構件；提供一包含一第一室的模具；將該基板設置在該模具中，其中該第一電子構件以及第二電子構件係被設置在該第一室中，其中該模具的一第二開口係被設置在該基板的一第一側邊之上；將一密封劑沉積到該第二開口中，其中該密封劑係流動通過該第一開口以覆蓋該第一電子構件、第二電子構件、以及該基板的一第二側邊；以及單粒化在該第一電子構件以及第二電子構件之間的該基板以及密封劑。
根據本發明之另一個態樣，其提供一種製造半導體裝置之方法，其係包括：提供一基板，其係包含一穿過該基板而被形成的第一開口；在該基板之上設置一第一電子構件；以及透過該第一開口來沉積一密封劑，以覆蓋該第一電子構件。
根據本發明之另一個態樣，其提供一種半導體裝置，其係包括：一基板，其係包含一穿過該基板而被形成的第一開口；一第一電子構件，其係被安裝在該第一開口的一覆蓋區之外的該基板之上；以及一密封劑，其係沉積在該第一電子構件的周圍以及在該第一開口中。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，其係欲涵蓋可內含在藉由以下的揭露內容及圖式所支持之所附的申請專利範圍及該些申請專利範圍的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
圖1是描繪具有一晶片載體基板或PCB 52的電子裝置50，其中複數個半導體封裝係被安裝在PCB 52的一表面之上。電子裝置50可以根據應用而具有一種類型的半導體封裝、或是多種類型的半導體封裝。不同類型的半導體封裝係為了說明之目的而被展示在圖1中。
電子裝置50可以是一獨立的系統，其係利用該些半導體封裝以執行一或多個電性功能。或者是，電子裝置50可以是一較大的系統的一子構件。例如，電子裝置50可以是一平板電腦、行動電話、數位相機、或是其它電子裝置的部分。或者是，電子裝置50可以是可被插入到一電腦中的一顯示卡、網路介面卡、或是其它的信號處理卡。該些半導體封裝可包含微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散的裝置、或是其它半導體晶粒或電性構件。小型化及重量縮減對於欲被市場接受的產品而言是重要的。在半導體裝置之間的距離可被縮短以達成較高的密度。
在圖1中，PCB 52係提供一個一般的基板，以用於被安裝在該PCB之上的半導體封裝的結構上的支撐及電互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或是其它適當的金屬沉積製程而被形成在PCB 52的一表面之上、或是在PCB 52的層之內。信號線路54係提供用於在該些半導體封裝、所安裝的構件、以及其它外部的系統構件的每一個之間的電性通訊。線路54亦視需要地提供電源、接地、以及時脈信號的連接至該些半導體封裝的每一個。
為了說明之目的，包含接合導線封裝56及覆晶58的數種類型的第一層級的封裝係被展示在PCB 52上。此外，數種類型的第二層級的封裝，其包含球格陣列(BGA)60、凸塊晶片載體(BCC)62、平台柵格陣列(LGA)66、多晶片的模組(MCM)68、四邊扁平無引腳封裝(QFN)70、四邊扁平封裝72、嵌入式晶圓層級球格陣列(eWLB)74、以及晶圓級晶片尺寸封裝(WLCSP)76係被展示安裝在PCB 52上。在一實施例中，eWLB 74是一扇出晶圓層級的封裝(Fo-WLP)，並且WLCSP 76是一扇入晶圓層級的封裝(Fi-WLP)。依據系統的需求，被配置有第一及第二層級的封裝類型的任意組合的半導體封裝以及其它電子構件的任意組合都可以連接至PCB 52。在某些實施例中，電子裝置50係包含單一附接的半導體封裝，而其它實施例則需要多個互連的封裝。
藉由在單一基板之上組合一或多個半導體封裝，製造商可以將預製的構件納入到電子裝置及系統內。因為該些半導體封裝係包含複雜的功能，所以電子裝置可以利用較不昂貴的構件以及一精簡的製程來加以製造。所產生的裝置是較不可能失效，而且製造起來是較不昂貴的，此係產生較低的成本給消費者。
圖2a係展示一具有一種例如是矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽、或是其它用於結構的支撐的基體半導體材料的基底基板材料122的半導體晶圓120。複數個半導體晶粒或構件124係被形成在晶圓120上，半導體晶粒124係藉由一非主動的晶粒間的晶圓區域或切割道126來加以分開。切割道126係提供切割區域以將半導體晶圓120單粒化成為個別的半導體晶粒124。在一實施例中，半導體晶圓120係具有一100-450毫米(mm)的寬度或直徑。
圖2b係展示半導體晶圓120的一部分的橫截面圖。每一個半導體晶粒124係具有一背表面或非主動表面128以及一包含類比或數位電路的主動表面130，該類比或數位電路係被實施為形成在該晶粒之上或是之內並且根據該晶粒的電性設計及功能來電互連的主動元件、被動元件、導電層、以及介電層。例如，該電路可包含一或多個電晶體、二極體、以及其它的電路元件，其係被形成在主動表面130內以實施類比電路或數位電路，其例如是數位信號處理器(DSP)、ASIC、記憶體、或是其它的信號處理電路。半導體晶粒124亦可包含例如是電感器、電容器及電阻器之整合的被動裝置(IPD)，以用於RF信號處理。
一導電層132係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它適當的金屬沉積製程而被形成在主動表面130之上。導電層132可以是一或多層的鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或是其它適當的導電材料。導電層132係運作為電連接至主動表面130上的電路的接觸墊。
半導體晶圓120係進行電性測試及檢查，以作為一品質管制製程的部分。人工視覺的檢查以及自動化的光學系統係被用來在半導體晶圓120上執行檢查。軟體可被利用在半導體晶圓120的自動化的光學分析中。視覺的檢查方法可以利用例如是一掃描電子顯微鏡、高強度或紫外光、或是金相顯微鏡的設備。半導體晶圓120係針對於包含翹曲、厚度變化、表面微粒、不規則性、裂縫、脫層、以及變色的結構特徵來加以檢查。
在半導體晶粒124內的主動及被動構件係在晶圓層級下，針對於電性效能以及電路功能進行測試。如同在圖2c中所示，每一個半導體晶粒124係針對於功能及電性參數，利用一包含複數個探針或測試引線138的測試探針頭136、或是其它的測試裝置來加以測試。探針138係被用來在每一個半導體晶粒124上的電路節點或導電層132做成電性接觸，並且提供電性刺激至主動表面130上的構件。半導體晶粒124係響應該些電性刺激，其係藉由電腦測試系統140來加以量測並且相較於一預期的響應以測試該半導體晶粒的功能。該些電性測試可包含電路功能、引線完整性、電阻率、連續性、可靠度、接面深度、ESD、RF效能、驅動電流、臨界電流、漏電流、以及該構件類型之特定的操作參數。半導體晶圓120的檢查及電性測試係使得通過的半導體晶粒124能夠被標明為已知良好的晶粒(KGD)，以用於一半導體封裝。
在圖2d中，一種導電的凸塊材料係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程來沉積在接觸墊132之上。該凸塊材料可以是具有一選配的助熔溶劑的Al、Sn、Ni、Au、Ag、鉛(Pb)、鉍(Bi)、Cu、焊料、或是其之組合。例如，該凸塊材料可以是共晶Sn/Pb、高鉛的焊料、或是無鉛的焊料。該凸塊材料係利用一適當的附接或是接合製程而被接合到接觸墊132。在一實施例中，該凸塊材料係藉由加熱該材料超過其熔點來加以回焊，以形成導電球或凸塊134。在某些實施例中，導電凸塊134係被回焊第二次，以改善至接觸墊132的電性耦接。導電凸塊134亦可被壓縮接合或是熱壓接合到接觸墊132。導電凸塊134係代表可被形成在接觸墊132之上的一種類型的互連結構。該互連結構亦可以使用柱形凸塊、微凸塊、或是其它的電互連。
在圖2e中，半導體晶圓120係透過切割道126，利用一鋸刀或雷射切割工具142而被單粒化成為個別的半導體晶粒124。該個別的半導體晶粒124可以被檢查及電性測試，以用於單粒化後的KGD的識別。
圖3a-3h係相關於圖1來描繪一種形成一系統級封裝(SIP)裝置的製程，其係利用一雙側成型製程。圖3a係展示一載體或臨時的基板160的一部分的橫截面圖，其係包含例如是矽、聚合物、鈹氧化物、玻璃、或是其它用於結構支撐的適當的低成本的剛性材料的犧牲基底材料。一介面層或雙面帶162係被形成或設置在載體160之上以作為一暫時的黏著接合膜、蝕刻停止層、或是熱釋放層。載體160可以是一夾具，其係在後續的處理步驟期間例如是利用一夾箝或夾頭來將一工件保持在適當的地方。
在圖3a中，封裝基板170係被設置在載體160上，其係被描繪只具有其中一SIP裝置將被形成的單一裝置區域171。在其它實施例中，基板170是大許多的，其係具有數百個或更多個裝置區域171，以用於平行地製造許多裝置。舉例而言，圖8a-8d係描繪具有十二個裝置區域171的基板170的實施例。基板170可以是一積層中介體、PCB、晶圓形式、帶式中介體、引線架、或是其它適當的基板。基板170係包含一或多個絕緣或鈍化層172、一或多個穿過該些絕緣層所形成的導電貫孔174、以及一或多個被形成在該些絕緣層之上或是之間的導電層176。基板170可包含一或多個具有酚醛棉紙、環氧樹脂、樹脂、玻璃布、磨砂玻璃、聚酯、以及其它強化纖維或織物的一組合的聚四氟乙烯預浸物(預浸料)、FR-4、FR-1、CEM-1或CEM-3之疊層的層。絕緣層172可包含一或多層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)、或是其它具有類似絕緣及結構的性質之材料。基板170亦可以是包含一主動表面的一多層的撓性的積層、陶瓷、銅箔積層、玻璃、或是半導體晶圓，該主動表面係包含一或多個電晶體、二極體以及其它的電路元件以實施類比電路或數位電路。
基板170係包含一或多個利用濺鍍、電解的電鍍、無電的電鍍、或是其它適當的沉積製程所形成的導電層或重分佈層(RDL)176。導電層176可以是一或多層的Al、Cu、Sn、Ni、Au、Ag、鈦(Ti)、鎢(W)、或是其它適當的導電材料。導電層176係包含橫向的RDL層以提供橫跨基板170的水平的導電路徑。導電層176係被形成在絕緣層172上、或是絕緣層172之間。
在圖3a中，只有一絕緣層172被描繪為一核心基板，並且一導電層176係被形成在該絕緣層的每一側上。在其它實施例中，額外的絕緣層172以及導電層176係被形成在圖3a中所示的結構之上，以實施更先進的信號繞線。導電層176的部分係根據正被形成的SIP封裝的設計及功能而為電性共通或是電性隔離的。導電貫孔174係穿過絕緣層172而被形成，以電耦接相鄰層級的導電層176。在一實施例中，導電貫孔174係藉由蝕刻、鑽孔、或是其它適當的製程，穿過絕緣層172以形成一開口，並且接著沉積導電材料到該開口中來加以形成的。在某些實施例中，用於一或多個導電層176的導電材料係在一和一或多個導電貫孔174共同的沉積步驟中加以沉積的。
一或多個開口180係完全穿過基板170來加以形成。開口180可以藉由一打孔機、一機械鑽孔機、一雷射鑽孔機、一水鑽孔機、一鋸刀，藉由在基板170被建立時圖案化絕緣層172及導電層176、或是藉由其它適當的製程來加以形成。開口180係被形成在裝置區域171之外，因而裝置佈局的選項並未因為該開口而顯著地被減低。開口180係容許一成型化合物或密封劑能夠在一後續的成型步驟期間流動在基板170的頂端側與底部側之間。
在圖3b中，焊料膏182係在其中裝置將被表面安裝到基板170的底表面177之上的位置處，被沉積或印刷到導電層176之上。焊料膏182可藉由噴印、雷射印刷、氣動地、藉由針板轉移法、利用一光阻遮罩、藉由模版印刷、或是藉由其它適當的製程來加以分配。在圖3c中，離散的裝置184係被設置在底表面177之上，其中該些離散的裝置的端子是在焊料膏182之上。離散的裝置184可以根據需要而為被動或主動裝置，以在所形成的半導體封裝之內實施任何給定的電性功能。離散的裝置184例如可以是半導體晶粒、半導體封裝、離散的電晶體、離散的二極體、等等的主動裝置。離散的裝置184例如亦可以是電容器、電感器、或是電阻器的被動裝置。
凸塊材料亦被沉積在底表面177的其它部分之上，以形成導電凸塊186。導電凸塊186係類似於以上的導電凸塊134來加以形成。用於導電凸塊186的材料可以和焊料膏182一起加以沉積為一膏、或是在一個別的球式滴落步驟中利用一不同的材料。該凸塊材料以及焊料膏182係被回焊以形成導電凸塊186，並且將離散的裝置184機械式及電性耦接至導電層176。焊料膏182可以在沉積導電凸塊186之前先被回焊，以在該球式滴落製程期間將離散的裝置184保持在適當的地方。
在圖3d中，載體160係藉由化學蝕刻、機械式剝離、化學機械平坦化(CMP)、機械式研磨、熱烘烤、UV光、雷射掃描、濕式剝除、或是其它適當的製程來加以移除，以露出基板170的頂表面179。基板170係被翻轉並且設置在載體190之上，其中底表面177係被定向朝向該載體。載體190係包含一選配的雙面帶、熱釋放層、或是其它介面層192。在其它實施例中，載體190是一夾具。在一實施例中，載體160係被再度使用作為載體190。
焊料膏182係被圖案化到基板170的頂表面179之上，並且任意所要的離散的裝置184都如上所述地加以表面安裝。半導體晶粒124a及124b係被覆晶安裝到頂表面179之上。半導體晶粒124a及124b可以實施正被產生的封裝所要的不同的功能，例如，半導體晶粒124a可以是一應用處理器，並且半導體晶粒124b可以是該應用處理器所使用的一記憶體晶片。導電凸塊134係被回焊以機械式及電性連接半導體晶粒124至導電層176。在頂表面179上的半導體晶粒124以及離散的裝置184係透過導電層176以及導電貫孔174來電連接至底表面177上的離散的裝置184以及導電凸塊186。
在圖3e中，具有離散的裝置184、導電凸塊186、以及半導體晶粒124的基板170係被設置在一模具200之內。模具200係包含一底板200a以及一頂板200b。一或多個入口埠200c係被形成在頂板200b的一側壁中，以用於密封劑的注入到該模具中。或者是，開口200c可被形成在底板200a中。在某些實施例中，模具200係包含相對開口200c的開口，以容許被排開的空氣能夠在密封劑的注入期間從該模具逸出。儘管開口200c係被描繪為緊鄰基板170，但是頂板200b的一部分在某些實施例中係延伸在開口200c以及基板170之間。底板200a以及頂板200b係界定一模具凹穴200d。模具凹穴200d係具有由頂板200b及底板200a的側壁高度所界定的充分的深度，以容納任何被設置在基板170上的電性構件。
底板200a係包含一在凹穴200d之內的模具膜202。模具膜202係由任何適當的材料所形成的。在某些實施例中，一絕緣的聚合物材料係被使用。在一實施例中，模具膜202係在板200a及200b之間延伸到模具200之外，並且藉由利用一連接至底板200a的真空而被下拉以接觸底板200a，以移除介於該模具膜與底板之間的空氣。
基板160係在模具200之內被設置在模具膜202之上。導電凸塊186係被壓入模具膜202之中，因而該些導電凸塊係排開該模具膜材料的一部分。在一實施例中，模具膜202係具有一低的彈性模數，以助於導電凸塊186被插入該膜中。在圖3f中，一密封劑或成型化合物210係透過開口200c而被注入到凹穴200d之中。密封劑210係完全覆蓋半導體晶粒124、離散的裝置184、以及導電凸塊186的除了其中那些元件接觸基板170、焊料膏182、導電凸塊134、模具200、或是模具膜202之外的每一側。尤其，在導電凸塊186與模具膜202之間的接觸係留下該些導電凸塊的尖端沒有密封劑210。密封劑210可以是聚合物複合材料，例如是具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。密封劑210是非導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。密封劑210亦保護半導體晶粒124免於由於曝露到光的劣化。
密封劑210係被注入到開口200c之中，並且採用兩個不同的路徑以覆蓋基板170。密封劑210的一第一部分係依循路徑212a以覆蓋包含半導體晶粒124以及離散的裝置184c的頂表面179。密封劑210的一第二部分係依循路徑212b，透過開口180以覆蓋基板170的底表面177，其係包含覆蓋導電凸塊186以及離散的裝置184a-184b的露出的部分。
在圖3g中，被覆蓋在密封劑210中的基板170係從模具200加以移除。在基板170(包含被安裝在基板170之上的元件)之上的密封劑210係形成一片或墊的被封入的裝置。儘管只有一裝置被展示在圖3g中，但是通常許多裝置都會一起被形成在一共同的基板170上，並且在單一成型步驟中加以封入。密封劑210係完全地覆蓋半導體晶粒124以及離散的裝置184。在裝置區域171之外的基板170的部分係從該密封劑露出，因為模具200係在成型期間壓抵該基板，以將該基板保持在適當的地方。
導電凸塊186係從密封劑210的一底表面露出並且延伸在其之上，因為該些導電凸塊在密封劑210沉積時係部分內嵌在模具膜202之內。離散的裝置184a-184b係包含在底表面177之上的一比導電凸塊186矮的高度，因而並未在成型期間內嵌在模具膜202中。因此，密封劑210係完全地覆蓋離散的裝置184，但是並未完全地覆蓋導電凸塊186。在其它實施例中，除了導電凸塊186之外，一被安裝在表面177之上的裝置，不論是否為一半導體晶粒124、離散的裝置184、或是其它構件，都可以內嵌在模具膜202中，因而在該成型的面板從模具200被移除時，將會從密封劑210露出。在一實施例中，為了較容易從密封劑210及導電凸塊186移除，模具膜202是一熱或UV釋放膜，以防該模具膜黏到該裝置。
在圖3h中，從模具200被移除的面板係利用鋸刀或雷射切割工具216，穿過基板170及密封劑210而被單粒化以分開該些個別的裝置區域171成為雙側成型SIP封裝220。單粒化係導致密封劑210的側表面與基板170的側表面共平面的。
圖4是描繪一被安裝到PCB 52之上的經單粒化的雙側成型SIP封裝220。導電凸塊186係被回焊到導電線路54的接觸墊之上，以機械式及電性連接封裝220至PCB 52。導電線路54係根據任何所要的電性功能來電連接在封裝220中的電性構件至電子裝置50的其它構件。半導體晶粒124及離散的裝置184係透過導電層176、導電貫孔174、以及導電凸塊186來電連接至PCB 52以及彼此。
在形成SIP封裝220中所採用的雙側成型方法只需要單一成型步驟，其係節省設置一具有兩個分開的成型步驟的製造線所需的時間及資本的支出。從一技術的觀點來看，由於降低的基板帶的翹曲以及循環時間，單一成型步驟也是較直接的。在基板170的邊緣，靠近模具200的側壁、或是在該基板的切割道中的開口180係維持在裝置區域171之內的設計彈性。
圖5係描繪SIP封裝230。SIP封裝230係類似於圖4中的SIP封裝220，但是其中導電凸塊186係被導電柱232所取代。在一實施例中，導電柱232係藉由在底表面177之上沉積一遮罩，穿過該遮罩來在其中該些導電柱是所要的位置形成開口以露出導電層176，並且沉積一種導電材料到該些遮罩開口中來加以形成。在其它實施例中，導電柱232係利用其它加成、半加成、或是減成的金屬沉積技術來加以形成。導電柱232係由Al、Cu、Sn、Ni、Au、Ag、其之組合、或是其它適當的導電材料所形成的。
具有所形成的導電柱232、以及被設置在該基板上的半導體晶粒124及離散的裝置184的基板170係被設置到模具200中，其中該些導電柱的末端係被嵌入到模具膜202之中。模具膜202係阻擋密封劑210完全地覆蓋導電柱232，因而該些導電柱係在從模具200移除之後從該密封劑延伸出。SIP封裝230可被安裝到PCB 52，並且利用焊料膏或其它適當的機構來電連接至線路54。相對於導電凸塊186，導電柱232係增加在基板170與PCB 52之間的互連的可能的間距。導電凸塊168係被回焊，並且必須被保持相隔一最小的距離，以降低兩個導電凸塊回焊在一起並且短路的可能性。導電柱232係以一種可以是在一較緊密的間距下，而不顯著地增加短路的風險之方式來加以形成的。
圖6a-6b係描繪在無膜的協助下形成一雙側成型SIP封裝。在圖6a中，具有導電凸塊186、半導體晶粒124、以及離散的裝置184的基板170係在無模具膜202之下，被設置在模具200中。密封劑210係如同在圖3f中地被注入到模具200之中，但是其係完全地覆蓋導電凸塊186，而無部分地保護該些導電凸塊以避開該密封劑的模具膜202。
在圖6b中，具有密封劑210的基板170係從模具200被移除。一利用研磨機240、或是其它適當的化學或機械式研磨或蝕刻製程的背面研磨操作係被用來降低密封劑210的一厚度，並且露出導電凸塊186。導電柱232或是其它類型的互連結構係在其它實施例中被使用，並且藉由平坦化而被露出。在圖6b中的平坦化係產生密封劑210的一底表面，其係藉由移除該些導電凸塊及密封劑的部分至在基板170之上的大致相同的高度來與導電凸塊186的一表面共平面的。一具有露出的導電凸塊186的經平坦化的封裝可被設置在PCB 52之上，並且該些導電凸塊係被回焊到線路54之上。在某些實施例中，一額外的量的焊料膏係被印刷到線路54之上，並且和導電凸塊186一起被回焊。
圖7a-7c係描繪利用一引線架250的一實施例。引線架250是一種固體的導電材料，例如是Au、Cu、Ag、Al、其之合金、或是其它適當的導電材料，並且包含一底座以及複數個從該底座延伸的導電柱252。導電柱252係被形成在引線架250上的其中外部的互連至基板170是所要的位置處。引線架250的底座可以是一連續地延伸橫跨每一個裝置區域171的整體的平板、或是可包含開口，而在該底座中有剛好足夠的材料以實際彼此連接每一個導電柱252。一半導體晶粒124c係被設置在底表面177上，而不是在先前實施例中的離散的裝置184a-184b。然而，在所揭露的實施例的任一個中，半導體晶粒124、離散的裝置184、或是其它所要的構件的任意組合都可被利用在底表面177及頂表面179上。
引線架250係被設置在基板170之上，其中導電柱252係被定向朝向該基板並且與導電層176的接觸墊對準。焊料膏254係被印刷、或是用其它方式而被設置在導電柱252或導電層176上，並且被回焊以電性及機械式地耦接引線架250至基板170。基板170係被翻轉，以將任意所要的構件安裝至頂表面179。
在圖7b中，具有引線架250的基板170係被設置在模具200中。密封劑210係透過模具200的開口200c以及基板170的開口180而被注入在底表面177及頂表面179兩者之上。密封劑210係包圍引線架250的導電柱252。引線架250的底座係由於接觸到選配的模具膜256而維持從密封劑210露出。在其它實施例中，引線架250係直接接觸底板200a以保持從該密封劑露出、或是密封劑可被容許以完全地包圍該引線架底座。
在圖7c中，SIP封裝258係藉由從模具200移除該面板來加以完成。一類似於圖6b中所示的背面研磨操作係被用來移除引線架250的底座以及密封劑210的一部分。引線架250的底座的移除係電性隔離導電柱252，並且從密封劑210露出該些導電柱以用於後續的連接至PCB 52。在某些實施例中，一焊料膏或其它的導電材料係在平坦化之後被印刷在導電柱252上，以助於做成至PCB 52的連接。從模具200被移除的面板係利用一雷射切割工具、鋸刀、或是其它適當的設備而被單粒化，以將一起被形成的裝置彼此分開。
圖8a-8d係描繪用於在基板170中的開口180不同的配置。在圖8a-8d中的基板170係總共包含十二個裝置區域171，以一次形成十二個SIP裝置。裝置區域171係被分開成為三個行259a-259c，其中每一行有四個裝置。在圖8a中，在該密封劑於該成型步驟期間被注入時，單一穿過基板170的開口180係容許密封劑210能夠從模具200的頂端流動至底部、或者反之亦然。開口180係位在接近模具200的注入點之處，以促進密封劑較容易通過該開口的流動。單一開口180係延伸橫跨裝置區域171的每一行259，以容許密封劑能夠穿過基板170而流動橫跨該基板的一整個寬度。
圖8b係描繪具有三個個別的開口180b的基板170，該些開口180b係在該基板的一相鄰其中密封劑將會被注入到模具200之中的邊緣處，穿過該基板來加以形成。針對於每一行259係形成一個別的開口180b。圖8c係描繪具有開口180b、以及被形成在相鄰的裝置區域171之間的切割道中的額外的開口180c的基板170。開口180c係容許密封劑210能夠在遍及該基板的長度及寬度的各個點之處，從基板170的頂端側流動至底部側、或是反之亦然。當密封劑210透過開口180b的流動速率係不足以大致相同的速率來完全填入底板200a及頂板200b時，開口180c係特別有助益的。在圖8c中的開口180c係被形成在一共同的行259中的每一對相鄰的裝置區域171之間。在其它實施例中，某些對相鄰的裝置區域171係具有開口180c，而某些對則無。
圖8d係描繪其中開口180c是只有每隔一個裝置區域171才出現一個的一實施例。此外，相鄰的行259係具有偏置的開口180c的圖案，以形成一棋盤圖案。在其它實施例中，任意所要的開口180c的圖案係被使用。圖8d亦增加被形成在相鄰的行259之間的切割道中的開口180d。同樣地，開口180a、180b、180c及180d的任意所要的組合都可被利用。開口180一般係被形成在切割道之內、或是在基板170的邊緣處。在裝置區域171中的開口180可能會對於被形成在基板170上的裝置造成設計的限制，儘管若為所要的話，在此項技術中具有普通技能者仍然可以在裝置區域171之內形成開口180。
圖9係描繪在模具260中的引線架170，以作為模具200之一替代的模具設計。模具260係包含一底板260a以及頂板260b。在引線架170的行259之間，底板260a係包含延伸部262，並且頂板260b係包含延伸部264。延伸部262及264係接觸在裝置區域171之間的基板170，以提供機械式支撐給該基板。延伸部262及264係提供額外的支撐給基板170，降低該基板的翹曲。在成型期間的較平坦的基板170係促進密封劑210在基板170的兩側之上橫跨每一個裝置區域171的均勻的厚度。
在一實施例中，延伸部262及264係連續地延伸每一行259的長度。延伸部262及264係將每一行259的裝置區域171分開成為一隔離室266a-266c。模具260係針對於每一行259包含一開口，以立刻注入密封劑210到每一行中。即使該密封劑係通過開口180自由地流動在底板260a及頂板260b之間，但是密封劑210並不流動跨過在行259之間藉由延伸部262及264所建立的邊界。在其它實施例中，延伸部262及264係被提供作為柱或是其它結構，其並不完全地分開相鄰的行259。密封劑210接著將會流動在相鄰的行259之間。
裝置的形成係類似於圖3a‑3h來進行，但是其中增加了延伸部262及264來支撐基板170。在某些實施例中，頂板200b係與底板260a一起被使用。底板200b的延伸部262係支撐基板170免於下垂，而不需要延伸部264。
圖10a-10b係描繪一雙側的膜輔助的成型實施例，其可以應用到以上或以下的SIP封裝的任一個。除了部分地嵌入導電凸塊186在模具膜202中之外，模具膜268係被設置在上方的板200b或260b中。當基板170被設置在模具260中時，半導體晶粒124係接觸模具膜268。因此，密封劑210係流入模具260之中，但是並不覆蓋半導體晶粒124的背表面128。
圖10b係描繪在雙側膜輔助的成型之後的一SIP封裝。導電凸塊186係在該封裝的底部上露出。半導體晶粒124係在該封裝的頂端露出。露出半導體晶粒124係容許一散熱片能夠在封裝之後被施加至該封裝，其係直接接觸該半導體晶粒。在其它實施例中，在基板170的任何表面上的任何吾人想要讓其從密封劑210露出的特點都可以在該成型製程期間被設置成接觸模具膜202或是模具膜268。
圖11a-11b係描繪在半導體晶粒124與基板170之間具有模具底膠填充(MUF)269的一實施例。MUF 269可以在導電凸塊134之後被施加至半導體晶粒124、或是可被施加至基板170。在導電凸塊134周圍具有與密封劑210分開的MUF 269係有助於減少在該些導電凸塊之間的絕緣材料中的空孔。尤其是在更細間隔的導電凸塊134下，使得密封劑210完全地填入在該些導電凸塊之間的半導體晶粒124之下可能會呈現挑戰性。MUF 269是較可能完全地填入在半導體晶粒124與基板170之間的空間，而不留下空孔。
圖11b係描繪一具有使用除了密封劑210以外的MUF 269的SIP封裝。密封劑210係覆蓋半導體晶粒124的側表面及背表面，而MUF 269係覆蓋主動表面130並且延伸至基板170。以上或以下的實施例的任一個都可以在半導體晶粒124與基板170之間增加MUF 269之下加以形成。
圖12a-12b係描繪利用在基板170的底表面177上的指狀部成型來形成一裝置。頂板200b或是頂板260b係如同先前的實施例地被使用。然而，一不同的底板270係被設置。底板270係包含跨坐相鄰的裝置區域171的平台272，並且指狀部凹穴274係沿著每一行259延伸。基板170係具有被安裝在下表面177及頂表面179之上的任意所要的離散的裝置184以及半導體晶粒124，但是並不具有導電凸塊186。
當基板170被設置在底板270上時，任何在底表面177上的離散的裝置184以及半導體晶粒124都位於指狀部凹穴274之內，使得底表面177係接觸該底板的平台272。當密封劑210被注入到該模具之中時，頂板200b的凹穴200d以及底板270的指狀部凹穴274係被填入密封劑，以覆蓋離散的裝置184以及半導體晶粒124。在底表面177上的導電層176的將被使用於外部的互連至最終的封裝的部分係接觸平台272。導電層176接觸平台272的部分在成型之後係保持沒有密封劑210、或是從密封劑210露出。接觸基板170的平台272係阻擋密封劑流動在導電層176的將被使用於外部的互連的部分之上。
在圖12b中，面板278係從該模具被移除，此係留下底表面177的一其中平台272原本接觸基板170之處的互連區域276被露出。導電凸塊284係以一種類似在先前的實施例中的導電凸塊186的方式而被形成在導電層176上的露出的互連區域中。在凸塊接合之後，該面板係利用鋸刀或雷射切割工具286而被單粒化成為個別的指狀部成型SIP封裝。導電凸塊284可以進一步延伸在基板170的表面177之上而超出密封劑210的底部部分280、或者可以是較短的。例如是導電柱、柱形凸塊、或引線接合的其它互連結構係依照一給定的情況所適合的來加以使用，以取代導電凸塊284。
圖13a-13f係描繪基板170的指狀部成型底表面177，其中增加了屏蔽層。圖13a係描繪在從圖12a中的頂板200b及底板270被移除之後的面板278。附帶一提的是，圖13a係以平面圖展示面板278在導電凸塊284被設置在互連區域276中之前並且在該些裝置於圖12b中被單粒化之前看起來像是如何。在圖13b中，一鋸刀或是雷射切割工具288係被用來穿過指狀部成型密封劑280以切半面板278。在圖13b中的切半的單粒化係延伸通過垂直於裝置行259的切割道，以將指狀部成型密封劑280分開成為用於每一個別的裝置區域171的一個別的密封劑部分280a。該切半的單粒化係移除在切割道290之內的指狀部成型密封劑280的一部分，但是並不完全地穿過面板278來單粒化。藉由鋸288的切半的深度可以是和完全地穿過基板170並且部分地穿過密封劑210的頂端部分282一樣深、或是和只有部分地穿過指狀部成型密封劑280一樣淺。技術上，該切割可以是完全地穿過面板278，但是只執行一部分的切割係具有密封劑210部分地保留以將每一個單元保持在一起的益處。
在圖13c中，一帶296或是其它遮罩係被施加在該些互連區域276之內的相鄰的指狀部成型部分280a之間。一屏蔽層300係利用例如是CVD、PVD、或無電的電鍍的適當的金屬沉積技術而被施加在指狀部成型部分280之上。帶296係阻擋該沉積的金屬免於粘附在互連區域276中。屏蔽層300係覆蓋在每一個裝置區域171之上的每一個指狀部成型密封劑部分280的頂表面以及每一個側表面，因為在圖13b中的切半的單粒化係露出每一個單元的最終的兩個側表面。屏蔽層300係在被安裝於底表面177之上的離散的裝置184以及任何其它的構件之上形成一蓋。在某些實施例中，一蓋係被預先形成並且置放在每一個指狀部成型密封劑部分280a之上。該些預先形成的蓋可以藉由被壓合在密封劑部分280a之上、藉由一黏著劑、或是藉由其它適當的手段而被保持在上面。
在圖13d中，帶296係藉由機械式剝離、UV釋放、熱釋放、化學蝕刻、或是其它適合用於所使用的類型的帶的手段來加以移除。帶296的移除亦移除屏蔽層300在互連區域276中的部分，以露出導電層176的部分。導電凸塊284係接著如同在圖12b中地加以形成。
在圖13e中，面板278係被翻轉並且設置在載體310上，其中基板170的頂表面179係被定向成背對該載體。鋸刀或雷射切割工具314係被用來完全地將每一個SIP封裝316彼此單粒化。在圖13e中的單粒化係露出頂端密封劑部分282的所有的側表面。一般而言，矩形裝置係被形成，因而頂端密封劑部分282係具有四個側邊，但是任意數目及形狀的側邊都可被利用於下方的密封劑部分280。黏著或介面層312係在單粒化之後將裝置316保持在適當的地方，以用於後續的處理。
在圖13f中，頂端屏蔽層320係以一種類似底部屏蔽層300的方式而被形成在頂端密封劑部分282之上。頂端屏蔽層320係延伸在頂端密封劑部分282的頂表面以及側表面之上，以提供電磁屏蔽給被設置在基板170的頂表面179上的半導體晶粒124以及其它的構件。頂端屏蔽層320以及底部屏蔽層300係一起提供全面的電磁屏蔽給SIP封裝316。
圖14係描繪一如同在圖13a-13f中所示地形成的SIP封裝326，但是具有另一可能的構件配置。SIP封裝326係在單一成型步驟中利用一種用於雙側成型的簡單且經濟的製程流程來加以製造，同時亦提供電磁屏蔽給在該裝置的兩側上的構件。
儘管本發明的一或多個實施例已經詳細地被描述，但是本領域技術人員將會體認到可以對於那些實施例做成修改及調適，而不脫離如同在以下的申請專利範圍中闡述的本發明的範疇。
50:電子裝置 52:PCB 54:信號線路 56:接合導線封裝 58:覆晶 60:球格陣列(BGA) 62:凸塊晶片載體(BCC) 66:平台柵格陣列(LGA) 68:多晶片的模組(MCM) 70:四邊扁平無引腳封裝(QFN) 72:四邊扁平封裝 74:嵌入式晶圓層級球格陣列(eWLB) 76:晶圓級晶片尺寸封裝(WLCSP) 120:半導體晶圓 122:基底基板材料 124、124a、124b、124c:半導體晶粒 126:切割道 128:背表面(非主動表面) 130:主動表面 132:導電層(接觸墊) 134:導電凸塊 136:測試探針頭 138:探針 140:電腦測試系統 142:鋸刀(雷射切割工具) 160:載體 162:介面層(雙面帶) 170:封裝基板(引線架) 171:裝置區域 172:絕緣層(鈍化層) 174:導電貫孔 176:導電層(重分佈層) 177:底表面 179:頂表面 180、180a、180b、180c、180d:開口 182:焊料膏 184、184a、184b、184c:離散的裝置 186:導電凸塊 190:載體 192:介面層 200:模具 200a:底板 200b:頂板 200c:入口埠 200d:模具凹穴 202:模具膜 210:密封劑 212a:路徑 212b:路徑 216:鋸刀(雷射切割工具) 220:雙側成型SIP封裝 230:SIP封裝 232:導電柱 240:研磨機 250:引線架 252:導電柱 254:焊料膏 256:模具膜 258:SIP封裝 259、259a-259c:行 260:模具 260a:底板 260b:頂板 262:延伸部 264:延伸部 266a-266c:隔離室 268:模具膜 269:模具底膠填充(MUF) 270:底板 272:平台 274:指狀部凹穴 276:互連區域 278:面板 280:指狀部成型密封劑 280a:密封劑部分(指狀部成型部分) 282:頂端部分 284:導電凸塊 286:鋸刀(雷射切割工具) 288:鋸刀(雷射切割工具) 290:切割道 296:帶 300:屏蔽層 310:載體 312:黏著層(介面層) 314:鋸刀(雷射切割工具) 316:SIP封裝 320:頂端屏蔽層 326 SIP:封裝
[圖1]係描繪一印刷電路板(PCB)，其中各種類型的封裝係被安裝到該PCB的一表面； [圖2a-2e]係描繪一半導體晶圓，其中複數個半導體晶粒係藉由切割道來加以分開的； [圖3a-3h]係描繪一種在單一成型步驟中形成一具有雙側成型的系統級封裝(SIP)裝置的製程； [圖4]係描繪被安裝到一PCB的一具有雙側成型的SIP裝置； [圖5]係描繪一利用導電柱的具有雙側成型的SIP裝置； [圖6a-6b]係描繪雙側成型以及接著背面研磨以露出互連結構； [圖7a-7c]係描繪利用一引線架的雙側成型； [圖8a-8d]係描繪PCB，其係具有開口以容許密封劑能夠在一模具之內流動在該PCB的頂端側與底部側之間； [圖9]係描繪一模具，其係具有內部的壁或柱以支撐一SIP基板； [圖10a-10b]係描繪雙側的膜輔助的成型； [圖11a-11b]係描繪在該雙側成型製程中利用一模具底膠填充； [圖12a-12b]係描繪形成具有底側的指狀部成型之雙側成型； [圖13a-13f]係描繪具有底側的指狀部成型與增加頂端及底部屏蔽層之雙側成型；以及 [圖14]係描繪另一具有雙側成型的SIP裝置，其係具有底側的指狀部成型以及屏蔽層。
124a、124b:半導體晶粒
132:接觸墊
172:絕緣層(鈍化層)
174:導電貫孔
176:導電層(重分佈層)
177:底表面
179:頂表面
180:開口
182:焊料膏
184a、184b、184c:離散的裝置
186:導電凸塊
200a:底板
200b:頂板
200c:入口埠
200d:模具凹穴
202:模具膜
210:密封劑
212a:路徑
212b:路徑

Claims (15)

  1. 一種製造半導體裝置之方法，包括： 提供包括多個裝置區域的基板；以及 在所述多個裝置區域的覆蓋區之外形成穿過所述基板的第一開口。
  2. 如請求項1的方法，其中所述第一開口的長度大於所述多個裝置區域的組合長度。
  3. 如請求項1的方法，進一步包括在所述基板的邊緣形成所述第一開口。
  4. 如請求項3的方法，進一步包括在所述多個裝置區域中的兩個裝置區域之間形成第二開口。
  5. 如請求項1的方法，進一步包括在所述多個裝置區域中的兩個裝置區域之間形成所述第一開口。
  6. 如請求項1的方法，進一步包括設置第一電子構件在所述多個裝置區域的第一裝置區域內的所述基板的第一表面上。
  7. 如請求項6的方法，進一步包括設置第二電子構件在所述多個裝置區域的所述第一裝置區域內的所述基板的第二表面上。
  8. 一種半導體裝置，包括： 基板，包括多個裝置區域；以及 第一開口，在所述基板的邊緣附近形成而穿過所述基板。
  9. 如請求項8的半導體裝置，其中所述多個裝置區域被編組為多個行，且所述第一開口延伸橫跨所述多個行中的每一行。
  10. 如請求項8的半導體裝置，進一步包括形成在所述基板的邊緣的多個第一開口。
  11. 如請求項8的半導體裝置，進一步包括形成在所述多個裝置區域中的兩個裝置區域之間的第二開口。
  12. 一種半導體裝置，包括： 基板，包括多個裝置區域；以及 開口，在所述多個裝置區域的覆蓋區之外形成而穿過所述基板。
  13. 如請求項12的半導體裝置，其中所述開口形成在所述多個裝置區域中的兩個裝置區域之間。
  14. 如請求項12的半導體裝置，進一步包括第一電子構件，所述第一電子構件設置在所述多個裝置區域的第一裝置區域內的所述基板的第一表面上。
  15. 如請求項14的半導體裝置，進一步包括第二電子構件，所述第二電子構件設置在所述多個裝置區域的所述第一裝置區域內的所述基板的第二表面上。
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