TW201810380A - 貼合式soi晶圓的製造方法 - Google Patents

貼合式soi晶圓的製造方法 Download PDF

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Publication number
TW201810380A
TW201810380A TW106115681A TW106115681A TW201810380A TW 201810380 A TW201810380 A TW 201810380A TW 106115681 A TW106115681 A TW 106115681A TW 106115681 A TW106115681 A TW 106115681A TW 201810380 A TW201810380 A TW 201810380A
Authority
TW
Taiwan
Prior art keywords
wafer
bonded
polycrystalline germanium
germanium layer
layer
Prior art date
Application number
TW106115681A
Other languages
English (en)
Chinese (zh)
Inventor
Taishi Wakabayashi
Kenji Meguro
Miho NIITANI
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of TW201810380A publication Critical patent/TW201810380A/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
TW106115681A 2016-06-23 2017-05-12 貼合式soi晶圓的製造方法 TW201810380A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016124475A JP6498635B2 (ja) 2016-06-23 2016-06-23 貼り合わせｓｏｉウェーハの製造方法

Publications (1)

Publication Number Publication Date
TW201810380A true TW201810380A (zh) 2018-03-16

Family

ID=60783453

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106115681A TW201810380A (zh) 2016-06-23 2017-05-12 貼合式soi晶圓的製造方法

Country Status (4)

Country Link
JP (1) JP6498635B2 (ja)
CN (1) CN109075028B (ja)
TW (1) TW201810380A (ja)
WO (1) WO2017221563A1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021190660A (ja) * 2020-06-04 2021-12-13 株式会社Sumco 貼り合わせウェーハ用の支持基板
JP2022070034A (ja) * 2020-10-26 2022-05-12 株式会社Sumco 貼り合わせウェーハ用の支持基板の製造方法、および貼り合わせウェーハ用の支持基板
JP2023157404A (ja) * 2022-04-15 2023-10-26 信越半導体株式会社 ポリシリコンウェーハの製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4559010A (en) * 1984-05-01 1985-12-17 Toray Industries, Inc. Apparatus for producing oxidized filaments
US7273818B2 (en) * 2003-10-20 2007-09-25 Tokyo Electron Limited Film formation method and apparatus for semiconductor process
JP2009016393A (ja) * 2007-06-29 2009-01-22 Toshiba Corp 半導体基板、半導体装置、及び半導体基板の製造方法
JP5453780B2 (ja) * 2008-11-20 2014-03-26 三菱化学株式会社 窒化物半導体
FR2953640B1 (fr) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
CN102485974B (zh) * 2010-12-03 2014-10-15 天威新能源控股有限公司 一种采用cvd反应直接生长单晶硅的方法
FR2973158B1 (fr) * 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
JP2013055231A (ja) * 2011-09-05 2013-03-21 Shin Etsu Handotai Co Ltd エピタキシャルウェーハの製造方法
JP6100200B2 (ja) * 2014-04-24 2017-03-22 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP2015228432A (ja) * 2014-06-02 2015-12-17 信越半導体株式会社 Ｓｏｉウェーハの製造方法及び貼り合わせｓｏｉウェーハ

Also Published As

Publication number Publication date
JP2017228686A (ja) 2017-12-28
WO2017221563A1 (ja) 2017-12-28
CN109075028B (zh) 2023-08-15
JP6498635B2 (ja) 2019-04-10
CN109075028A (zh) 2018-12-21

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