TW201810380A - Bonded SOI wafer manufacturing method - Google Patents

Bonded SOI wafer manufacturing method Download PDF

Info

Publication number
TW201810380A
TW201810380A TW106115681A TW106115681A TW201810380A TW 201810380 A TW201810380 A TW 201810380A TW 106115681 A TW106115681 A TW 106115681A TW 106115681 A TW106115681 A TW 106115681A TW 201810380 A TW201810380 A TW 201810380A
Authority
TW
Taiwan
Prior art keywords
wafer
bonded
polycrystalline germanium
germanium layer
layer
Prior art date
Application number
TW106115681A
Other languages
Chinese (zh)
Inventor
Taishi Wakabayashi
Kenji Meguro
Miho NIITANI
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of TW201810380A publication Critical patent/TW201810380A/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The present invention comprises: a step for depositing a polycrystalline silicon layer on a base wafer; a step for obtaining a polished surface by polishing the polycrystalline silicon layer; a step for forming an insulating film on a bond wafer; a step for bonding the polished surface of the polycrystalline silicon layer and the bond wafer via the insulating film; and a step for thinning the bond wafer, wherein a silicon single crystal wafer of at least 100 [Omega]·cm is used as the base wafer, the step for depositing the polycrystalline silicon layer further includes a step for forming, in advance, an oxide film on a surface of the base wafer on which the polycrystalline silicon layer is to be deposited, the polycrystalline silicon layer is deposited by supplying, after being heated to a predetermined temperature of at least 1,000 DEG C, a source gas for the polycrystalline silicon layer at the predetermined temperature, and furthermore, even during heating to the predetermined temperature, the source gas for the polycrystalline silicon layer is supplied. Thus, provided is a bonded SOI wafer manufacturing method in which single crystallization of the polycrystalline silicon layer can be inhibited while high productivity is maintained.

Description

貼合式SOI晶圓的製造方法Method for manufacturing a bonded SOI wafer

本發明係關於一種貼合式SOI晶圓的製造方法。The present invention relates to a method of fabricating a conformable SOI wafer.

作為對應射頻(Radio Frequency: RF)裝置的SOI晶圓,一直是以將基底晶圓的電阻率為高電阻化的方式解決。但是,為了對應更進一步的高速化而逐漸變得有對應更射頻的必要,僅使用習知的高電阻晶圓已經逐漸變得無法解決。As an SOI wafer corresponding to a radio frequency (RF) device, it has been solved in such a manner that the resistivity of the base wafer is increased. However, in order to gradually become more necessary for a higher radio frequency in response to further increase in speed, it has become increasingly impossible to use only conventional high-resistance wafers.

於是,作為對策提出有於SOI晶圓的埋入氧化膜層(BOX層)緊接下方,加入具有使產生的載子消滅的效果的層(載體捕陷層),而變得有必要將用以使高電阻晶圓中所產生的載子再結合的高電阻的多晶矽層形成於基底晶圓上。Then, as a countermeasure, it is proposed that a layer (carrier trap layer) having an effect of destroying the generated carrier is added immediately below the buried oxide film layer (BOX layer) of the SOI wafer, and it is necessary to use it. A high-resistance polysilicon layer in which the carriers generated in the high-resistance wafer are recombined is formed on the base wafer.

專利文獻1中,記載有於BOX層及基底晶圓的交界面形成作為載子捕陷層的多晶矽層或非晶矽層。Patent Document 1 describes that a polycrystalline germanium layer or an amorphous germanium layer as a carrier trap layer is formed at the interface between the BOX layer and the base wafer.

另一方面,專利文獻2中,也記載有於BOX層及基底晶圓的交界面,形成作為載子捕陷層的多結晶層,更進一步,限制多晶矽層形成後的熱處理溫度以防止多晶矽層的再結晶化。On the other hand, Patent Document 2 also discloses that a polycrystalline layer as a carrier trap layer is formed at the interface between the BOX layer and the base wafer, and further, the heat treatment temperature after the formation of the polysilicon layer is restricted to prevent the polycrystalline layer. Recrystallization.

又,專利文獻3中,雖未記載有形成作為載子捕陷層的多晶矽層或非晶矽層,但記載有藉由將與接合晶圓貼合側的基底晶圓表面的表面粗糙度增大,得到與載子捕陷層相同的效果。 〔先前技術文獻〕 〔專利文獻〕Further, in Patent Document 3, although a polycrystalline germanium layer or an amorphous germanium layer as a carrier trap layer is not described, it is described that the surface roughness of the surface of the base wafer bonded to the bonded wafer side is increased. Large, get the same effect as the carrier trap layer. [Prior Technical Literature] [Patent Literature]

〔專利文獻1〕日本特表2007-507093號公報 〔專利文獻2〕日本特表2013-513234號公報 〔專利文獻3〕日本特開2010-278160號公報 〔專利文獻4〕日本特開2015-211061號公報[Patent Document 1] Japanese Patent Publication No. 2007-507093 (Patent Document 2) Japanese Patent Publication No. 2013-513234 (Patent Document 3) Japanese Laid-Open Patent Publication No. 2010-278160 (Patent Document 4) JP-A-2015-211061 Bulletin

〔發明欲解決課題〕 但是,若將於基底晶圓的表面成長多晶矽層之際的成長溫度予以高溫,則會有增進多晶矽層的單晶化、失去作為載子捕陷層的功能、使射頻的特性劣化的情況。又,雖然以降低多晶矽層的形成溫度得以抑制多晶矽層的單晶化,但是會有成長速度下降、生產率惡化的問題。[Explanation of the Invention] However, if the growth temperature of the polycrystalline germanium layer is raised to a high temperature on the surface of the base wafer, the polycrystalline germanium layer is single-crystallized, and the function as a carrier trap layer is lost. The case where the characteristics are degraded. Further, although the single crystal of the polycrystalline germanium layer is suppressed by lowering the formation temperature of the polycrystalline germanium layer, there is a problem that the growth rate is lowered and the productivity is deteriorated.

在此,專利文獻4中,提出有製造貼合式SOI晶圓的方法,包含將多晶矽層的堆積以1010℃以下的第一溫度進行之第一成長,以及以較第一溫度更高溫的第二溫度進行較第一成長更厚的堆積。此製造方法,得以防止發生多晶矽層的單晶化,得以維持作為載子捕陷層的效果。但是,若堆積工程中進行如此低溫堆積及高溫堆積的二階段之堆積,則不可避免生產率低落。Here, Patent Document 4 proposes a method of manufacturing a bonded SOI wafer including a first growth in which a polycrystalline germanium layer is deposited at a first temperature of 1010 ° C or lower, and a temperature higher than a first temperature. The second temperature is deposited thicker than the first growth. This manufacturing method can prevent the occurrence of single crystallization of the polycrystalline germanium layer and maintain the effect as a carrier trap layer. However, if the two-stage accumulation of such low-temperature deposition and high-temperature deposition is carried out in the stacking process, productivity is inevitably lowered.

本發明,鑑於前述狀況,目的在於提供一種得以保持高生產率並同時抑制多晶矽層的單晶化之貼合式SOI晶圓的製造方法。 〔解決問題之技術手段〕The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for producing a bonded SOI wafer which can maintain high productivity while suppressing single crystal formation of a polysilicon layer. [Technical means to solve the problem]

為解決前述課題,本發明提供一種貼合式SOI晶圓之製造方法,將皆為矽單晶所構成之接合晶圓及基底晶圓透過絕緣膜予以貼合而製造貼合式SOI晶圓,該製造方法包含下列步驟:於該基底晶圓的貼合面側堆積多晶矽層;研磨該多晶矽層的表面而得到研磨面;於該接合晶圓的貼合面形成該絕緣膜;透過該絕緣膜將該基底晶圓的該多晶矽層的該研磨面與該接合晶圓貼合;以及將經貼合之該接合晶圓予以薄膜化而形成SOI層,其中,使用電阻率100Ω‧cm以上之單晶矽晶圓作為該基底晶圓,堆積該多晶矽層之步驟,更包含於該基底晶圓的堆積該多晶矽層的表面預先形成氧化膜之階段,該多晶矽層的堆積係藉由升溫至1000℃以上的規定溫度為止,且在該規定溫度下供給該多晶矽層之原料氣體而進行,更進一步在升溫至該規定溫度為止之際也供給該多晶矽層之原料氣體。In order to solve the above problems, the present invention provides a method for manufacturing a bonded SOI wafer, in which a bonded wafer and a base wafer each composed of a single crystal are bonded through an insulating film to produce a bonded SOI wafer. The manufacturing method includes the steps of: depositing a polysilicon layer on a bonding surface side of the base wafer; polishing a surface of the polysilicon layer to obtain a polishing surface; forming the insulating film on a bonding surface of the bonding wafer; and transmitting the insulating film through the bonding film Bonding the polished surface of the polysilicon layer of the base wafer to the bonded wafer; and thinning the bonded bonded wafer to form an SOI layer, wherein a single resistivity of 100 Ω ‧ cm or more is used As a step of depositing the polysilicon layer on the base wafer, the wafer wafer is further included in a stage in which an oxide film is formed on the surface of the base wafer on which the polysilicon layer is deposited, and the polycrystalline germanium layer is heated to 1000 ° C. The raw material gas of the polycrystalline germanium layer is supplied at the predetermined temperature up to the predetermined temperature, and the raw material gas of the polycrystalline germanium layer is also supplied when the temperature is raised to the predetermined temperature. .

若為此種貼合式SOI晶圓的製造方法,由於以自低溫升溫至高溫為止之升溫階段的時間點,放入多晶矽層之原料氣體而形成多晶矽層的基礎,並以高溫成長多晶矽層,故得以製造兼顧抑制多晶矽層的單晶化及高生產率的貼合式SOI晶圓。In the method of manufacturing such a bonded SOI wafer, a polycrystalline germanium layer is formed by placing a material gas of a polycrystalline germanium layer at a temperature rising stage from a low temperature to a high temperature, and a polycrystalline germanium layer is grown at a high temperature. Therefore, it is possible to manufacture a bonded SOI wafer in which single crystallization and high productivity of the polycrystalline germanium layer are suppressed.

此時,該氧化膜藉由濕洗淨形成為佳。At this time, it is preferable that the oxide film is formed by wet cleaning.

由於使氧化膜介入於基底晶圓與多晶矽層之間,可能會對RF裝置的特性有影響,因此形成氧化膜的厚度以薄為佳,例如作為10nm以下的厚度為佳。作為如此厚度的氧化膜形成方法,能舉出濕洗淨為最簡便的方法。Since the oxide film is interposed between the base wafer and the polysilicon layer, the characteristics of the RF device may be affected. Therefore, the thickness of the oxide film is preferably thin, and is preferably, for example, 10 nm or less. As a method of forming an oxide film having such a thickness, wet cleaning is the easiest method.

又於此時,該規定溫度,以1150℃以下為佳。Further, at this time, the predetermined temperature is preferably 1150 ° C or lower.

若前述升溫之規定溫度為1150℃以下,則能夠降低在以高溫的堆積中多晶矽層的單晶化之可能性。When the predetermined temperature for the temperature rise is 1150 ° C or lower, the possibility of single-crystalization of the polycrystalline germanium layer at a high temperature deposition can be reduced.

又於此時,在升溫至該規定溫度為止之際中的開始該多晶矽層之原料氣體的供給的溫度以600℃~980℃的範圍內之溫度為佳。Further, at this time, the temperature at which the supply of the material gas of the polycrystalline germanium layer is started during the temperature rise to the predetermined temperature is preferably in the range of 600 ° C to 980 ° C.

在升溫至前述的該規定溫度為止之際中的開始該多晶矽層之原料氣體的供給的溫度若為980℃以下,由於升溫中氧化膜變得不易消失,因此得以抑制多晶矽層的單晶化。又,若為600℃以上,得以確保高生產率。 〔對照先前技術之功效〕When the temperature at which the supply of the material gas of the polycrystalline germanium layer is started is 980 ° C or less at the time of the temperature rise to the predetermined temperature, the oxide film is less likely to disappear during the temperature rise, so that the single crystal of the polycrystalline germanium layer is suppressed. Moreover, when it is 600 ° C or more, high productivity is ensured. [Compared with the efficacy of prior art]

本發明之貼合式SOI晶圓的製造方法中,在基底晶圓堆積多晶矽層之際,自低溫升溫至高溫為止的升溫階段的時間點以放入多晶矽層的原料氣體而形成多晶矽層的基礎,並以高溫成長多晶矽層。藉此,得以製造兼顧抑制多晶矽層的單晶化及高生產率之貼合式SOI晶圓。又,本發明之貼合式SOI晶圓的製造方法,不僅於多晶矽層的形成,亦得以應用於單晶矽層形成時的生產率提升之故,通用性為高。 【圖示簡單說明】In the method for producing a bonded SOI wafer of the present invention, when a polycrystalline germanium layer is deposited on a base wafer, a polycrystalline germanium layer is formed by placing a material gas of a polycrystalline germanium layer at a time of a temperature rising phase from a low temperature to a high temperature. And grow polycrystalline germanium layer at high temperature. Thereby, it is possible to manufacture a bonded SOI wafer in which both the single crystallization of the polycrystalline germanium layer and the high productivity are suppressed. Further, the method for producing a bonded SOI wafer of the present invention can be applied not only to the formation of a polycrystalline germanium layer but also to productivity improvement at the time of formation of a single crystal germanium layer, and has high versatility. [Simplified illustration]

第1圖係顯示本發明之貼合式SOI晶圓的製造方法的一範例的流程圖。 第2圖係顯示本發明之貼合式SOI晶圓的製造方法的一範例的示意圖。 第3圖係顯示實施例之多晶矽層的堆積條件的圖表。 第4圖係顯示比較例1之多晶矽層的堆積條件的圖表。 第5圖係顯示比較例2之多晶矽層的堆積條件的圖表。 第6圖係顯示在比較實施例及比較例1、2中的生產率(生產能力)之圖表。 第7圖係在實施例及比較例1、2中堆積多晶矽層的晶圓的剖面SEM照片。Fig. 1 is a flow chart showing an example of a method of manufacturing a bonded SOI wafer of the present invention. Fig. 2 is a schematic view showing an example of a method of manufacturing a bonded SOI wafer of the present invention. Fig. 3 is a graph showing the deposition conditions of the polycrystalline germanium layer of the examples. Fig. 4 is a graph showing the deposition conditions of the polysilicon layer of Comparative Example 1. Fig. 5 is a graph showing the deposition conditions of the polysilicon layer of Comparative Example 2. Fig. 6 is a graph showing the productivity (production capacity) in Comparative Examples and Comparative Examples 1 and 2. Fig. 7 is a cross-sectional SEM photograph of a wafer in which a polycrystalline germanium layer was deposited in Examples and Comparative Examples 1 and 2.

以下,雖然針對本發明,參考圖式並同時詳細說明,但本發明並不限定於此。Hereinafter, the present invention is described in detail with reference to the drawings, but the present invention is not limited thereto.

如前述,需要一種能夠保持高生產率並同時抑制多晶矽層的單晶化之貼合式SOI晶圓的製造方法。As described above, there is a need for a method of manufacturing a bonded SOI wafer capable of maintaining high productivity while suppressing single crystal formation of a polysilicon layer.

本發明人們,針對前述課題反覆專心研究,思考出在多晶矽層的形成時中,不使生產率惡化而可抑制多晶矽層的單晶化之貼合式SOI晶圓的製造方法。雖然習知的多晶矽層的形成方法中,以將多晶矽層的形成溫度降低,升溫至規定溫度之後才放入多晶矽層的原料氣體(矽成長氣體)而成長多晶矽層以抑制多晶矽層的單晶化,但此種方法,會有多晶矽層的成長速度下降,且生產率惡化的問題。另一方面,為了提升生產率,將多晶矽層的形成溫度予以高溫,雖然提升了多晶矽層的成長速度,卻面對產生多晶矽層的單晶化之問題。The present inventors have intensively studied the above-mentioned problems, and have considered a method of manufacturing a bonded SOI wafer in which single crystal formation of a polycrystalline germanium layer can be suppressed without deteriorating productivity in the formation of a polycrystalline germanium layer. In the conventional method for forming a polycrystalline germanium layer, the formation temperature of the polycrystalline germanium layer is lowered, and after the temperature is raised to a predetermined temperature, the raw material gas (germanium growth gas) of the polycrystalline germanium layer is introduced to grow the polycrystalline germanium layer to suppress single crystal formation of the polycrystalline germanium layer. However, in this method, there is a problem that the growth rate of the polycrystalline germanium layer is lowered and the productivity is deteriorated. On the other hand, in order to increase the productivity, the formation temperature of the polycrystalline germanium layer is raised to a high temperature, and although the growth rate of the polycrystalline germanium layer is increased, the problem of single crystal formation of the polycrystalline germanium layer is faced.

於是,本發明人們發現,以自低溫升溫至高溫為止的升溫階段之時間點,放入矽成長氣體而形成多晶矽層的底部,並以高溫成長多晶矽層,能夠實現兼顧抑制單晶化及高生產率的多晶矽層的堆積,進而完成本發明。Then, the inventors of the present invention have found that the bottom of the polycrystalline germanium layer is formed by adding a cerium growth gas at a temperature rising stage from a low temperature to a high temperature, and the polycrystalline germanium layer is grown at a high temperature, thereby achieving both suppression of single crystal formation and high productivity. The accumulation of polycrystalline germanium layers completes the present invention.

以下,參考第1圖、第2圖,並同時說明本發明之貼合式SOI晶圓的製造方法的實施型態的一範例,另外,以下雖然作為貼合式SOI晶圓的製造方法,舉例使用離子植入剝離法的製造方法而說明,但本發明不限定於此。Hereinafter, an example of an embodiment of a method for manufacturing a bonded SOI wafer of the present invention will be described with reference to FIGS. 1 and 2, and an example of a method for manufacturing a bonded SOI wafer will be described below. Although the manufacturing method of the ion implantation peeling method is demonstrated, this invention is not limited to this.

首先,準備由單晶矽所構成的接合晶圓1(參考第1圖的步驟S11、第2圖(a))。First, a bonded wafer 1 made of a single crystal germanium is prepared (refer to step S11 and Fig. 2 (a) of Fig. 1).

接著,藉由例如熱氧化或CVD等,於接合晶圓1的貼合面,形成成為埋入絶緣膜層的絶緣膜3(例如,氧化膜)(參考第1圖的步驟S12、第2圖(b))。此情況,絶緣膜3的形成,不僅於貼合面、亦可形成於接合晶圓的整體。Then, an insulating film 3 (for example, an oxide film) to be buried in the insulating film layer is formed on the bonding surface of the bonded wafer 1 by, for example, thermal oxidation or CVD (refer to step S12 and FIG. 2 of the first drawing). (b)). In this case, the formation of the insulating film 3 can be formed not only on the bonding surface but also on the entire bonding wafer.

接著,對接合晶圓1自絶緣膜3的上方藉由離子植入機,植入氫離子及稀有氣體離子中至少一個種類的氣體離子,而於接合晶圓1内形成離子植入層4(參考第1圖的步驟S13、第2圖(c))。Next, the bonding wafer 1 is implanted with an ion implantation layer 4 in the bonding wafer 1 by implanting at least one kind of gas ions of hydrogen ions and rare gas ions from the upper surface of the insulating film 3 by the ion implanter. Refer to step S13 and FIG. 2(c) of Fig. 1 .

在此,為了除去接合晶圓1的貼合面的粒子,進行貼合前的洗淨(參考第1圖的步驟S14)。Here, in order to remove the particles bonded to the bonding surface of the wafer 1, the cleaning before bonding is performed (refer to step S14 of FIG. 1).

另一方面,別於前述,準備由單晶矽所構成之基底晶圓2(參考第1圖的步驟S21、第2圖(d))。此時,準備電阻率100Ω‧cm以上的單晶矽晶圓,作為基底晶圓2。On the other hand, in addition to the above, the base wafer 2 composed of single crystal germanium is prepared (refer to step S21 and Fig. 2 (d) of Fig. 1). At this time, a single crystal germanium wafer having a specific resistance of 100 Ω ‧ cm or more is prepared as the base wafer 2 .

基底晶圓2的電阻率,若為100Ω‧cm以上則能夠合適地使用於射頻裝置製造用,而1000Ω‧cm以上為更佳、3000Ω‧cm以上為特佳。雖然電阻率的上限並無特別限定,但例如能夠為50000Ω‧cm。When the specific resistance of the base wafer 2 is 100 Ω··cm or more, it can be suitably used for the manufacture of a radio frequency device, and more preferably 1000 Ω··cm or more and more preferably 3,000 Ω··cm or more. Although the upper limit of the specific resistance is not particularly limited, it can be, for example, 50,000 Ω ‧ cm.

接著,於基底晶圓2上,形成氧化膜(基底氧化膜)5(參考第1圖的步驟S22、第2圖(e))。雖然氧化膜5的厚度並無特別限定,但由於藉由基底晶圓與多晶矽層之間介入氧化膜而可能會對RF裝置的特性有影響,因此形成氧化膜的厚度以薄為佳,例如0.3nm以上、10nm以下的厚度為佳。Next, an oxide film (base oxide film) 5 is formed on the base wafer 2 (refer to step S22 and FIG. 2(e) of FIG. 1). Although the thickness of the oxide film 5 is not particularly limited, it may affect the characteristics of the RF device by interposing an oxide film between the base wafer and the polysilicon layer, so that the thickness of the oxide film is preferably thin, for example, 0.3. The thickness of nm or more and 10 nm or less is preferable.

作為如此厚度的氧化膜的形成方法,作為最簡便的方法能舉出濕洗淨。具體而言,藉由進行使用SC1(NH4 OH與H2 O2 之混合水溶液)、SC2(HCl與H2 O2 之混合水溶液)、硫酸氧化氫水(H2 SO4 與H2 O2 之混合水溶液)、臭氧水等之洗淨,或組合這些溶液之洗淨,能夠形成厚度0.5~3nm程度均勻的氧化膜。As a method of forming an oxide film having such a thickness, wet cleaning can be mentioned as the most convenient method. Specifically, by using SC1 (a mixed aqueous solution of NH 4 OH and H 2 O 2 ), SC 2 (a mixed aqueous solution of HCl and H 2 O 2 ), and hydrogen peroxide water (H 2 SO 4 and H 2 O 2 ) The mixed aqueous solution), ozone water, or the like is washed, or a combination of these solutions is washed to form an oxide film having a thickness of 0.5 to 3 nm.

接著,使多晶矽層6堆積於氧化膜(基底氧化膜)5上(參考第1圖的步驟S23、第2圖(f))。在此,多晶矽層的堆積,藉由升溫至1000℃以上的規定溫度為止,並於規定溫度中供給多晶矽層的原料氣體而進行,更進一步,在升溫至其規定溫度為止之際中也供給多晶矽層的原料氣體。Next, the polysilicon layer 6 is deposited on the oxide film (base oxide film) 5 (refer to step S23 and FIG. 2(f) of FIG. 1). Here, the deposition of the polycrystalline germanium layer is performed by raising the temperature to a predetermined temperature of 1000 ° C or higher, supplying the material gas of the polycrystalline germanium layer at a predetermined temperature, and further supplying the polycrystalline silicon at the time of raising the temperature to a predetermined temperature. The raw material gas of the layer.

另外,本發明中,升溫至1000℃以上的規定溫度為止為必須。前述升溫之規定溫度未滿1000℃,則雖然可抑制多晶矽層的單晶化,但成長速度下降、生產率惡化。又,前述升溫之規定溫度的上限,以1150℃以下為佳。若前述升溫之規定溫度為1150℃以下,則以在升溫至前述之規定溫度為止之際導入多晶矽層的原料氣體而薄薄地堆積多晶矽層,並由於在以前述高溫之規定溫度的堆積中氧化膜變得不易消失,故能夠降低多晶矽層單晶化的可能性。Further, in the present invention, it is necessary to raise the temperature to a predetermined temperature of 1000 ° C or higher. When the predetermined temperature of the temperature rise is less than 1000 ° C, the single crystal of the polycrystalline germanium layer can be suppressed, but the growth rate is lowered and the productivity is deteriorated. Further, the upper limit of the predetermined temperature for the temperature rise is preferably 1150 ° C or lower. When the predetermined temperature of the temperature rise is 1150° C. or lower, the polycrystalline germanium layer is deposited thinly by introducing the material gas of the polycrystalline germanium layer at a temperature rise to the predetermined temperature, and the oxide film is deposited at a predetermined temperature of the high temperature. Since it does not easily disappear, the possibility of single crystallization of the polycrystalline germanium layer can be reduced.

又,在升溫至前述規定溫度為止之際的開始多晶矽層的原料氣體的供給的溫度,以600℃~980℃的範圍內的溫度為佳。若在升溫至前述規定溫度為止之際中的開始多晶矽層之原料氣體的供給的溫度為980℃以下,則由於升溫中氧化膜變得不易消失,故能夠抑制多晶矽層的單晶化。又,若為600℃以上,則能夠確保高生產率。In addition, the temperature at which the supply of the material gas of the polycrystalline germanium layer is started at the time of the temperature rise to the predetermined temperature is preferably in the range of 600 ° C to 980 ° C. When the temperature at which the supply of the raw material gas of the polycrystalline germanium layer is started is 980 ° C or less at the time of the temperature rise to the predetermined temperature, the oxide film is less likely to disappear during the temperature rise, so that the single crystal of the polycrystalline germanium layer can be suppressed. Moreover, when it is 600 ° C or more, high productivity can be ensured.

另外,在升溫至前述規定溫度為止之際中的多晶矽層的原料氣體的供給,在與所述升溫至規定溫度為止的升溫開始為同時開始亦可,或在正進行升溫至規定溫度為止的中途開始亦可。In addition, the supply of the material gas in the polycrystalline silicon layer at the time of the temperature rise to the predetermined temperature may be started simultaneously with the start of the temperature rise until the temperature rises to the predetermined temperature, or may be performed until the temperature is raised to the predetermined temperature. It can be started.

接著,研磨堆積於基底晶圓2的多晶矽層6的表面而得到研磨面(參考第1圖的步驟S24、第2圖(g))。Next, the surface of the polysilicon layer 6 deposited on the base wafer 2 is polished to obtain a polished surface (refer to step S24 and FIG. 2(g) of FIG. 1).

在此,為了除去經研磨之多晶矽層6的表面的粒子,進行貼合前洗淨(參考第1圖的步驟S25)。Here, in order to remove the particles on the surface of the polished polycrystalline germanium layer 6, the particles are washed before bonding (refer to step S25 of Fig. 1).

另外,對於接合晶圓的第1圖的步驟S11~S14,以及對於基底晶圓的第1圖的步驟S21~S25,任一方先進行亦可,或雙方並行進行亦可。Further, either the steps S11 to S14 of the first drawing of the bonding wafer and the steps S21 to S25 of the first drawing of the base wafer may be performed either first or both.

接著,將經形成多晶矽層6的基底晶圓2,以將基底晶圓2的經形成多晶矽層6的表面(研磨面)與接合晶圓 1的經植入離子側的表面接合的方式,與形成絶緣膜3的接合晶圓 1密接而貼合(參考第1圖的步驟S31、第2圖(h))。Next, the base wafer 2 on which the polycrystalline germanium layer 6 is formed is bonded to the surface of the base wafer 2 on which the polycrystalline germanium layer 6 is formed (the polished surface) and the surface on which the implanted wafer 1 is implanted on the ion side. The bonded wafer 1 on which the insulating film 3 is formed is in close contact with each other (refer to step S31 and FIG. 2(h) of FIG. 1).

接著,對於經貼合的晶圓,施予使離子植入層4產生微小氣泡層的熱處理(剝離熱處理),藉由以離子植入層4(微小氣泡層)剝離接合晶圓1而薄膜化,製作於基底晶圓2上經形成絶緣膜3及SOI層7的貼合式SOI晶圓8(參考第1圖的步驟S32、第2圖(i))。Next, a heat treatment (peeling heat treatment) for causing the ion implantation layer 4 to generate a microbubble layer is applied to the bonded wafer, and the wafer 1 is peeled off by the ion implantation layer 4 (microbubble layer) to be thinned. The bonded SOI wafer 8 on which the insulating film 3 and the SOI layer 7 are formed on the base wafer 2 is produced (refer to step S32 and FIG. 2(i) of FIG. 1).

之後,為了增加貼合交界面的結合強度,對貼合式SOI晶圓8施予結合熱處理(參考第1圖的步驟S33)。Thereafter, in order to increase the bonding strength of the bonding interface, a bonding heat treatment is applied to the bonded SOI wafer 8 (refer to step S33 of Fig. 1).

以如前述方式,能夠製造貼合式SOI晶圓。另外,經貼合的接合晶圓1的薄膜化,離子植入剝離法以外,亦得以藉由研磨、拋光、蝕刻等進行或藉由這些組合而進行。As described above, a bonded SOI wafer can be manufactured. Further, the thinned film of the bonded bonded wafer 1 can be formed by polishing, polishing, etching, or the like in addition to the ion implantation stripping method.

若為如以上説明的本發明之貼合式SOI晶圓的製造方法,能夠保持高生產率並同時抑制多晶矽層的單晶化。又,本發明之貼合式SOI晶圓的製造方法,不僅限於多晶矽層的形成,亦能夠應用於單晶矽層形成時的生產率提升之故,通用性為高。 〔實施例〕According to the method for producing a bonded SOI wafer of the present invention as described above, it is possible to maintain high productivity and suppress single crystal formation of the polysilicon layer. Further, the method for producing a bonded SOI wafer of the present invention is not limited to the formation of a polycrystalline germanium layer, and can be applied to an increase in productivity at the time of formation of a single crystal germanium layer, and has high versatility. [Examples]

以下,雖然顯示實施例及比較例並更具體地說明本發明,但本發明並非限定於這些實施例。Hereinafter, the present invention will be described more specifically by showing examples and comparative examples, but the present invention is not limited to these examples.

〔實施例〕 使用第1圖、第2圖說明之貼合式SOI晶圓的製造方法製作貼合式SOI晶圓。在此之際,使用直徑200mm、晶體方位<100>、電阻率1300Ω‧cm、p型的單晶矽晶圓作為基底晶圓,於基底晶圓之氧化膜的形成及多晶矽層的堆積以以下條件進行。[Examples] A bonded SOI wafer was produced by using the method of manufacturing a bonded SOI wafer described in Figs. 1 and 2 . In this case, a single crystal germanium wafer having a diameter of 200 mm, a crystal orientation of <100>, a resistivity of 1300 Ω·cm, and a p-type is used as the base wafer, and the formation of the oxide film on the base wafer and the deposition of the polysilicon layer are as follows. Conditions are carried out.

氧化膜形成條件 SC1+SC2洗淨 氧化膜的厚度約1nmOxide film formation conditions SC1+SC2 cleaning The thickness of the oxide film is about 1 nm

多晶矽層的堆積條件(如第3圖所顯示之條件) 投入溫度:850℃ 850℃~1070℃的一階段的堆積(在升溫開始的同時供給原料氣體) 常壓 膜厚3.0μm(研磨後的膜厚為2.0μm) 載子氣體:H2 氣體 原料氣體:三氯氫矽氣體(TCS氣體) 此時,在1070℃的堆積速度為3.0μm/分。Stacking conditions of polycrystalline germanium layer (as shown in Fig. 3) Input temperature: 850 °C 850 °C ~ 1070 °C one-stage deposition (feeding raw material gas at the same time of temperature rise) Normal pressure film thickness 3.0 μm (after grinding) The film thickness was 2.0 μm. Carrier gas: H 2 gas source gas: trichlorohydroquinone gas (TCS gas) At this time, the deposition rate at 1070 ° C was 3.0 μm / min.

又,測定多晶矽層的堆積所耗費時間(製程步驟經過時間),將後述比較例1中生產一片經堆積多晶矽層的晶圓的所需時間(秒/片)為基準而求得生產率(生產能力)。更進一步,藉由觀察剖面SEM確認堆積後的多晶矽層的單晶化狀況。將這些結果顯示於表1、第6圖及第7圖。以如此於基底晶圓上堆積多晶矽層,更進一步進行後續程序而進行貼合式SOI晶圓的製作。Further, it takes time (the elapsed time of the process step) to measure the deposition of the polycrystalline germanium layer, and the productivity (production capacity) is determined based on the time (seconds/piece) required to produce a wafer in which a polycrystalline germanium layer is deposited in Comparative Example 1 to be described later. ). Further, the single crystallized state of the deposited polycrystalline germanium layer was confirmed by observing the cross-sectional SEM. These results are shown in Table 1, Figure 6, and Figure 7. The polycrystalline germanium layer is deposited on the base wafer in this manner, and the subsequent process is further performed to fabricate the bonded SOI wafer.

〔比較例1〕 與實施例相同地進行貼合式SOI晶圓的製作。除了,多晶矽層的堆積條件,以第4圖所顯示為條件。即,在升溫之際不供給TCS氣體,藉由以900℃與1070℃的二階段的條件供給TCS氣體而進行多晶矽層的堆積,又,在900℃中的堆積速度為0.3μm/分,在1070℃中的堆積速度為3.0μm/分。[Comparative Example 1] A bonded SOI wafer was produced in the same manner as in the example. Except for the deposition conditions of the polycrystalline germanium layer, the conditions shown in Fig. 4 are ascertained. In other words, when the temperature is raised, the TCS gas is not supplied, and the TCS gas is supplied under two-stage conditions of 900 ° C and 1070 ° C to deposit the polycrystalline germanium layer, and the deposition rate at 900 ° C is 0.3 μm / min. The deposition rate at 1070 ° C was 3.0 μm / min.

又,與實施例同樣地進行多晶矽層的堆積工程中的製程步驟經過時間的測定,以及堆積後的多晶矽層的單晶化的狀況確認。於此比較例1之中,由於將生產一片經堆積多晶矽層的晶圓的所需時間為基準,因此生產能力為1。將這些結果顯示於表1、第6圖及第7圖。Further, in the same manner as in the examples, the measurement of the elapsed time of the process step in the deposition process of the polycrystalline germanium layer and the state of single crystal formation of the polycrystalline germanium layer after deposition were confirmed. In Comparative Example 1, the productivity was 1 because the time required to produce a wafer in which a polycrystalline germanium layer was deposited was used as a reference. These results are shown in Table 1, Figure 6, and Figure 7.

〔比較例2〕 與實施例同樣地進行貼合式SOI晶圓的製作。但是,多晶矽層的堆積條件,以第5圖所顯示為條件。即,在升溫之際不供給TCS氣體,藉由僅以1020℃的一階段的條件供給TCS氣體而進行多晶矽層的堆積。又,堆積速度為2.2μm/分。[Comparative Example 2] A bonded SOI wafer was produced in the same manner as in the example. However, the deposition conditions of the polycrystalline germanium layer are as shown in Fig. 5. In other words, the TCS gas was not supplied at the time of temperature rise, and the polycrystalline germanium layer was deposited by supplying the TCS gas only at one stage of 1020 °C. Further, the deposition rate was 2.2 μm/min.

又,與實施例同様地進行在多晶矽層的堆積工程中的製程步驟經過時間的測定、以比較例1為基準的生產能力的算出、以及堆積後的多晶矽層的單晶化的狀況確認。這些結果顯示於表1、第6圖及第7圖。In the same manner as in the examples, the measurement of the elapsed time of the process step in the deposition process of the polycrystalline germanium layer, the calculation of the productivity based on Comparative Example 1, and the state of single crystal formation of the polycrystalline germanium layer after deposition were confirmed. These results are shown in Table 1, Figure 6, and Figure 7.

【表1】 【Table 1】

如表1、第6圖及第7圖所顯示,以本發明之貼合式SOI晶圓的製造方法製造貼合式SOI晶圓的實施例中,經堆積多晶矽層的晶圓的生產率(生產能力)高,亦無發生多晶矽層的單晶化。又,清楚得知於製作貼合式SOI晶圓後之中亦無發生多晶矽層的單晶化,也提升貼合式SOI晶圓製造整體的生產率。As shown in Table 1, Figure 6, and Figure 7, the productivity of a wafer in which a polycrystalline germanium layer is stacked in an embodiment of manufacturing a bonded SOI wafer by the method of manufacturing a bonded SOI wafer of the present invention (production) The ability is high, and no single crystal of the polysilicon layer occurs. Further, it is clear that the single crystal of the polysilicon layer does not occur in the production of the bonded SOI wafer, and the overall productivity of the bonded SOI wafer is improved.

另一方面,在升溫之際不供給多晶矽層的原料氣體,以二階段的條件進行多晶矽層的堆積的比較例1中,雖然無發生多晶矽層的單晶化,但生產率低。又,在升溫之際未供給多晶矽層的原料氣體,以一階段的條件進行多晶矽層的堆積的比較例2中,生產率低,且發生多晶矽層的單晶化。On the other hand, in Comparative Example 1 in which the raw material gas of the polycrystalline germanium layer was not supplied and the polycrystalline germanium layer was deposited under the two-stage condition, the single crystal of the polycrystalline germanium layer did not occur, but the productivity was low. In addition, in Comparative Example 2 in which the raw material gas of the polycrystalline germanium layer was not supplied and the polycrystalline germanium layer was deposited under one-stage conditions, the productivity was low and the polycrystalline germanium layer was single-crystallized.

另外,本發明並不為前述實施例所限制。前述實施例為例示,具有與本發明的申請專利範圍所記載的技術思想為實質相同的構成,且發揮同樣作用效果者,皆包括於本發明的技術範圍。Further, the present invention is not limited by the foregoing embodiments. The above-described embodiments are exemplified, and have substantially the same configuration as the technical idea described in the patent application scope of the present invention, and all of the same effects are included in the technical scope of the present invention.

1‧‧‧接合晶圓
2‧‧‧基底晶圓
3‧‧‧絶緣膜
4‧‧‧離子植入層
5‧‧‧氧化膜
6‧‧‧多晶矽層
7‧‧‧SOI層
8‧‧‧貼合式SOI晶圓
1‧‧‧ Bonded wafer
2‧‧‧Substrate wafer
3‧‧‧Insulation film
4‧‧‧Ion implantation layer
5‧‧‧Oxide film
6‧‧‧Polysilicon layer
7‧‧‧SOI layer
8‧‧‧Fixed SOI Wafer

Claims (5)

一種貼合式SOI晶圓之製造方法,將皆為矽單晶所構成之接合晶圓及基底晶圓透過絕緣膜予以貼合而製造貼合式SOI晶圓,該製造方法包含下列步驟: 於該基底晶圓被貼合的貼合面側予以堆積多晶矽層; 研磨該多晶矽層的表面而得到研磨面; 於該接合晶圓的貼合面形成該絕緣膜; 透過該絕緣膜將該基底晶圓的該多晶矽層的該研磨面與該接合晶圓予以貼合;以及 將經貼合之該接合晶圓予以薄膜化而形成SOI層, 其中,使用電阻率100Ω‧cm以上之單晶矽晶圓作為該基底晶圓, 堆積該多晶矽層之步驟,更包含於該基底晶圓的堆積該多晶矽層的表面上預先形成氧化膜之階段, 該多晶矽層的堆積係藉由升溫至1000℃以上的規定溫度為止,且在該規定溫度下供給該多晶矽層之原料氣體而進行,更進一步在升溫至該規定溫度為止之際中也供給該多晶矽層之原料氣體。A method for manufacturing a bonded SOI wafer, wherein a bonded wafer and a base wafer each composed of a single crystal are bonded through an insulating film to produce a bonded SOI wafer, the manufacturing method comprising the following steps: Depositing a polycrystalline germanium layer on the bonding surface side of the bonded base wafer; polishing the surface of the polycrystalline germanium layer to obtain a polished surface; forming the insulating film on the bonding surface of the bonded wafer; and transmitting the underlying crystal through the insulating film The polished surface of the circular polycrystalline germanium layer is bonded to the bonded wafer; and the bonded bonded wafer is thinned to form an SOI layer, wherein single crystal twin crystal having a resistivity of 100 Ω·cm or more is used. The step of depositing the polysilicon layer as the base wafer further includes a step of depositing an oxide film on the surface of the base wafer on which the polysilicon layer is deposited, and the deposition of the polysilicon layer is increased to 1000 ° C or higher. The raw material gas of the polycrystalline germanium layer is supplied at a predetermined temperature until the predetermined temperature is reached, and the raw material gas of the polycrystalline germanium layer is also supplied while the temperature is raised to the predetermined temperature. 如請求項1所述之貼合式SOI晶圓的製造方法,其中該氧化膜係藉由濕洗淨所形成。The method of manufacturing a bonded SOI wafer according to claim 1, wherein the oxide film is formed by wet cleaning. 如請求項1所述之貼合式SOI晶圓的製造方法,其中該規定溫度為1150℃以下。The method of manufacturing a bonded SOI wafer according to claim 1, wherein the predetermined temperature is 1150 ° C or lower. 如請求項2所述之貼合式SOI晶圓的製造方法,其中該規定溫度為1150℃以下。The method of manufacturing a bonded SOI wafer according to claim 2, wherein the predetermined temperature is 1150 ° C or lower. 如請求項1至4中任一項所述之貼合式SOI晶圓的製造方法,其中在升溫至該規定溫度為止之際中的開始供給該多晶矽層之原料氣體的溫度為600℃~980℃的範圍內之溫度。The method for producing a bonded SOI wafer according to any one of claims 1 to 4, wherein, when the temperature is raised to the predetermined temperature, the temperature of the source gas supplied to the polysilicon layer is 600 ° C to 980 Temperature in the range of °C.
TW106115681A 2016-06-23 2017-05-12 Bonded SOI wafer manufacturing method TW201810380A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016124475A JP6498635B2 (en) 2016-06-23 2016-06-23 Manufacturing method of bonded SOI wafer

Publications (1)

Publication Number Publication Date
TW201810380A true TW201810380A (en) 2018-03-16

Family

ID=60783453

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106115681A TW201810380A (en) 2016-06-23 2017-05-12 Bonded SOI wafer manufacturing method

Country Status (4)

Country Link
JP (1) JP6498635B2 (en)
CN (1) CN109075028B (en)
TW (1) TW201810380A (en)
WO (1) WO2017221563A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021190660A (en) * 2020-06-04 2021-12-13 株式会社Sumco Support substrate for bonded wafers
JP2022070034A (en) * 2020-10-26 2022-05-12 株式会社Sumco Method for manufacturing support substrate for laminated wafer, and support substrate for laminated wafer
JP2023157404A (en) * 2022-04-15 2023-10-26 信越半導体株式会社 Method for manufacturing polysilicon wafer

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4559010A (en) * 1984-05-01 1985-12-17 Toray Industries, Inc. Apparatus for producing oxidized filaments
US7273818B2 (en) * 2003-10-20 2007-09-25 Tokyo Electron Limited Film formation method and apparatus for semiconductor process
JP2009016393A (en) * 2007-06-29 2009-01-22 Toshiba Corp Semiconductor substrate, semiconductor apparatus, and method of manufacturing semiconductor substrate
JP5453780B2 (en) * 2008-11-20 2014-03-26 三菱化学株式会社 Nitride semiconductor
FR2953640B1 (en) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, WITH REDUCED ELECTRICAL LOSSES AND CORRESPONDING STRUCTURE
CN102485974B (en) * 2010-12-03 2014-10-15 天威新能源控股有限公司 Method for direct growth of monocrystalline silicon through CVD (chemical vapor deposition) reaction
FR2973158B1 (en) * 2011-03-22 2014-02-28 Soitec Silicon On Insulator METHOD FOR MANUFACTURING SEMICONDUCTOR-TYPE SUBSTRATE ON INSULATION FOR RADIO FREQUENCY APPLICATIONS
JP2013055231A (en) * 2011-09-05 2013-03-21 Shin Etsu Handotai Co Ltd Epitaxial wafer manufacturing method
JP6100200B2 (en) * 2014-04-24 2017-03-22 信越半導体株式会社 Manufacturing method of bonded SOI wafer
JP2015228432A (en) * 2014-06-02 2015-12-17 信越半導体株式会社 Soi wafer manufacturing method and bonded soi wafer

Also Published As

Publication number Publication date
CN109075028A (en) 2018-12-21
JP6498635B2 (en) 2019-04-10
WO2017221563A1 (en) 2017-12-28
CN109075028B (en) 2023-08-15
JP2017228686A (en) 2017-12-28

Similar Documents

Publication Publication Date Title
TWI590298B (en) Method of manufacturing a bonded SOI wafer
TWI610335B (en) Laminated SOI wafer manufacturing method and bonded SOI wafer
TWI709197B (en) A method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers
TWI692001B (en) Method for manufacturing laminated SOI wafer
US7910455B2 (en) Method for producing SOI wafer
JP2015228432A (en) Soi wafer manufacturing method and bonded soi wafer
TW201810380A (en) Bonded SOI wafer manufacturing method
JP5942948B2 (en) Manufacturing method of SOI wafer and bonded SOI wafer
JP5310004B2 (en) Manufacturing method of bonded wafer
TWI804626B (en) Method for manufacturing bonded SOI wafer and bonded SOI wafer
WO2012086122A1 (en) Method for manufacturing soi wafer
JP6070487B2 (en) SOI wafer manufacturing method, SOI wafer, and semiconductor device
JP2018137278A (en) Bonded soi wafer manufacturing method
JP2003309253A (en) Soi wafer and manufacturing method of soi wafer