TW201735260A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TW201735260A TW201735260A TW105142857A TW105142857A TW201735260A TW 201735260 A TW201735260 A TW 201735260A TW 105142857 A TW105142857 A TW 105142857A TW 105142857 A TW105142857 A TW 105142857A TW 201735260 A TW201735260 A TW 201735260A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
- H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/696—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having at least one additional gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
- H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/031—Manufacture or treatment of data-storage electrodes
- H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016001669A JP6591291B2 (ja) | 2016-01-07 | 2016-01-07 | 半導体装置およびその製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201735260A true TW201735260A (zh) | 2017-10-01 |
Family
ID=59275103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105142857A TW201735260A (zh) | 2016-01-07 | 2016-12-23 | 半導體裝置及其製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US10600799B2 (enExample) |
| JP (1) | JP6591291B2 (enExample) |
| CN (1) | CN106952920B (enExample) |
| TW (1) | TW201735260A (enExample) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI658585B (zh) * | 2018-03-30 | 2019-05-01 | 世界先進積體電路股份有限公司 | 半導體結構及其製造方法 |
| TWI724560B (zh) * | 2018-09-27 | 2021-04-11 | 台灣積體電路製造股份有限公司 | 半導體結構 |
| US11158533B2 (en) | 2018-11-07 | 2021-10-26 | Vanguard International Semiconductor Corporation | Semiconductor structures and fabrication method thereof |
| TWI755063B (zh) * | 2019-09-17 | 2022-02-11 | 台灣積體電路製造股份有限公司 | 半導體結構、積體電路以及形成半導體結構的方法 |
| TWI800881B (zh) * | 2020-12-15 | 2023-05-01 | 日商鎧俠股份有限公司 | 半導體裝置、其製造方法及記憶裝置 |
| TWI842085B (zh) * | 2021-12-09 | 2024-05-11 | 台灣積體電路製造股份有限公司 | 半導體結構與其形成方法 |
| US12336265B2 (en) | 2018-09-27 | 2025-06-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate structures for field effect transistors |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019050314A (ja) * | 2017-09-11 | 2019-03-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| KR102403031B1 (ko) * | 2017-10-19 | 2022-05-27 | 삼성전자주식회사 | 반도체 장치 |
| CN109979943B (zh) * | 2017-12-28 | 2022-06-21 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
| JP6998267B2 (ja) * | 2018-05-08 | 2022-01-18 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP7038607B2 (ja) * | 2018-06-08 | 2022-03-18 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| KR102582074B1 (ko) * | 2018-12-28 | 2023-09-21 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| US11158648B2 (en) * | 2019-03-14 | 2021-10-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Double channel memory device |
| JP2021082656A (ja) * | 2019-11-15 | 2021-05-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US11114451B1 (en) * | 2020-02-27 | 2021-09-07 | Silicon Storage Technology, Inc. | Method of forming a device with FinFET split gate non-volatile memory cells and FinFET logic devices |
| JP2021174911A (ja) | 2020-04-28 | 2021-11-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| CN115295570B (zh) * | 2022-09-26 | 2022-12-30 | 合肥晶合集成电路股份有限公司 | Cmos图像传感器的制作方法 |
| CN115863252B (zh) * | 2023-01-29 | 2023-05-23 | 合肥晶合集成电路股份有限公司 | 一种半导体结构的制备方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6204126B1 (en) * | 2000-02-18 | 2001-03-20 | Taiwan Semiconductor Manufacturing Company | Method to fabricate a new structure with multi-self-aligned for split-gate flash |
| JP4564272B2 (ja) | 2004-03-23 | 2010-10-20 | 株式会社東芝 | 半導体装置およびその製造方法 |
| US7098477B2 (en) * | 2004-04-23 | 2006-08-29 | International Business Machines Corporation | Structure and method of manufacturing a finFET device having stacked fins |
| KR100652433B1 (ko) * | 2005-09-08 | 2006-12-01 | 삼성전자주식회사 | 다중 비트 저장이 가능한 비휘발성 메모리 소자 및 그 제조방법 |
| US7612405B2 (en) * | 2007-03-06 | 2009-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabrication of FinFETs with multiple fin heights |
| KR100990599B1 (ko) * | 2008-05-30 | 2010-10-29 | 주식회사 하이닉스반도체 | 반도체 장치의 제조 방법 및 그에 따라 제조된 반도체 장치 |
| JP2010182751A (ja) * | 2009-02-03 | 2010-08-19 | Renesas Electronics Corp | 不揮発性半導体記憶装置及びその製造方法 |
| JP2011009296A (ja) * | 2009-06-23 | 2011-01-13 | Panasonic Corp | 半導体装置及びその製造方法 |
| JP2011040458A (ja) * | 2009-08-07 | 2011-02-24 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
| US8941153B2 (en) * | 2009-11-20 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with different fin heights |
| US20110147848A1 (en) * | 2009-12-23 | 2011-06-23 | Kuhn Kelin J | Multiple transistor fin heights |
| JP5816560B2 (ja) * | 2012-01-10 | 2015-11-18 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US8748989B2 (en) * | 2012-02-28 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin field effect transistors |
| KR101823105B1 (ko) * | 2012-03-19 | 2018-01-30 | 삼성전자주식회사 | 전계 효과 트랜지스터의 형성 방법 |
| JP5951374B2 (ja) * | 2012-07-09 | 2016-07-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| KR101953240B1 (ko) * | 2012-09-14 | 2019-03-04 | 삼성전자 주식회사 | 핀 트랜지스터 및 이를 포함하는 반도체 집적 회로 |
| US9012287B2 (en) * | 2012-11-14 | 2015-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell layout for SRAM FinFET transistors |
| US8896067B2 (en) * | 2013-01-08 | 2014-11-25 | International Business Machines Corporation | Method of forming finFET of variable channel width |
| US9159832B2 (en) * | 2013-03-08 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor fin structures and methods for forming the same |
| KR102054302B1 (ko) | 2013-06-21 | 2019-12-10 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
| US20150014808A1 (en) * | 2013-07-11 | 2015-01-15 | United Microelectronics Corp. | Semiconductor structure and fabrication method thereof |
| US9006110B1 (en) * | 2013-11-08 | 2015-04-14 | United Microelectronics Corp. | Method for fabricating patterned structure of semiconductor device |
| US9184087B2 (en) * | 2013-12-27 | 2015-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanisms for forming FinFETs with different fin heights |
| WO2015142847A1 (en) * | 2014-03-17 | 2015-09-24 | Tufts University | Integrated circuit with multi-threshold bulk finfets |
| JP2015185613A (ja) * | 2014-03-20 | 2015-10-22 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US9214358B1 (en) * | 2014-10-30 | 2015-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Equal gate height control method for semiconductor device with different pattern densites |
| KR102327143B1 (ko) * | 2015-03-03 | 2021-11-16 | 삼성전자주식회사 | 집적회로 소자 |
| US10396000B2 (en) * | 2015-07-01 | 2019-08-27 | International Business Machines Corporation | Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions |
-
2016
- 2016-01-07 JP JP2016001669A patent/JP6591291B2/ja active Active
- 2016-12-01 US US15/366,047 patent/US10600799B2/en active Active
- 2016-12-23 TW TW105142857A patent/TW201735260A/zh unknown
- 2016-12-28 CN CN201611236524.6A patent/CN106952920B/zh active Active
-
2020
- 2020-02-10 US US16/786,176 patent/US11393838B2/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI658585B (zh) * | 2018-03-30 | 2019-05-01 | 世界先進積體電路股份有限公司 | 半導體結構及其製造方法 |
| TWI724560B (zh) * | 2018-09-27 | 2021-04-11 | 台灣積體電路製造股份有限公司 | 半導體結構 |
| US12336265B2 (en) | 2018-09-27 | 2025-06-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate structures for field effect transistors |
| US11158533B2 (en) | 2018-11-07 | 2021-10-26 | Vanguard International Semiconductor Corporation | Semiconductor structures and fabrication method thereof |
| TWI755063B (zh) * | 2019-09-17 | 2022-02-11 | 台灣積體電路製造股份有限公司 | 半導體結構、積體電路以及形成半導體結構的方法 |
| TWI800881B (zh) * | 2020-12-15 | 2023-05-01 | 日商鎧俠股份有限公司 | 半導體裝置、其製造方法及記憶裝置 |
| US12120870B2 (en) | 2020-12-15 | 2024-10-15 | Kioxia Corporation | Semiconductor device and method for manufacturing semiconductor device |
| TWI842085B (zh) * | 2021-12-09 | 2024-05-11 | 台灣積體電路製造股份有限公司 | 半導體結構與其形成方法 |
| US12137573B2 (en) | 2021-12-09 | 2024-11-05 | Taiwan Semiconductor Manufacturing Company Limited | Self-aligned multilayer spacer matrix for high-density transistor arrays and methods for forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| US20170200726A1 (en) | 2017-07-13 |
| CN106952920B (zh) | 2021-12-24 |
| US10600799B2 (en) | 2020-03-24 |
| CN106952920A (zh) | 2017-07-14 |
| JP2017123398A (ja) | 2017-07-13 |
| JP6591291B2 (ja) | 2019-10-16 |
| US20200185394A1 (en) | 2020-06-11 |
| US11393838B2 (en) | 2022-07-19 |
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