TW201608615A - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TW201608615A
TW201608615A TW104126048A TW104126048A TW201608615A TW 201608615 A TW201608615 A TW 201608615A TW 104126048 A TW104126048 A TW 104126048A TW 104126048 A TW104126048 A TW 104126048A TW 201608615 A TW201608615 A TW 201608615A
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trench
sidewall
insulating layer
gate insulating
angle
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TW104126048A
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TWI562209B (en
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丁裕偉
蔡竣揚
黃國欽
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供用於電子裝置如DRAM記憶單元之嵌入式電晶體與其形成方法。溝槽形成於基板中，而閘極介電層與閘極形成於基板的溝槽中。源極/汲極區形成於基板中的溝槽其相反兩側上。在一實施例中，源極/汲極區之一者耦接至儲存節點，而源極/汲極區的另一者耦接至位元線。在此實施例中，閘極可耦接至字元線以形成DRAM記憶單元。介電成長調整劑可佈植至溝槽的側壁中，以調整閘極介電層的厚度。

Description

半導體裝置與其形成方法
本發明實施例關於半導體裝置，更特別關於嵌入式電晶體。
一般而言，互補式金氧半(CMOS)電晶體包括閘極和閘極介電層形成於基板(通常為半導體矽基板)上。藉由將N型或P型雜質佈植至基板中，可形成輕摻雜汲極於閘極的相反兩側上。氧化物襯墊與一或多個佈植遮罩(通常被稱為間隔物)可形成與閘極相鄰，並進行額外佈植以完成源極/汲極區。接著可控制施加至閘極的電流等級，以控制流經源極/汲極區的電流。
在過去數十年中，CMOS電晶體尺寸縮小以不斷改善速度、效能、電路密度、和每單位功能的成本。隨著習知基體MOSFET的閘極長度縮小，源極和汲極與通道相互影響的程度越來越高，造成對通道電位的影響增加。如此一來，具有短閘極長度的電晶體具有閘極無法充分控制通道的開關狀態等問題。
本發明一實施例提供之半導體裝置的形成方法，包括：佈植介電成長調整劑至溝槽的第一側壁中；以及沿著溝 槽的第一側壁與底部形成閘極絕緣層，其中閘極絕緣層沿著溝槽的第一側壁之形成速率，與閘極絕緣層沿著溝槽的底部之形成速率不同，且閘極絕緣層其厚度沿著溝槽的第一側壁逐漸縮小。
本發明一實施例提供之半導體裝置的形成方法，包括：以第一角度佈植第一介電成長調整劑至溝槽的第一側壁中；以第二角度佈植第二介電成長調整劑至溝槽的第二側壁中，第一角度不同於第二角度，且第一側壁不同於第二側壁；以及沿著溝槽的第一側壁、第二側壁、與底部形成閘極絕緣層，其中沿著溝槽的底部之閘極絕緣層具有第一厚度，沿著溝槽的第一側壁與第二側壁之閘極絕緣層具有第二厚度，且第一厚度小於第二厚度。
本發明一實施例提供之半導體裝置，包括：溝槽位於基板中，且溝槽包括第一側壁、第二側壁、與底部；以及閘極絕緣層襯墊溝槽的第一側壁、第二側壁、與底部，其中襯墊第一側壁之閘極絕緣層其厚度自溝槽之頂部至底部逐漸縮小。
θ1‧‧‧第一角度
θ2‧‧‧第二角度
D1‧‧‧深度
M1‧‧‧第一金屬化層
T1‧‧‧第一厚度
T2‧‧‧第二厚度
T3‧‧‧第三厚度
W1、W2‧‧‧寬度
WL‧‧‧字元線
110‧‧‧基板
112‧‧‧第一圖案化遮罩
114‧‧‧硬遮罩
216、2161、2162、2163、2164、2165‧‧‧溝槽
218‧‧‧鰭狀物
320‧‧‧第一介電材料
526‧‧‧閘極絕緣層
528‧‧‧閘極材料
630‧‧‧閘極
732‧‧‧第二介電層
834‧‧‧源極/汲極區
836‧‧‧矽化物區
950‧‧‧記憶單元
952‧‧‧位元線
954‧‧‧位元線接點
956‧‧‧儲存節點
958‧‧‧儲存節點接點
1101‧‧‧第一佈植製程
1103‧‧‧第二佈植製程
1105‧‧‧第一介電成長調整區
1107‧‧‧第二介電成長調整區
第1至8圖係一實施例中，嵌入式電晶體於製程中不同階段的示意圖。
第9圖一實施例中，採用嵌入式電晶體的記憶單元之平面圖。
第10A與10B圖係第9圖中記憶單元的剖視圖。
第11至12圖係一實施例中，採用雙側斜向佈植的示意圖。
第13至14圖係一實施例中，採用單側斜向佈植的示意圖。
如何製作與使用本發明實施例的方法將詳述於下。可以理解的是，本發明提供多種發明概念以實施於多種特定方向，但這些特定實施例僅用以舉例而非侷限本發明範疇。在本發明的多種圖式及實施例中，相同標號將用以標示類似單元。
首先如第1圖所示，提供基板110，其具有第一圖案化遮罩112形成其上。基板110可包含任何半導體材料，且可包含已知結構如組成漸變層或埋置氧化物。在一實施例中，基板110包括基體矽，其可為未摻雜或摻雜(比如p型、n型、或上述之組合)。適用於形成半導體裝置的其他材料亦可用。然而在一實施例中，基板110為基體矽。
第一圖案化遮罩112係形成以圖案化下方的材料(如下方的基板110)。在一實施例中，第一圖案化遮罩112包括已光罩曝光和顯影的光阻材料。一般而言，光阻材料經沉積、照射(曝光)、及顯影以去除部份光阻材料，因此定義第1圖所示的圖案。保留的光阻材料保護下方的材料免於後續製程步驟(如蝕刻)影響。
如第1圖所示，可視情況採用硬遮罩114。硬遮罩114是保護層，用以防止下方結構(如基板110)在蝕刻製程中被移除。在某些情況下，由於將圖案化的材料、蝕刻製程的時間、蝕刻劑的種類等因素，需在第一圖案化遮罩112外額外採用遮 罩。在基板110為矽基板的實施例中，適當的硬遮罩114包括氧化物層如氧化矽層，以及上方的氮化物層如氮化矽層(Si3N4)。氧化物層之形成方法可為任何氧化製程，比如在包含氧化物、水、一氧化氮、或上述之組合的環境中的濕式或乾式熱氧化，或者採用四乙基矽酸鹽(TEOS)和氧作為前驅物之化學汽相沉積(CVD)技術。舉例來說，氧化物層的形成方法亦可在氧、水、一氧化氮、上述之組合、或類似物之環境中，以原位蒸汽產生(ISSG)製程形成。在一實施例中，氧化物層的厚度介於約50Å至約100Å之間。氮化物層的形成方法可為CVD技術，其採用矽烷與氨作為前驅物。氮化物層的圖案化方法可採用CHF3電漿，而氧化物層的圖案化方法可採用CF4電漿。
本技術領域中具有通常知識者應理解，其他遮罩材料及/或結構可用於形成第一圖案化遮罩112和硬遮罩114中的任一者或兩者。舉例來說，可採用其他材料、單層、三層、或更多層。在另一實施例中，硬遮罩可包含單一氮化矽層而無下方的氧化物層。
第2圖係一實施例中，圖案化基板後的基板110。基板110的圖案化方法可為一或多個蝕刻步驟，以形成溝槽2161至2165(統稱為溝槽216)，上述溝槽具有鰭狀物218夾設於相鄰溝槽216之間。舉例來說，蝕刻基板110可採用HBr/O2、HBr/Cl2/O2、或SF6/Cl2電漿。如後續詳述內容，鰭狀物218將形成電晶體的源極/汲極區，而溝槽中交替的溝槽將形成電晶體的閘極。溝槽中的其他溝槽將形成隔離結構如淺溝槽隔離(STI)。
在第2圖所示之實施例中，溝槽216之深度D1可介於約1000Å至4000Å之間(即鰭狀物218的高度)，且鰭狀物218之寬度W1可介於約100Å至800Å之間。雖然此實施例中鰭狀物218具有相同寬度W1，但其他實施例中的鰭狀物218可具有不同寬度。如上所述，後續製程形成源極/汲極區於鰭狀物218的較上部份中。如此一來，可調整尺寸(如鰭狀物218的寬度和高度)以達電晶體所需的電性。此外，應注意相同晶圓上的鰭狀物可以具有不同的寬度和深度。
此外，亦可改變溝槽的寬度W2。如上所述，溝槽將轉變為閘極和隔離溝槽。如此一來，可調整溝槽寬度以改變閘極長度和隔離特性。舉例來說，與用於閘極的溝槽相比，某些實施例需要較寬的隔離溝槽以提供更大的隔離特性於相鄰裝置之間。在其他實施例中，需要較寬的溝槽用於閘極。
如第2圖所示，已移除第1圖之第一圖案化遮罩112。舉例來說，可採用O2電漿乾剝除與濃硫酸及過氧化氫的混合物去除第一圖案化遮罩112。
如第3圖所示，第一介電材料320形成於基板110上，其實質上填滿溝槽216。在一實施例中，第一介電材料320包括氧化矽層，其形成方法可為高密度電漿CVD沉積製程，其採用SiH4與O2的混合物。
如第3圖所示的一實施例中，平坦化第一介電材料320直到基板110的上表面。舉例來說，平坦化第一介電層320的方法可採用化學機械研磨(CMP)製程，其採用氧化物漿，且基板110作為停止層。
第4圖顯示自選定的溝槽216(如溝槽2162與2164)移除第一介電材料320。在一實施例中，可藉由形成並圖案化遮罩層(未圖示)以保護溝槽2161、2163、及2165中的第一介電材料320，並露出溝槽2162與2164中的介電材料，以選擇性地移除溝槽2162與2164中的第一介電材料320。遮罩的圖案化方法可採用前述第1與2圖中蝕刻基板110所用的光微影技術。舉例來說，可形成光阻材料，依據所需圖案進行曝光(如露出溝槽2162與2164)並顯影。此外，亦可採用上述的硬遮罩。
在第一介電材料320為氧化矽且基板110為矽的實施例中，可採用對基板110與第一介電材料320具有高蝕刻選擇性的蝕刻劑如CF4或C2F6，進行非等向蝕刻製程以去除第一介電材料320。上述方法在蝕刻或移除第一介電材料320時較不會影響基板110。
第5圖係一實施例中，沿著溝槽2162和2164的表面形成閘極絕緣層526，並在溝槽2162和2164內形成閘極材料528後的基板110。一般而言，閘極絕緣層526避免源極/汲極區和閘極之間的電子消耗(electron depletion)。在一實施例中，閘極絕緣層526包括氧化物層，其形成方法包括氧化製程(如在包括氧化物、水、一氧化氮、或上述之組合的環境中的濕式或乾式熱氧化)、在氧、水、一氧化氮、上述之組合、或類似物的環境中的原位蒸汽產生(ISSG)製程、或採用四乙氧基矽酸鹽(TEOS)與氧作為前驅物的化學氣相沉積(CVD)技術。其他材料包括高介電常數介電材料如氧化鉿、氧化鉿矽、氧化鋅、氧化鋯、氧化鉭、氧化鋁、或類似物，且亦可採用其他製程如原子 層沉積(ALD)、原子氣相沉積(AVD)、或類似製程形成。在一實施例中，閘極絕緣層526之厚度介於約20Å至約50Å之間。應注意第5圖中閘極絕緣層526未延伸於第一介電材料320上僅用以舉例。閘極絕緣層526是否延伸於第一介電材料320上，至少部分取決於閘極絕緣層526的形成方法。舉例來說，熱製程通常形成第5圖所示的實施例，而CVD製程或ISSG製程形成的閘極絕緣層526可延伸於第一介電材料320上。
視情況可佈植以幫助或抑制閘極絕緣層526的形成。舉例來說，佈植氮可抑制氧化物成長於選定的區域(如溝槽底部)，而佈植氟可增加氧化物成長。在一實施例中，氮佈植的角度可與基板的上表面正交。在此實施例中，溝槽側壁的佈植量低於溝槽底部的佈植量。沿著溝槽底部的氮佈植將抑制氧化物成長，造成溝槽底部的閘極絕緣層比溝槽側壁的閘極絕緣層薄。在另一實施例中，可調整佈植角度以沿著側壁佈植氮，使溝槽底部的閘極絕緣層比溝槽側壁的柵極絕緣層厚。藉由佈植氟以增加閘極絕緣層的相對成長速率，可達到類似效果(比如沿著溝槽底部的閘極絕緣層較薄或較厚)。
應注意在形成閘極絕緣層前，可先摻雜基板110以製備通道區。舉例來說，在形成具有P型摻雜源極/汲極區的P型電晶體時，可在形成閘極絕緣層526前，先對基板110之通道區(沿著溝槽2162和2164的側壁和底部)佈植n型掺質如磷、砷、氮、銻、或類似物。類似地，在形成具有n型摻雜源極/汲極區的n型電晶體時，可先對基板的通道區佈植p型掺質如硼、鋁、鎵、銦、或類似物。藉由調整佈植角度，可確保適當的佈植沿 著溝槽2162和2164的側壁區，如同沿著溝槽2162和2164的底部。在另一實施例中，可在形成溝槽前佈植基板110以分別形成n型井或p型井，且溝槽2162與2164形成於n型井或p型井中。
舉例來說，p型電晶體的形成方法可為佈植磷離子，對應溝槽2162與2164底部之佈植角度介於約0°至5°，而對應溝槽2162與2164的垂直側壁之佈植角度介於-25°至25°，佈植劑量介於約1E12原子/cm2至約3E13原子/cm2之間，且佈植能量介於約20KeV至400KeV之間。n型電晶體的形成方法可為佈植硼離子，對應溝槽2162與2164底部之佈植角度介於約0°至5°，而對應溝槽2162與2164的垂直側壁之佈植角度介於-25°至25°，佈植劑量介於約1E12原子/cm2至約3E13原子/cm2之間，且佈植能量介於約5KeV至300KeV之間。
閘極材料528包含導電材料如金屬(比如鉭、鈦、鉬、鎢、鉑、鋁、鉿、或釕)、金屬矽化物(比如鈦矽化物、鈷矽化物、鎳矽化物、鉭矽化物)、金屬氮化物(比如氮化鈦或氮化鉭)、掺雜多晶矽、其他導電材料、或上述之組合。在一實例中，沉積並再結晶非晶矽以產生多晶矽。在一實施例中，閘極層的形成方法為沉積如CVD、低壓CVD(LPCVD)、或類似方法，以形成順應性的層狀物覆蓋基板110並填入溝槽2162與2164。之後可進行平坦化製程如CMP製程，以移除多餘材料並形成與第5圖類似之結構。
閘極材料528可掺雜或未掺雜的沉積。舉例來說，一實施例之閘極材料528的形成方法可為沉積多晶矽層，且多晶矽層可掺雜磷離子(或其他p型掺質)以形成PMOS裝置，或掺 雜硼(或其他n型掺質)以形成NMOS裝置。舉例來說，多晶矽的沉積方法亦可為臨場掺雜多晶矽的爐管沉積。在另一實施例中，閘極材料528可包含多晶矽金屬合金或金屬閘極，其包含金屬如鎢、鎳、鈦、氮化鈦、或類似物。
第6圖顯示使第5圖之閘極材料528凹陷以形成閘極630，且閘極630沿著溝槽2162與2164的底部。在閘極材料包含多晶矽的實施例中，凹陷製程可採用乾蝕刻或濕蝕刻。在使用乾蝕刻的情況下，製程氣體可包含CF4、CHF3、NF3、SF6、Br2、HBr、Cl2、或上述之組合。稀釋氣體如氮氣、氧氣、或氬氣可視情況使用。在使用濕蝕刻的情況下，化學品可包含氨水：過氧化氫：水(APM)、氫氧化胺、氫氧化鉀、硝酸：氟化銨：水、及/或類似物。在一實施例中，閘極材料528的凹陷程度介於約500Å至約2000Å之間。
如第7圖所示，第二介電層732形成於基板110上，填滿溝槽2162與2164中的閘極630上之凹陷。第二介電層732之材料與製程可與前述之第一介電材料320類似。在沉積第二介電層732後，可進行平坦化製程如CMP製程以移除多餘材料，並形成與第7圖類似之結構。在一實施例中，平坦化製程露出鰭狀物218。
第8圖顯示一實施例中，形成源極/汲極區834。源極/汲極區834之掺雜方法可為佈植n型掺質或p型掺質。舉例來說，n型電晶體的形成方法可為佈植n型離子如磷離子，掺雜劑量介於約1E15原子/cm2至約5E15原子/cm2之間，且佈植能量介於約20KeV至約100KeV之間。p型電晶體的形成方法可為佈植p 型離子如硼離子，掺雜劑量介於約1E15原子/cm2至約5E15原子/cm2之間，且佈植能量介於約10KeV至約50KeV之間。
此外，第8圖亦顯示一實施例中視情況形成的矽化物區836。矽化物區836減少源極/汲極區834與後續步驟形成的接點之間的接觸電阻。舉例來說，矽化物區836之形成方法可為電漿氣相沉積(PVD)製程沉積金屬層(未圖示)如鈦、鎳、鎢、或鈷。回火製程可使金屬層與源極/汲極區834之基板110(如矽)反應，以形成金屬矽化物。其他區域如第一介電材料320(比如隔離結構)與第二介電層732上的部份金屬層，仍維持未反應的狀態。舉例來說，選擇性移除未反應的部份金屬層之方法，可為濕蝕刻製程。若必要的話可進行額外的回火循環，使矽化物區836轉化至更低電阻。
應理解的是，上述段落描述之實施例中的嵌入式電晶體可用於多種用途。舉例來說，第9、10A、10B圖所示之實施例中，上述嵌入式電晶體作為DRAM記憶單元中的存取電晶體。特別是第9圖為多個DRAM記憶單元之平面圖，第10A圖係沿著第9圖之切線A-A'的剖視圖，且第10B圖係沿著第9圖之切線B-B'的剖視圖。虛線框標示者為單一記憶單元950。
記憶單元950包含位元線952形成其中，比如第一金屬化層M1具有位元線接點954，使位元線952電性耦接至下方之存取電晶體的源極/汲極區834之一者。存取電晶體的其他源極/汲極區834，經由儲存節點接點958電性耦接至儲存節點956。舉例來說，儲存節點956可為金屬-絕緣物-金屬(MIM)電容、平面電容、U型電容、垂直電容、水平電容、非電容儲存 結構、或類似物。閘極630係電性耦接至字元線(WL)。
應理解上述實施例採用單一光罩與蝕刻製程形成隔離溝槽與嵌入式閘極。在此情況下採用自我對準製程的這些實施例，可避免採用分開光罩與蝕刻製程形成隔離溝槽與閘極溝槽的其他製程中對不準的問題。相信這些實施例可降低字元線干擾的問題。
上述實施例使佈局設計者擁有較大的設計自由。舉例來說，閘極長度係由溝槽深度而非鰭狀物之間的間距定義，因此不需增加間距即可調整閘極長度。
第11圖係另一實施例中，沿著溝槽216之側壁調整閘極絕緣層526(未圖示於第11圖，但搭配第12圖說明如下)的厚度。此實施例一開始如第11圖所示，已形成鰭狀物218與溝槽216，且某些溝槽已填有第一介電材料320(如前述之第1-3圖)。包含第一佈植製程1101與第二佈植製程1103的雙側斜向佈植，可用以佈植介電成長調整劑至溝槽216的側壁中。此外，一系列的斜向佈植製程只佈植微量(甚至沒有)介電成長調整劑至溝槽216的底部中。在一實施例中，介電常長調整劑可為介電成長促進劑如氟，或介電成長抑制劑如氮。
在介電成長調整劑為介電成長促進劑的一實施例中，當介電成長調整劑主要佈植至溝槽216的側壁時，沿著溝槽216之側壁成長的閘極絕緣層526其成長速率與厚度，均大於沿著溝槽216之底部成長的閘極絕緣層526。在介電成長調整劑為介電成長抑制劑的另一實施例中，沿著溝槽216之側壁成長的閘極絕緣層526其成長速率與厚度，均小於沿著溝槽216之底 部成長的閘極絕緣層526。
在一實施例中，第一佈植製程1101以第一角度θ1佈植介電成長調整劑，使其主要佈植至溝槽側壁中而避免檔板效應。舉例來說，當鰭狀物218的間距為寬度W2且溝槽216具有深度D1時，進行第一佈植製程1101的第一角度θ1大於寬度W2除以深度D1之反正切值(θ1>tan-1(W2/D1))。藉由大於寬度W2除以深度D1之反正切值的佈植角度，介電成長調整劑主要佈植至溝槽216的側壁中而非溝槽216的底部中。
在介電成長調整劑為氟的實施例中，第一佈植製程1101可佈植氟以形成第一介電成長調整區1105於溝槽216的側壁中。在一實例中，第一介電成長調整區1105其介電成長調整劑(如氟)的濃度可介於約1E13cm2至約1E15cm2之間，比如約1E14cm2。
同樣地，第二佈植製程1103的方向可與第一佈植製程1101的方向相反，將介電成長調整劑佈植至溝槽216的側壁，其與第一佈植製程1101佈植的側壁相對。在此實施例中，第二佈植製程1103以第二角度θ2佈植氟，且第二角度與第一角度θ1相反。第二角度θ2亦取決於寬度W2與深度D1，即大於寬度W2除以深度D1之反正切值(θ2>tan-1(W2/D1))。第二角度θ2與第一角度θ1相反，使第二佈植製程1103得以將介電成長調整劑佈植至溝槽216的側壁，其與第一佈植製程1101佈植的側壁相對。
第一佈植製程1101與第二佈植製程1103可由分開的製程進行，即在第一佈植製程1101與第二佈植製程1103之間需重新調整基板110的位置。在另一實施例中，第一佈植製程 1101與第二佈植製程1103可由單一製程完成，即於佈植製程中旋轉基板110，使溝槽216中的相對側壁得以暴露至佈植製程。介電成長調整劑的佈植方法可為任何合適方法，且這些方法均屬於此實施例之範疇。
在介電成長調整劑為氟的實施例中，第二佈植製程1103可佈植氟以形成第二介電成長調整區1107於溝槽216的側壁中。在一實施例中，第二介電成長調整區1107之介電成長調整劑(如氟)濃度可介於約1E13cm2至約1E15cm2之間，比如約1E14cm2。
第12圖顯示當第一佈植製程1101與第二佈植製程1103進行後，形成第一介電成長調整區1105與第二介電成長調整區1107。接著可形成閘極絕緣層526如前述(第5圖)。舉例來說，閘極絕緣層526可為氧化製程(如在包括氧化物、水、一氧化氮、或上述之組合的環境中的濕式或乾式熱氧化)、在氧、水、一氧化氮、上述之組合、或類似物的環境中的原位蒸汽產生(ISSG)製程、或採用四乙氧基矽酸鹽(TEOS)與氧作為前驅物的化學氣相沉積(CVD)技術形成的氧化物。其他合適製程與材料亦可用於形成閘極絕緣層526。
然而在第一介電成長調整區1105與第二介電成長調整區1107主要位於溝槽216之側壁中的情況下，沿著溝槽216之側壁(具有較高濃度的氟)成長的閘極絕緣層526，比沿著溝槽216之底部(具有較低濃度的氟或沒有氟)成長的閘極絕緣層具有更快的成長速度。如此一來，沿著溝槽216之側壁的閘極絕緣層526比沿著溝槽216之底部的閘極絕緣層厚，且溝槽216側 壁上的閘極絕緣層526其厚度由溝槽216之頂部至底部逐漸變薄。
舉例來說，在介電成長調整劑為氟的實施例中，沿著溝槽216之側壁的閘極絕緣層526於溝槽216頂部具有第一厚度T1(介於約30Å至約40Å之間)。沿著溝槽216之側壁的閘極絕緣層526於溝槽216底部具有第二厚度T2(小於約20Å)。換言之，沿著側壁的閘極絕緣層526其厚度自頂部朝底部變薄。沿著溝槽216之底部的閘極絕緣層526具有第三厚度T3，其小於第一厚度T1且小於或等於第二厚度T2(比如小於約20Å)。
在形成閘極絕緣層526後，可形成閘極630於閘極絕緣層526上，可形成第二介電層732於閘極630上，可形成源極/汲極區834(見虛線標示的區域)於鰭狀物218上，可視情況形成矽化物區836(未圖示於第14圖中)，且可形成位元線接點954、位元線952、儲存節點接點958、與儲存節點956。在一實施例中，閘極630、第二介電層732、源極/汲極區834、視情況形成的矽化物區836、位元線接點954、與儲存節點956的形成方法可為前述第5至10b圖中所述之方法。然而，任何其他合適方法與材料亦可用以形成上述單元。
藉由介電成長調整劑，可更佳地控制閘極絕緣層526的形成方法以產生所需結果。舉例來說，增加沿著溝槽側壁之閘極絕緣層526的厚度，可讓閘極絕緣層526隨之具有較大當量的氧化物厚度。如此一來，可降低閘極誘發的汲極漏電流(GIDL)而不會有次臨界漏電流(Isoff)的缺點，因為溝槽216之底部的閘極絕緣層仍維持較薄厚度。此外，上述製程不會在通 道遷移率上產生不需要的副作用。
第13圖係另一實施例中，沿著溝槽216之側壁形成的閘極絕緣層526(未圖示於第13圖中，但圖示於第14圖中)具有減少的厚度。在此實施例中，進行第一佈植製程1101如前述之第11圖。舉例來說，介電成長調整劑係佈植至溝槽216之側壁中以形成第一介電成長調整區1105，且此佈植製程以第一角度θ1佈植(依寬度W2除以深度D1的值計算)，使介電成長調整劑主要佈植至溝槽216的側壁中而非溝槽216的底部中。
然而此實施例中的介電成長調整劑僅佈植至溝槽中一側的側壁中，而不佈植至溝槽中對側的側壁中。上述佈植製程可為第一佈植製程1101。舉例來說，此實施例中的第一佈植製程1101可用以佈植介電成長調整劑至溝槽216的單側側壁中。然而僅進行第一佈植製程1101而不進行第二佈植製程1103，因此介電成長調整劑係佈植於溝槽216的單側側壁，而其他側壁大致上不具有介電成長調整劑。上述製程形成第一介電成長調整區1105於溝槽216的單側壁壁中(且亦沿著鰭狀物218的頂部)。
第14圖顯示進行第一佈植製程1101(但未進行第二佈植製程1103)後，可形成閘極絕緣層526如前述(見第5圖)。舉例來說，閘極絕緣層526可為氧化製程(如在包括氧化物、水、一氧化氮、或上述之組合的環境中的濕式或乾式熱氧化)、在氧、水、一氧化氮、上述之組合、或類似物的環境中的原位蒸汽產生(ISSG)製程、或採用四乙氧基矽酸鹽(TEOS)與氧作為前驅物的化學氣相沉積(CVD)技術形成的氧化物。其他合適製 程與材料亦可用於形成閘極絕緣層526。
然而在介電成長調整劑存在於溝槽216的單側側壁中的情況下，沿著溝槽216之單側側壁(佈植有介電成長調整劑)成長的閘極絕緣層526的成長速度(較快)，與沿著溝槽216之底部或相對側壁成長的閘極絕緣層526的成長速度不同。如此一來，溝槽216側壁上的閘極絕緣層526其厚度由溝槽216之頂部至底部逐漸變薄。舉例來說，位於溝槽216之側壁頂部(佈植有介電成長調整劑)的閘極絕緣層526可具有第一厚度T1。沿著溝槽216之側壁且靠近底部的閘極絕緣層526可具有第二厚度T2。此外，此實施例中沿著溝槽216之底部及其他側壁(未佈植介電成長調整劑)的閘極絕緣層526可具有第三厚度T3。
在形成閘極絕緣層526後，可形成閘極630於閘極絕緣層526上，可形成第二介電層732於閘極630上，可形成源極/汲極區834(見虛線標示的區域)於鰭狀物218上，可視情況形成矽化物區836(未圖示於第14圖中)，且可形成位元線接點954、位元線952、儲存節點接點958、與儲存節點956。在一實施例中，閘極630、第二介電層732、源極/汲極區834、視情況形成的矽化物區836、位元線接點954、與儲存節點956的形成方法可為前述第5至10b圖中所述之方法。然而，任何其他合適方法與材料亦可用以形成上述單元。
藉由介電成長調整劑沿著溝槽216之單側側壁之設計，可更佳地控制閘極形成，比如較厚的介電層可形成於源極/汲極區834之一者上，而不形成於源極/汲極區834的另一者上。舉例來說，在嵌入式電晶體之源極線節點上具有較厚的介 電層，而位元線結點上不具有較厚的介電層。如此一來，源極線節點上較厚的介電層可降低GIDL，且可避免位元線節點上的介電層較厚所造成的驅動電流劣化。
在一實施例中，半導體裝置的形成方法，包括：佈植介電成長調整劑至溝槽的第一側壁中。沿著溝槽的第一側壁與底部形成閘極絕緣層，其中閘極絕緣層沿著溝槽的第一側壁之形成速率，與閘極絕緣層沿著溝槽的底部之形成速率不同，且閘極絕緣層其厚度沿著溝槽的第一側壁逐漸縮小。
在另一實施例中，半導體裝置的形成方法包括：以第一角度佈植第一介電成長調整劑至溝槽的第一側壁中。以第二角度佈植第二介電成長調整劑至溝槽的第二側壁中，其中第一角度不同於第二角度，且第一側壁不同於第二側壁。沿著溝槽的第一側壁、第二側壁、與底部形成閘極絕緣層，其中沿著溝槽的底部之閘極絕緣層具有第一厚度，沿著溝槽的第一側壁與第二側壁之閘極絕緣層具有第二厚度，且第一厚度小於第二厚度。
在又一實施例中，半導體裝置，包括溝槽位於基板中，且溝槽包括第一側壁、第二側壁、與底部。閘極絕緣層襯墊溝槽的該第一側壁、第二側壁、與底部，其中襯墊第一側壁之閘極絕緣層其厚度自溝槽之頂部至底部逐漸縮小。
雖然本發明已以某些實施例及其優點揭露如上，但應理理解其非用以限定本發明，任何本技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。舉例來說，本技術領域中具有通常知識者自可在本發明範疇中採用多種結構、功能、步驟、與材料組成。此外，本申請案的範疇並不限於特定實施例中的製程、機器、製造、材料組成、裝置、方法、與步驟。本技術領域中具有通常知識者自可依據本發明，採用現有或未來發展中與上述實施例具有實質上相同功能或達到實質上相同結果的製程、機器、製造、材料組成、裝置、方法、與步驟。綜上所述，所附申請專利範圍意在將這樣的製程、機器、製造、材料組成、裝置、方法、與步驟包括在內。
T1‧‧‧第一厚度
T2‧‧‧第二厚度
T3‧‧‧第三厚度
110‧‧‧基板
218‧‧‧鰭狀物
320‧‧‧第一介電材料
526‧‧‧閘極絕緣層
630‧‧‧閘極
732‧‧‧第二介電層
834‧‧‧源極/汲極區
952‧‧‧位元線
954‧‧‧位元線接點
956‧‧‧儲存節點
1105‧‧‧第一介電成長調整區

Claims (12)

  1. 一種半導體裝置的形成方法，包括：佈植一介電成長調整劑至一溝槽的一第一側壁中；以及沿著該溝槽的該第一側壁與一底部形成一閘極絕緣層，其中該閘極絕緣層沿著該溝槽的該第一側壁之形成速率，與該閘極絕緣層沿著該溝槽的該底部之形成速率不同，且該閘極絕緣層其厚度沿著該溝槽的該第一側壁逐漸縮小。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，更包括佈植該介電成長調整劑至該溝槽的一第二側壁中，且該第二側壁不同於該第一側壁。
  3. 如申請專利範圍第2項所述之半導體裝置的形成方法，其中佈植該介電成長調整劑至該第一側壁中的第一角度大於0，且該第一角度大於該溝槽之寬度除以該溝槽之高度的反正切值。
  4. 如申請專利範圍第3項所述之半導體裝置的形成方法，其中佈植該介電成長調整劑至該第二側壁中的第二角度，與該第一角度相反。
  5. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中該溝槽的一第二側壁不具有任何介電成長調整劑。
  6. 一種半導體裝置的形成方法，包括：以一第一角度佈植一第一介電成長調整劑至一溝槽的一第一側壁中；以一第二角度佈植一第二介電成長調整劑至該溝槽的一第二側壁中，該第一角度不同於該第二角度，且該第一側壁 不同於該第二側壁；以及沿著該溝槽的該第一側壁、該第二側壁、與一底部形成一閘極絕緣層，其中沿著該溝槽的該底部之該閘極絕緣層具有一第一厚度，沿著該溝槽的該第一側壁與該第二側壁之該閘極絕緣層具有一第二厚度，且該第一厚度小於該第二厚度。
  7. 如申請專利範圍第6項所述之半導體裝置的形成方法，其中該第一角度大於該溝槽之寬度除以該溝槽之高度的反正切值，其中該第二角度大於該溝槽之寬度除以該溝槽之高度的反正切值，且該第二角度與該第一角度相反。
  8. 一種半導體裝置，包括：一溝槽位於一基板中，且該溝槽包括一第一側壁、一第二側壁、與一底部；以及一閘極絕緣層襯墊該溝槽的該第一側壁、該第二側壁、與該底部，其中襯墊該第一側壁之該閘極絕緣層其厚度自該溝槽之頂部至底部逐漸縮小。
  9. 如申請專利範圍第8項所述之半導體裝置，其中襯墊該第二側壁之該閘極絕緣層具有一致的厚度。
  10. 如申請專利範圍第8項所述之半導體裝置，其中襯墊該第二側壁之該閘極絕緣層自該溝槽之頂部至底部具有逐漸縮小的厚度。
  11. 如申請專利範圍第8項所述之半導體裝置，更包括一第一濃度之介電成長增進材料位於該第一側壁中。
  12. 如申請專利範圍第11項所述之半導體裝置，更包括一第二 濃度之介電成長增進材料位於該第二側壁中，其中該溝槽底部不具有任何該介電成長增進材料。
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