TWI646683B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TWI646683B
TWI646683B TW106135770A TW106135770A TWI646683B TW I646683 B TWI646683 B TW I646683B TW 106135770 A TW106135770 A TW 106135770A TW 106135770 A TW106135770 A TW 106135770A TW I646683 B TWI646683 B TW I646683B
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fin
feature
gate
gate stack
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TW106135770A
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TW201839984A (zh
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廖忠志
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台灣積體電路製造股份有限公司
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Abstract

本揭露提供了半導體結構之實施方式。半導體結構包含自半導體基材突出之鰭式主動區域；設置於鰭式主動區域上之閘極堆；形成於鰭式主動區域且設置於閘極堆之一側上之源極/汲極特徵；著陸於源極/汲極特徵上之伸長接觸特徵以及沉積於伸長接觸特徵之側壁上，且與伸長接觸特徵之末端無連接之介電材料層。

Description

半導體結構及其形成方法
本揭露是有關於一種鰭式場效電晶體之結構以及形成方法。
積體電路已進展至具有較小特徵尺寸之先進技術，例如32奈米、28奈米以及20奈米。於此先進技術中，閘極節距(間距)持續地縮減且因此包含接點至閘及。再者，具有鰭式主動區域之三維電晶體經常預期可增進組件效能。形成於鰭式主動區域上之三維場效電晶體亦被稱為鰭式場效電晶體。鰭式場效電晶體因短通道控制而需要狹窄鰭寬，因而導致相較於平面場效電晶體具有較小之上源極/汲極區域。此將進一步降低與源極/汲極著陸邊界之接觸。
隨著元件尺寸比例縮減，例如在深微米技術中，為了達到高密度閘極節距之需求，接觸尺寸持續地縮減。為了縮減接觸尺寸而不影響接觸電阻，於32奈米及以上之技術中提出了長形接點。長形接點允許閘極節距方向上有緊密寬度維度，但於閘極佈線方向上增加了長度以於微影圖案化制程中延 展延展源極/汲極接觸區域以及曝露區域。長形接點可達到高閘極密度以及較小之接觸電阻。然而，因線端側之空間限制而存在產生顧慮。於線端之顧慮，包含線端縮短、線端至線端橋接，導致接點至鰭式主動連結開口(短路)或是接點至接點漏電(橋接)。為了減少線端縮短，需要較寬之空間規範或是藉由光學鄰近校正(optical proximity correction,OPC)於線段上執行更多強勢再成形，此將影響晶片尺寸或是在一給定晶片節距內造成橋接。因鰭式主動區域非常狹窄，使得此顧慮在將來的鰭式電晶體甚至將更加嚴重。
因此，出現了為解決這些疑慮以增進電路效能及可靠度之鰭式電晶體以及接觸結構之結構與方法需求。
根據本揭露之一些實施方式，提出一種半導體結構，包含自半導體基材突出之鰭式主動區域，設置於鰭式主動區域上之閘極堆，形成於鰭式主動區域內且設置於閘極堆之一側上之源極/汲極特徵，著陸於源極/汲極特徵上之伸長接觸特徵；以及設置於伸長接觸特徵之側壁上，且與伸長接觸特徵的末端無連接之介電材料層，其中伸長接觸特徵之側壁係與閘極堆平行。
根據本揭露之一些實施方式，提出一種半導體結構，包含：自半導體基材突出之第一鰭式主動區域，且沿著第一方向自第一末端延展至第二末端；自半導體基材突出之第二鰭式主動區域，且沿著第一方向自第三末端延展至第四末端； 第一閘極堆以及第二閘極堆，各設置於第一鰭式主動區域以及第二鰭式主動區域上，其中第一閘極堆以及第二閘極堆於第一方向上遠離，且沿著與第一方向正交之一第二方向延伸；形成於第一鰭式主動區域內之第一源極/汲極特徵，且安插於第一閘極堆以及第二閘極堆間；形成於第二鰭式主動區域內之第二源極/汲極特徵，且安插於第一閘極堆以及第二閘極堆間；沿著第二方向延伸且著陸於第一源極/汲極特徵以及第二源極/汲極特徵上之伸長接觸特徵；，設置於伸長接觸特徵之側壁上之介電材料層，且與伸長接觸特徵的兩末端無連接，且伸長接觸特徵之側壁係沿著第二方向延伸。
根據本揭露之一些實施方式，提出一種積體電路結構形成方法，包含：形成淺溝隔離(STI)結構於第一半導體材料之半導體基材內，藉此定義以淺溝隔離(STI)結構分隔彼此之複數個鰭式主動區域；形成閘極堆於鰭式主動區域上；形成層間介電層以填充閘極堆間之空隙；圖案化層間介電層以形成溝槽於閘極堆中的兩相鄰者間；沉積第一介電材料層共型於溝槽內；以第二介電材料層填充溝槽；圖案化第二介電材料層以形成接觸開口；以及填充導電材料於接觸開口內以形成接觸特徵。
100‧‧‧方法
200‧‧‧半導體結構
202‧‧‧基材
204‧‧‧淺溝隔離特徵
206‧‧‧鰭式主動區域
208、208a、208b、208c、208d‧‧‧閘極堆
210‧‧‧閘極間隔物
212‧‧‧源極/汲極特徵
220‧‧‧層間介電材料層
230、230a、230b、230c、230d‧‧‧閘極堆
232‧‧‧閘極介電特徵
234‧‧‧閘極電極
234-1‧‧‧覆蓋層
234-2‧‧‧遮蔽層
234-3‧‧‧功函數金屬層
234-4‧‧‧另一遮蔽層
234-5‧‧‧填充金屬層
236‧‧‧硬遮罩
240‧‧‧層間介電材料層
242‧‧‧接觸開口
246‧‧‧高介電常數介電材料層
248‧‧‧介電材料層
250‧‧‧接觸開口
260‧‧‧接觸特徵
262‧‧‧長邊界
264‧‧‧短邊界
102~128‧‧‧步驟
為讓本揭露更明顯易懂，所附圖式將於下文中詳細說明。應瞭解到，這些圖式並非繪示各組件的實際尺寸。為了清楚表達這些實施方式中各元件之間的連接關係，將於圖式中將元件尺寸增加或縮減。
第1圖為繪示根據本揭露之一些實施方式之不同層面建構出製造具有多鰭結構之半導體結構之方法的流程圖。
第2圖、第3A圖、第4A圖、第4C圖、第5圖、第6圖、第7圖、第9圖、第10B圖、第11B圖、第12圖、第13B圖、第14圖以及第15A圖為繪示根據一些實施方式所建構之半導體結構在不同製造階段之剖面圖。
第3B圖、第4B圖、第10A圖、第11A圖、第13A圖、第13C圖以及第15B圖為繪示根據一些實施方式所建構之半導體結構在不同製造階段之上視圖。
第8A圖以及第8B圖為繪示根據一些實施方式所建構之半導體結構之閘極堆之剖面圖。
以下將以不同實施方式實施例揭露複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本揭露。也就是說，在本揭露部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。並且，除非有其他表示，在不同圖式中相同之元件符號可視為相對應的組件。這些圖式之繪示是為了清楚表達這些實施方式中各元件之間的連接關係，並非繪示各元件的實際尺寸。
第1圖為根據一些實施方式所建構之具有鰭式電晶體以及伸長接觸特徵之半導體結構之製造方法100之流程 圖。第2圖至第15B圖為繪示半導體結構200在不同製造階段中之上視圖或剖面圖。根據一些實施方式，半導體結構200包含以非對稱方式設計之鰭式電晶體以及伸長接觸特徵。半導體結構200及製造其之方法100將參照下文中之第1圖至第15B圖統一描述。
請參照第2圖，方法100始於步驟102，提供一半導體基材202。基材202包含矽。於一些其他實施方式中，基材202包含鍺、鍺化矽或是其他合適之半導體材料。基材202可替代地由一些其他合適之元素半導體組成，例如鑽石或鍺；合適之半導體化合物，例如矽碳化物、砷化銦或是磷化銦；或是合適之半導體合金，例如矽鍺碳化物、磷砷化鎵或是磷銦化鎵。
半導體基材202亦包含多種摻雜區域，例如n型井以及p型井。於一實施方式中，半導體基材202包含一磊晶半導體層。於另一實施方式中，半導體基材202包含以合適技術形成之隔離用之一埋置介電材料層，例如注氧隔離(separation by implanted oxygen,SIMOX)。於一些實施方式中，基材202可為絕緣層上覆半導體，例如，絕緣層上覆矽(silicon on insulator,SOI)。
仍參照第2圖，方法100前進至步驟104，形成淺溝隔離(STI)特徵204於半導體基材202上。於一些實施方式中，淺溝隔離特徵204之形成係藉由蝕刻至形成凹槽、以介電材料填充凹槽、研磨以去除多餘之介電材料以及平坦化上表面。一次或多次之蝕刻制程藉由軟遮罩或硬遮罩上之開口執行 於基材202上，其中上述之軟遮罩或硬遮罩係藉由微影圖案化以及蝕刻而形成。淺溝隔離特徵204之形成將進一步根據下文中之一些實施方式描述。
於此實施例中，硬遮罩係沉積於基材202上並藉由微影制程圖案化。硬遮罩層包含介電質，例如半導體氧化物、半導體氮化物，半導體氮氧化物，及/或半導體碳化物，且於一例示性實施方式中，硬遮罩層包含氧化矽薄膜以及氮化矽薄膜。硬遮罩層可藉由熱成長、原子層沉積(ALD)、化學氣相沉積(CVD)、高密度電漿化學氣相沉積(HDP-CVD)以及其他合適之沉積制程而形成。
用於定義鰭式結構之光阻層(或是光阻劑)可於硬遮罩層上形成。一例示性光阻層包含曝露於，例如紫外光、深紫外光或是極紫外光時產生質變之光敏材料。質變可被利用於藉由顯影制程選擇性移除曝光與未曝光之光阻層部位。此形成圖案化之光阻層之過程亦稱為微影圖案化。
於一實施方式中，藉由微影制程圖案化光阻層，並留下設置於半導體結構200上之部分之光阻材料。圖案化光阻層後，執行一蝕刻制程於半導體結構200上以使硬遮罩層產生開口，藉此將光阻層之圖案轉移至硬遮罩層。剩餘之光阻層可於圖案化硬遮罩層後移除。一例示性微影制程包含光阻層自旋塗布、軟烤、遮罩對準、曝光、曝光後烘烤、光阻層顯影、清洗以及風乾(例如，硬烤)。可替代地，微影制程可被執行、附加或是由其他方法取代，其他方法例如無光罩微影、電子束直寫以及離子束直寫。圖案化硬遮罩層之蝕刻制程可包含濕蝕 刻、乾蝕刻或是上述制程之組合。蝕刻制程可包含多重蝕刻步驟。例如，硬遮罩層中之矽氧化物薄膜可藉由磷酸溶液蝕刻。
於蝕刻制程中，接著蝕刻基材202未被已圖案化之硬遮罩層所覆蓋之部分。蝕刻制程中利用圖案化之硬遮罩層為蝕刻遮罩以圖案化基材202。蝕刻制程可包含任何合適之蝕刻技術，例如乾蝕刻、濕蝕刻及/或其他蝕刻方法(例如，活性離子蝕刻(RIE))。於一些實施方式中，蝕刻制程包含具有不同蝕刻化學組成之多重蝕刻步驟，設計為蝕刻基材202以形成具有特定凹槽輪廓之凹槽，以增進元件效能以及圖案密度。於一些實施例中，基材202之半導體材料可藉由使用氟基蝕刻液之乾蝕刻制程而蝕刻。尤其，應用於基材202之蝕刻制程被控制為使基材202被部分蝕刻。此蝕刻控制可藉由控制蝕刻時間或是藉由控制其他蝕刻參數而達成。於蝕刻制程後，具有鰭式主動區域206之鰭式結構係定義於基材202之上方及由基材202延伸。
一或更多之介電材料係填充於凹槽以形成淺溝隔離特徵204。合適之填充介電材料包含半導體氧化物、半導體氮化物、半導體氮氧化物、氟矽氧玻璃(FSG)、低介電常數之介電材料，及/或上述之組合。於不同之例示性實施方式中，介電材料係藉由高密度電漿化學氣相沉積制程、次大氣壓化學氣相沉積(SACVD)制程、高縱深比制程(HARP)、流動式化學氣相沉積及/或自旋塗布制程而形成。
介電材料之沉積可接續化學機械研磨/平坦化(CMP)制程以移除多餘之介電材料以及平坦化半導體結構之 頂表面。化學機械研磨制程可利用硬遮罩層為研磨停止層以避免研磨至半導體基材202。於此例中，化學機械研磨制程完全移除硬遮罩。硬遮罩可替代地以蝕刻制程移除。雖然於進一步之實施方式中，硬遮罩層之一些部分於化學機械研磨制程後保留。
請參照第3A圖以及第3B圖，方法100進行至步驟106，形成具有多個鰭式主動區域206(或是鰭特徵)之鰭式結構。步驟106包含使淺溝隔離特徵204凹陷以使鰭式主動區域206凸出至淺溝隔離特徵204之上方。凹陷制程引用一或多次蝕刻步驟(例如，乾蝕刻、濕蝕刻或是上述制程之組合)以選擇性地回蝕淺溝隔離特徵204。舉例來說，當淺溝隔離特徵204為氧化矽時，可利用以氫氟酸蝕刻之濕蝕刻制程。第3B圖為半導體結構200之上視圖。例示性之鰭式主動區域206於第一方向(X方向)彼此等間距隔開。鰭式主動區域206具有伸長之形狀以及朝向與X方向正交之第二方向(Y方向)。
多種摻雜制程可被應用於半導體區域以形成多種摻雜井，例如現階段或步驟106之前之n-井以及p-井。多種摻雜井可藉由重複離子布植而形成於半導體基材202內。
請參照第4A圖、第4B圖，以及第4C圖，方法100進行至步驟108，形成多種閘極堆208於鰭式主動區域206上。第4B圖為半導體結構200上視圖；第4A圖為沿著虛線線段AA’之半導體結構200側視圖；以及第4C圖為沿著虛線線段BB’之半導體結構200側視圖。如第4B圖所繪示，於此實施方式中，閘極堆208包含例示性閘極堆208a、208b、208c、208d。閘 極堆208具有伸長之形狀且朝向第一方向(X方向)。每一閘極堆208係設置於多個鰭式主動區域206上方。特定之一閘極堆208(例如閘極堆208a或是閘極堆208d)係設置於鰭式主動區域206之末端以使得閘極堆部分地著陸於鰭式主動區域206上且沿著Y方向部分地著陸於淺溝隔離特徵204。邊界被配置成虛設結構以縮減邊界效應以及增進整體之組件效能。
每一閘極堆208包含一閘極介電層以及一閘極電極。閘極介電層包含介電材料，例如矽氧化物以及包含導電材料之閘極電極，例如多晶矽。閘極堆208之形成包含沉積閘極材料(此例中包含多晶矽)；以及藉由微影制程以及蝕刻圖案化閘極材料。閘極硬遮罩層可形成於閘極材料層上以及於閘極堆之形成步驟中作為蝕刻遮罩。閘極硬遮罩層可包含任何合適之材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽、其他合適材料，及/或上述之組合。於一實施方式中，閘極硬遮罩包含多層膜，例如氧化矽以及氮化矽。於一些實施方式中，形成閘極堆之圖案化制程包含藉由微影制程形成一圖案化之光阻層；利用圖案化之光阻層為蝕刻遮罩以蝕刻硬遮罩層；以及利用圖案化之硬遮罩層為蝕刻閘極材料以形成閘極堆208。
閘極側壁特徵(或是閘極間隔物210)中之一或多者係形成於閘極堆208之側壁上。閘極間隔物210可被利用於使接續形成之源極/汲極特徵偏移且可用於設計或改良源極/汲極結構輪廓。閘極間隔物210可包含任何合適之介電材料，例如半導體氧化物、半導體氮化物、半導體碳化物、半導體氮氧化物、其他合適之介電材料及/或上述之組合。閘極間隔物 210可具有多層膜，例如雙膜(氮化矽膜以及氧化矽膜)或是三層膜(氧化矽膜；氮化矽膜；以及氧化矽膜)。閘極間隔物210之形成包含沉積以及非等向性蝕刻，例如乾蝕刻。
閘極堆208被配置於多種場效電晶體中之鰭式主動區域206，因此被稱為鰭式場效電晶體。於一些實施例中，場效電晶體包含n型電晶體以及p型電晶體。於一些其他實施例中，配置場效電晶體以形成一或多個靜態隨機存取記憶體(SRAM)晶片。每一靜態隨機存取記憶體晶片包含兩個配置為資料儲存之交叉耦合之反相器。更甚者，閘極堆208被配置以增加圖案密度均勻性以及增進製造品質。舉例來說，如上所述，閘極堆208包含每一沿著y方向自鰭式主動區域206延伸至淺溝隔離特徵204之邊界閘極堆208a、208d，並著陸於淺溝隔離特徵204以及鰭式主動區域206兩者之上。
請參照第5圖，方法100進行至步驟110，形成多種源極/汲極特徵212至個別之鰭式場效電晶體。源極/汲極特徵212可包含輕摻雜汲極(light doped drain,LDD)特徵以及重摻雜源極與汲極(S/D)兩者。舉例來說，每一場效電晶體包含形成至個別之鰭式主動區域206上以及被閘極堆208安插之源極/汲極特徵。通道形成於鰭式主動區域206中位於閘極堆下方之部位以及延展延展於源極/汲極特徵之間。
被抬高之源極/汲極特徵可藉由應變效應之選擇性磊晶成長以及增進之載子移動率與組件效能而形成。閘極堆208以及閘極間隔物210限制源極/汲極特徵212於源極/汲極區域。於一些實施方式中，源極/汲極特徵212係由一或多磊晶 層或是磊晶(epi)制程而形成，其中矽特徵、鍺化矽特徵、碳化矽特徵及/或其他合適特徵係以晶態成長於鰭式主動區域206上。可替代地，應用蝕刻制程以於磊晶成長前凹陷源極/汲極區域。合適之磊晶制程包含化學氣相沉積技術(例如，氣相磊晶(vapor-phase epitaxy,VPE)及/或超高真空化學氣相沉積(ultra-high vacuum CVD,UHV-CVD))、原子束磊晶、及/或其他合適制程。磊晶制程可利用與鰭式結構之成分反應之氣態及/或液態前驅物。
源極/汲極特徵212可於磊晶制程中原處摻雜，藉由引進摻雜成分包含：p型摻雜物，例如硼或二氟化硼(BF2)；n型摻雜物，例如磷或砷；及/或包含上述組合的其他合適摻雜物。當源極/汲極特徵212非於原處摻雜，則執行布植制程(例如，接面布植制程)以引進對應之摻雜物至源極/汲極特徵212。於一例示性實施方式中，n型場效電晶體中之源極/汲極特徵212包含碳化矽或是以磷摻雜之矽，而p型場效電晶體中之源極/汲極特徵212包含鍺或是以硼摻雜之鍺化矽。於一些其他實施方式中，抬高之源極/汲極特徵212包含多於一層之半導體材料層。舉例來說，鍺化矽層係磊晶成長於源極/汲極區域內之基材上且矽層係磊晶成長於鍺化矽層上。一或多次之退火制程包含快速熱退火(rapid thermal annealing,RTA)、雷射退火制程、其他合適之退火技術或是上述之組合。
請參照第6圖，方法100進行至步驟112，層間介電材料(inter-level dielectric,ILD)層220形成於基材上以覆蓋源極/汲極區域內之源極/汲極特徵212。層間介電材料層220 圍繞閘極堆208以及閘極間隔物210使得閘極堆208得以被移除且替代閘極形成於產生之孔穴內(亦稱為閘極凹槽)。於是，於此實施方式中，閘極堆208於層間介電層材料220形成後被移除。層間介電材料層220可為電性連接半導體結構200中多種元件之電性連接結構的部分。於此實施方式中，層間介電材料層220以絕緣物之作用支撐以及隔離導電線路。層間介電材料層220可包含任何合適之介電材料，例如半導體氧化物、半導體氮化物，半導體氮氧化物，其他合適之介電材料，或是上述之組合。於一些實施方式中，層間介電層材料220之形成包含沉積以及化學機械研磨以提供平坦化之頂表面。
請參照第7圖，方法100進行至步驟114之閘極替代。閘極堆208被閘極堆230以高介電常數介電質以及金屬替代，因此亦稱為高介電常數金屬閘極。如第7圖所繪示，鰭式主動區域206沿著Y方向自末端238A延展延展至另一末端238B。閘極替代制程可包含蝕刻、沉積以及研磨。於本揭露之實施例所繪示，例示性之閘極堆208a、208b、208c、208d被移除，致使閘極凹槽產生。於一些實施方式中，閘極堆208係藉由蝕刻制程移除，例如濕蝕刻，以選擇性移除閘極堆208。如存在更多材料，則蝕刻制程可包含多個蝕刻步驟以移除虛設閘極。接著沉積閘極材料，例如高介電常數介電材料以及金屬，於閘極凹槽內以形成閘極堆230，例如例示性之閘極堆230a、230b、230c、230d。進一步實行化學機械研磨以研磨以及自半導體結構200移除多餘之閘極材料。閘極堆230之結構以及形成將進一步於下文中參照第8A圖以及第8B圖描述。 第8A圖以及第8B圖為根據多種實施方式繪示之例示性閘極堆230之剖面圖。
閘極堆230(例如閘極堆230b)係與鰭式主動區域206之通道區域重迭而形成於基材202上。閘極堆230包含閘極介電特徵232以及設置於閘極介電特徵232上之閘極電極234。於此實施方式中，閘極介電特徵232包含高介電常數介電材料且閘極電極234包含金屬或合金。於一些實施例中，閘極介電層以及閘極電極皆可包含一些次層。高介電常數介電材料可包含金屬氧化物、金屬氮化物、例如氧化鑭(LaO)、一氧化鋁(AlO)、氧化鋯(ZrO)、氧化鈦(TiO)、五氧化二鉭(Ta2O5)、三氧化二釔(Y2O3)、鈦酸鍶(SrTiO3,STO)、鈦酸鋇(BaTiO3,BTO)、鋇鋯氧(BaZrO)、氧化鉿鋯(HfZrO)、氧化鉿鑭(HfLaO)、矽氧化鉿(HfSiO)、矽氧化鑭(LaSiO)、矽氧化鋁(AlSiO)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、鈦酸鍶鋇((Ba,Sr)TiO3,BST)、三氧化二鋁(Al2O3)、氮化矽(Si3N4)、氮氧化物、氮氧化矽(SiON)，或是其他合適之介電材料。閘極電極可包含鈦(Ti)、銀(Ag)、鋁(Al)、氮化鋁鈦(TiAlN)、碳化鉭(TaC)、碳氮化鉭(TaCN)、氮矽化鉭(TaSiN)、錳(Mn)、鋅(Zr)、氮化鈦(TiN)、氮化鉭(TaN)、銣(Ru)、鉬(Mo)、Al、氮化鎢(tungsten nitride,WN)、銅(Cu)、(鎢)W，或是任何合適材料。於一些實施方式中，不同金屬材料係使用於有各自功函數之n型場效電晶體以及p型場效電晶體。閘極堆230係藉由合適步驟形成於閘極凹槽內，例如包含沉積以及化學機械研磨之步驟。然而應當理解，閘極堆230可 為任何合適閘極結構。
閘極介電特徵232可進一步包含夾於高介電常數介電材料層以及鰭式主動區域206間之層間層。層間層可包含氧化矽、氮化矽、氮氧化矽及/或其他合適材料。層間層係藉由合適之方法沉積，例如原子層沉積、化學氣相沉積、臭氧氧化等。高介電常數介電層係藉由合適技術沉積於層間層上，例如原子層沉積、化學氣相沉積、金屬有機化學氣相沉積(metal-organic CVD,MOCVD)、物理氣相沉積、熱氧化、上述制程之組合，及/或其他合適技術。於一些實施方式中，閘極介電特徵232係於步驟108中形成於鰭式主動區域206上以形成閘極堆208。於此例中，閘極介電特徵232係成型為如第8A圖中繪示。於一些其他實施方式中，閘極介電特徵232係形成於高介電常數後制程中，其中閘極介電特徵232係於步驟118中設置於閘極凹槽內。於此例中，如第8B圖所示，閘極介電特徵232為U型。
閘極電極234可包含多種導電材料。於一些實施方式中，閘極電極234包含覆蓋層234-1、遮蔽層234-2、功函數金屬層234-3、另一遮蔽層234-4以及填充金屬層234-5。為促進本實施方式，覆蓋層234-1包含氮化鈦、氮化鉭或是其他合適材料，並以合適之沉積技術所形成，例如原子層沉積。遮蔽層234-2包含氮化鈦、氮化鉭或是其他合適材料，並以合適之沉積技術所形成，例如原子層沉積。於一些實施例中，並無呈現遮蔽層或是僅呈現其中一者於閘極電極234。
功函數金屬層234-3包含具有合適功函數之金屬 或合金之導電層，以增進對應之場效電晶體之組件效能。p型場效電晶體與n型場效電晶體之功函數(WF)金屬層1606不相同，其個別被稱為n型WF金屬以及p型WF金屬。WF金屬之選擇取決於形成於主動區域上之場效電晶體。舉例來說，半導體結構200包含n型場效電晶體之第一主動區域以及p型場效電晶體之另一主動區域，並據此個別形成n型WF金屬以及p型WF金屬於對應之閘極堆。尤其n型WF金屬為具有第一功函數之金屬，以縮減對應之n型場效電晶體之臨界電壓。n型WF金屬接近於矽傳導帶能量(Ec)或是較低之功函數，代表電子逃離較容易。舉例來說，n型WF金屬之功函數係約為或小於4.2電子伏特。p型WF金屬為具有第二功函數之金屬，以縮減對應之p型場效電晶體之臨界電壓。p型WF金屬接近於矽價電帶能量(Ev)或較高之功函數，代表電子與核間之強鍵結能。舉例來說，p型WF金屬之功函數係約為或大於5.2電子伏特。於一些實施方式中，n型WF金屬包含鉭。於一些其他實施方式中，n型WF金屬包含鋁化鈦(TiAl)、氮化鋁鈦，或是上述之組合。於一些其他實施方式中，n金屬包含鉭、鋁化鈦、氮化鋁鈦、氮化鎢，或是上述之組合。n型WF金屬可為包含多種金屬基薄膜之一堆疊，用以優化元件效能以及加工相容性。於一些實施方式中，p型WF金屬包含氮化鈦或氮化鉭。於一些其他實施方式中，p金屬包含氮化鈦、氮化鉭、氮化鎢、鋁鈦，或是上述之組合。p型WF金屬可為包含多種金屬基薄膜之一堆疊，用以優化元件效能以及加工相容性。功函數金屬係以合適技術沉積，例如物理氣相沉積。
遮蔽層234-4包含氮化鈦、氮化鉭或是其他合適材料，並以合適之沉積技術所形成，例如原子層沉積。於不同一些實施方式中，填充金屬層234-5包含鋁、鎢或是其他合適金屬。填充金屬層234-5係以合適之技術沉積，例如物理氣相沉積或電鍍。
請參照回第7圖，方法100亦可包含形成硬遮罩236於閘極堆230上之步驟，以保護閘極堆230於接續之制程中之損失。根據本揭露之實施例，硬遮罩236之形成包含藉由選擇性蝕刻凹陷閘極堆230；沉積(例如化學氣相沉積)；以及化學機械研磨。硬遮罩236可包含不同於層間介電層之介電材料之合適材料，以於蝕刻制程中達到選擇性蝕刻並形成接觸開口。於一些實施方式中，硬遮罩236包含氮化矽。舉例來說，氮化矽之硬遮罩236，係利用包含六氯乙矽烷(Hexachlorodisilane,HCD or Si2Cl6)、二氯矽烷(Dichlorosilane,DCS or SiH2Cl2)、丁氨基矽烷(Bis(TertiaryButylAmino)Silane,BTBAS or C8H22N2Si)以及二矽乙烷(Disilane,DS or Si2H6)之化學藥品之化學氣相沉積而形成。
請參照第9圖，方法100進行至步驟116，形成與層間介電材料層220於成分及形成上近似之另一層間介電材料層240。舉例來說，層間介電材料層240之形成可包含沉積以及化學機械研磨。
請參照第10A圖以及第10B圖，方法100進行至步驟118，藉由微影制程圖案化以及蝕刻以圖案化層間介電層240至形成連續開口242。硬遮罩可被使用於圖案化層間介電 層240。蝕刻制程自層間介電材料層240、220蝕刻至曝露出源極/汲極特徵212。第10A圖為上視圖之一部分(僅顯示層間介電層240以及接觸開口242)。第10B圖係沿著虛線段AA’之剖面圖。
請參照第11A以及11B圖，方法100進行至步驟120，藉由沉積使高介電常數介電材料層形成於連續接觸開口242之側壁上，形成高介電常數介電材料層246於側壁上。於一些實施方式中，高介電常數介電材料不同於閘極堆230之材料。舉例來說，高介電常數介電材料層246包含氮化矽或其他氮基介電材料。於一些其他實施方式中，高介電常數介電材料層246包含金屬氧化介電材料，例如氧化鉿、氧化鉭、氧化鈦、氧化鋯、氧化鋁或上述之組合。於一些實施例中，高介電常數介電材料層246之厚度介於5埃至30埃間之範圍內。第11A圖為上視圖之一部分(僅顯示層間介電層240；高介電常數介電材料層246；以及接觸開口242)。第11B圖係沿著虛線段AA’之剖面圖。
請參照第12圖，方法100進行至步驟122，沉積介電材料層248以填充於連續接觸開口242內。介電材料層248係填充於接觸開口內以取代填充導電材料於接觸開口242而形成接觸特徵。介電材料層248可具有不同於層間介電層之介電材料之成分。舉例來說，介電材料層248包含藉由流動式化學氣相沉積而形成之氧化矽。
請參照第13A圖以及第13B圖，方法100進行至步驟124，藉由圖案化介電材料層248定義將被填充以形成接觸 特徵之接觸開口250。接觸開口250與開口242不相同。開口242係由圖案化之層間介電層240定義，而接觸開口250係由層間介電層240、圖案化之介電材料層248以及高介電常數介電材料層246集體定義。第13A圖為上視圖之一部分(僅顯示層間介電層240；高介電常數介電材料層246；介電材料層248以及接觸開口250)。第13B圖係沿著虛線段AA’之剖面圖。於步驟124中，介電材料層248係藉由微影制程以及蝕刻而圖案化。於一些實施例中，圖案化之遮罩係藉由微影制程以及蝕刻而形成於介電材料層248上，其中源極/汲極特徵212因蝕刻制程選擇性地移除介電材料層248而被曝露。
第13C圖為根據一些實施方式所建構之半導體結構200之上視圖。第13C圖係與第13A圖近似，而其縮小至可包含大面積之半導體結構200以較佳地繪示原始開口242以及接觸開口250。開口242係由層間介電層240所定義以及延展延展之連續長開口，而接觸開口250係由高介電常數介電材料層246以及介電材料層248集體定義。尤其高介電常數介電材料層246僅位於沿著X方向之接觸開口250之側壁上而未位於沿著Y方向之末段側壁上。再者，如第13C圖所繪示，已形成之接觸開口250具有自一或多者鰭式場效電晶體延展延展之伸長形狀。因高介電常數介電材料層246不存在於接觸開口250之末端，形成於接觸開口250之接觸特徵將具有可縮減接觸電阻之更大接觸區域以及可增進制程視窗之擴大邊界。因此，其擴大了介於凹槽接觸至鰭式場效電晶體之源極/汲極區域之著陸邊界。
請參照第14圖，方法100進行至步驟126，回蝕高 介電常數介電材料層246使得源極/汲極特徵212於開口內被曝露。於回蝕制程中，高介電常數介電材料層246之頂表面亦被凹陷。
請參照第15A圖以及第15B圖，方法100進行至步驟128，形成接觸特徵260於接觸開口250內。根據一些實施例，接觸特徵260之形成包含沉積導電材料以及化學機械研磨。沉積可藉由合適技術而實行，例如物理氣相沉積、電鍍、化學氣相沉積，或是其他合適方法。接觸開口250係以一或多種導電材料填充，例如鈦、氮化鈦、氮化鉭、鈷、鎢、鋁、銅，或是上述之組合。如上所述，已形成之接觸特徵260具有長寬比大於二之伸長形狀，以縮減接觸電阻以及增進制程視窗。尤其，伸長之接觸特徵260係沿著其寬度方向以及長度方向為非對稱的。如第15B圖所繪示，伸長之接觸特徵260包含橫向接觸於高介電常數介電材料層246之兩長邊界262，以及橫向接觸於介電材料層248之兩短邊界264(亦被稱為末端)。換句話說，兩短邊界264之側壁與高介電常數介電材料層246無連接。
於一些實施方式中，於填充導電材料於接觸開口250前，矽化物可形成於源極/汲極特徵212上以進一步縮減接觸電阻。矽化物包含矽以及金屬，例如鈦矽化物、鉭矽化物、鎳矽化物或是鈷矽化物。矽化物可藉由成為自對準矽化物(或是金屬矽化物)之制程而形成。制程包含金屬沉積、使金屬與矽反應之退火以及移除未反應之金屬之蝕刻。
其他製造步驟可於方法100之步驟之前、之中以及之後實行。舉例來說，互連結構內之多種金屬線以及貫穿孔 進一步形成於半導體結構200上，以藉由合適技術電性連接多種鰭式場效電晶體以及其他元件至一功能電路內，例如雙重鑲嵌制程。於上述方法100中之多種圖案化制程中，每一圖案化制程可經由雙重圖案化或是多重圖案化而實行。
本揭露根據多種實施方式提供了接觸結構以及其製造方法。因而形成具有伸長形狀以及沿著其長度方向以及寬度方向為非對稱結構之接觸特徵。高介電常數介電材料層係設置於接觸特徵之長度側壁上但並未存在於兩末端。伸長之接觸特徵將具有更多為縮減接觸電阻之接觸區域以及為增進制程視窗之擴大邊界。因此，其擴大了介於凹槽接觸至鰭式場效電晶體之源極/汲極區域之著陸邊界。此使得設計者能壓縮線端空間規範因而增加了接觸點至鰭式主動區域206之線端著陸區域。已揭露之結構可使用於多種結合鰭式場效電晶體以增進效能之應用中。
因此，本揭露根據一些實施方式提供了半導體結構。半導體結構包含自半導體基材突出之鰭式主動區域；設置於鰭式主動區域上之閘極堆；形成於鰭式主動區域內且設置於閘極堆之一側上之源極/汲極特徵；著陸於源極/汲極特徵上之伸長接觸特徵；以及沉積於伸長接觸特徵之側壁上，且與伸長接觸特徵之末端無連接之介電材料層。伸長接觸特徵之側壁係與閘極堆平行。
本揭露根據一些其他實施方式提供了半導體結構。半導體結構包含自半導體基材突出，且沿著第一方向自第一末端延展延展至第二末端之第一鰭式主動區域；自半導體基 材突出，且沿著第一方向自第三末端延展延展至第四末端之第二鰭式主動區域；分別設置於第一鰭式主動區域以及第二鰭式主動區域上之第一閘極堆以及一第二閘極堆，其中第一閘極堆以及第二閘極堆於第一方向上遠離，且沿著與第一方向正交之第二方向延展延展；形成於第一鰭式主動區域內，且安插於第一閘極堆以及第二閘極堆間之第一源極/汲極特徵；形成於第二鰭式主動區域內，且安插於第一閘極堆以及第二閘極堆間之第二源極/汲極特徵；，沿著第二方向延展延展且著陸於第一源極/汲極特徵以及第二源極/汲極特徵上之伸長接觸特徵；沉積於伸長接觸特徵之側壁上，兩末端與伸長接觸特徵無連接之介電材料層。伸長接觸特徵之側壁係沿著第二方向延展延展。
本揭露根據一些實施方式提供了積體電路結構之形成方法。此方法包含形成淺溝隔離(STI)結構於第一半導體材料之半導體基材內，藉此定義複數個以淺溝隔離(STI)結構彼此分隔之鰭式主動區域；形成閘極堆於鰭式主動區域上；形成層間介電層以填充閘極堆間之空隙；圖案化層間介電層以形成溝槽於相鄰兩閘極堆間；保形地沉積第一介電材料層於溝槽內；以第二介電材料層填充溝槽；圖案化第二介電材料層以形成接觸開口；以及填充導電材料於接觸開口內以形成接觸特徵。
雖然本揭露已以實施方式揭露如上，然其並不用以限定本揭露，任何熟習此技藝者，在不脫離本揭露的精神和範圍內，當可作各種的更動與潤飾，因此本揭露的保護範圍當視後附的申請專利範圍所界定者為准。

Claims (10)

  1. 一種半導體結構，包含：一鰭式主動區域，自一半導體基材突出；一閘極堆，設置於該鰭式主動區域上；一源極/汲極特徵，形成於該鰭式主動區域內且設置於該閘極堆之一側上；一伸長接觸特徵，著陸於該源極/汲極特徵上，該伸長接觸特徵具有兩長邊界及兩短邊界；以及一介電材料層，設置於該伸長接觸特徵之該些長邊界上，且與該伸長接觸特徵的該些短邊界無連接，其中該伸長接觸特徵之該些長邊界係與該閘極堆的長軸平行。
  2. 如請求項第1項所述之半導體結構，其中該閘極堆包含一閘極介電特徵、該閘極介電特徵上之一閘極電極以及該閘極電極之側壁上之一間隔物；以及該介電材料層係安插於該閘極堆與該伸長接觸特徵間，且與該間隔物與該伸長接觸特徵直接接觸。
  3. 如請求項第1項所述之半導體結構，進一步包含一淺溝隔離(shallow trench isolation,STI)特徵，形成於該半導體基材上且環繞該鰭式主動區域。
  4. 如請求項第3項所述之半導體結構，進一步包含一第二閘極堆，部分地設置於該鰭式主動區域之一末端且部分地設置於該淺溝隔離特徵上。
  5. 一種半導體結構，包含：一第一鰭式主動區域，自一半導體基材突出，且沿著一第一方向自一第一末端延展至一第二末端；一第二鰭式主動區域，自該半導體基材突出，且沿著該第一方向自一第三末端延展至一第四末端；一第一閘極堆以及一第二閘極堆，各設置於該第一鰭式主動區域以及該第二鰭式主動區域上，其中該第一閘極堆以及該第二閘極堆於該第一方向上遠離，且沿著與該第一方向正交之一第二方向延伸；一第一源極/汲極特徵，形成於該第一鰭式主動區域內，且安插於該第一閘極堆以及該第二閘極堆間；一第二源極/汲極特徵，形成於該第二鰭式主動區域內，且安插於該第一閘極堆以及該第二閘極堆間；一伸長接觸特徵，沿著該第二方向延伸且著陸於該第一源極/汲極特徵以及該第二源極/汲極特徵上；以及一介電材料層，設置於該伸長接觸特徵之側壁上，且與該伸長接觸特徵的兩末端無連接，且該伸長接觸特徵之該些側壁係沿著該第二方向延伸。
  6. 如請求項第5項所述之半導體結構，其中該第一閘極堆以及該第二閘極堆皆包含一閘極介電特徵、該閘極介電特徵上之一閘極電極以及該閘極電極之側壁上之一間隔物；以及該介電材料層與該第一閘極堆之該間隔物以及該第二閘極堆之該間隔物直接接觸。
  7. 如請求項第5項所述之半導體結構，進一步包含：一淺溝隔離(shallow trench isolation,STI)特徵，形成於該半導體基材上且環繞該第一鰭式主動區域以及該第二鰭式主動區域；一第三閘極堆，部分地設置於該第一鰭式主動區域之該第一末端上以及該第二鰭式主動區域之該第三末端上，且部分地設置於該淺溝隔離特徵上；以及一第四閘極堆，部分地設置於該第一鰭式主動區域之該第二末端上以及該第二鰭式主動區域之該第四末端上，且部分地設置於該淺溝隔離特徵上。
  8. 一種半導體結構形成方法，包含：形成一淺溝隔離(STI)結構於一第一半導體材料之半導體基材內，藉此定義以淺溝隔離(STI)結構分隔彼此之複數個鰭式主動區域；形成閘極堆於該鰭式主動區域上；形成一層間介電層以填充該些閘極堆間之空隙；圖案化該層間介電層以形成一溝槽於該些閘極堆中的兩相鄰者間；沉積一第一介電材料層共型於該溝槽內；以一第二介電材料層填充該溝槽；圖案化該第二介電材料層以形成一接觸開口；以及填充一導電材料於該接觸開口內以形成一接觸特徵。
  9. 如請求項第8項所述之半導體結構形成方法，其中該圖案化該第二介電材料層以形成該接觸開口之步驟，包含圖案化該第二介電材料層以形成延展至曝露該些鰭式主動區域中之至少兩源極/汲極區域之一伸長開口。
  10. 如請求項第8項所述之半導體結構形成方法，其中該形成該些閘極堆之步驟包含：形成一虛設閘極堆於該些鰭式主動區域之第一末端；以及形成一第一閘極間隔物以及一第二閘極間隔物於該虛設閘極堆之相對側壁上，其中該第一閘極間隔物著陸於該淺溝隔離結構上且該第二閘極間隔物著陸於該些鰭式主動區域上。
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