CN112563266A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN112563266A CN112563266A CN202010475836.2A CN202010475836A CN112563266A CN 112563266 A CN112563266 A CN 112563266A CN 202010475836 A CN202010475836 A CN 202010475836A CN 112563266 A CN112563266 A CN 112563266A
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Abstract
本发明实施例的半导体装置,包括位于第一装置区中的多个第一全绕式栅极装置,以及位于第二装置区中的多个第二全绕式栅极装置。第一全绕式栅极装置的每一者包括多个通道部件的第一垂直堆叠、第一栅极结构以及多个内侧间隔物结构;第一栅极结构围绕通道部件的第一垂直堆叠并位于其上。第二全绕式栅极装置的每一者包括多个通道部件的第二垂直堆叠以及第二栅极结构,第二栅极结构围绕通道部件的第二垂直堆叠并位于其上。通道部件的第一垂直堆叠的两个相邻的通道部件之间,隔有第一栅极结构的一部分与内侧间隔物结构的至少一者。通道部件的第二垂直堆叠的两个相邻的通道部件之间,只隔有第二栅极结构的一部分。
Description
技术领域
本发明实施例涉及多栅极晶体管与制作方法,特别涉及在制作全绕式栅极晶体管时形成内侧间隔物于半导体装置的不同装置区中。
背景技术
半导体集成电路产业已经历指数成长。集成电路材料与设计的技术进展,使每一代的集成电路比前一代具有更小且更复杂的电路。在集成电路演进中,功能密度(如单位芯片面积的内连线装置数目)通常随着几何尺寸(如制作工艺所能产生的最小构件或线路)缩小而增加。尺寸缩小通常有利于增加产能与降低相关成本。尺寸缩小亦增加处理与形成集成电路的复杂度。
举例来说,集成电路技术朝更小的技术节点进展,并导入多栅极装置以增加栅极-通道耦合、降低关闭状态的电流、并减少短通道效应,进而改善栅极控制。多栅极装置通常指的是栅极结构或其部分位于通道区的多侧上的装置。鳍状场效晶体管与全绕式栅极晶体管(均视作非平面晶体管)为多栅极装置的例子,其变得更普及且为高效能与低漏电流应用的有力候选。鳍状场效晶体管具有栅极包覆超过一侧的隆起通道,比如栅极包覆自基板延伸的半导体材料的鳍状物的顶部与侧壁。与平面晶体管相较,此设置可更佳地控制通道并大幅降低短通道效应。具体而言,可减少次临界漏电流(如关闭状态的鳍状场效晶体管的源极与漏极之间的耦合),以降低短通道效应。全绕式栅极晶体管的栅极结构可部分或完全延伸于通道区周围,以由两侧或更多侧连接至通道区。全绕式栅极晶体管的通道区可由纳米线、纳米片、其他纳米结构、及/或其他合适结构所形成。在一些实施方式中,这些通道区包括多个垂直堆叠的纳米结构(水平延伸,以提供水平方向的通道)。这些全绕式栅极晶体管可视作垂直堆叠的水平全绕式栅极晶体管。
在全绕式栅极装置中,内侧间隔物用于降低栅极结构与源极/漏极结构之间的电容以及漏电流。虽然现有的据有内侧间隔物的全绕式栅极装置一般适用于其发展目的,但无法满足所有方面的需求。
发明内容
本发明一例示性的实施例关于半导体装置。半导体装置包括位于第一装置区中的多个第一全绕式栅极装置,以及位于第二装置区中的多个第二全绕式栅极装置。第一全绕式栅极装置的每一者包括多个通道部件的第一垂直堆叠、第一栅极结构以及多个内侧间隔物结构,第一栅极结构围绕通道部件的第一垂直堆叠并位于其上。第二全绕式栅极装置的每一者包括多个通道部件的第二垂直堆叠以及第二栅极结构,第二栅极结构围绕通道部件的第二垂直堆叠并位于其上。通道部件的第一垂直堆叠的两个相邻的通道部件之间,隔有第一栅极结构的一部分与内侧间隔物结构的至少一者。通道部件的第二垂直堆叠的两个相邻的通道部件之间,只隔有第二栅极结构的一部分。
本发明另一例示性的实施例关于半导体装置。半导体装置包括:第一全绕式栅极装置与第二全绕式栅极装置。第一全绕式栅极装置包括:第一通道部件、第一栅极结构以及内侧间隔物结构,第一通道部件位于第一全绕式栅极装置的通道区中;第一栅极结构包覆第一通道部件并位于其上。第二全绕式栅极装置包括:第二通道部件以及第二栅极结构,第二通道部件位于第二全绕式栅极装置的通道区中;第二栅极结构包覆第二通道部件并位于其上。两个相邻的第一通道部件之间隔有第一栅极结构的一部分与至少一内侧间隔物结构,且两个相邻的第二通道部件之间只隔有第二栅极结构的一部分。
本发明又一例示性的实施例关于半导体装置的制作方法。半导体装置的制作方法包括:形成层状物堆叠于基板上,且层状物堆叠包括交错的多个第一半导体层与多个第二半导体层;自基板的第一区中的层状物堆叠形成第一鳍状单元;自基板的第二区中的层状物堆叠形成第二鳍状单元;蚀刻第一源极/漏极沟槽,以露出第一鳍状单元中的第一半导体层与第二半导体层的侧壁,并以图案膜遮罩第二鳍状单元;选择性地使第一鳍状单元中的第二半导体层凹陷以形成内侧间隔物凹陷,并以图案膜遮罩第二鳍状单元;沉积内侧间隔物层于内侧间隔物凹陷之中与第二鳍状单元上的图案膜之上;蚀刻第二源极/漏极沟槽,以露出第二鳍状单元中的第一半导体层与第二半导体层的侧壁;以及同时形成第一外延的源极/漏极结构于第一源极/漏极沟槽中,以及第二外延的源极/漏极结构于第二源极/漏极沟槽中。
附图说明
图1A、1B、与1C是本发明一或多个实施例中,具有多重装置区的半导体装置的形成方法的流程图。
图2A至20A与图2B至20B是本发明一或多个实施例中,工件于图1的制作工艺工艺时的剖视图。
附图标记说明如下:
H1:第一高度
H2:第二高度
H3:第三高度
W1:第一宽度
W2:第二宽度
10AN,10BN:n型装置区
10AP,10BP:p型装置区
100:方法
102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136:步骤
200:工件
202:基板
204:外延堆叠
206,208:外延层
210:鳍状单元
210A:第一鳍状单元
210B:第二鳍状单元
212:浅沟槽隔离结构
218A:第一源极/漏极沟槽
218BN:第二源极/漏极沟槽
218BP:第三源极/漏极沟槽
222:虚置栅极堆叠
222A:第一虚置栅极堆叠
222B:第二虚置栅极堆叠
224:虚置介电层
226:虚置电极层
228:硬遮罩
230:氧化物层
232:氮化物层
234:栅极间隔物
234-1:第一栅极间隔物
234-2:第二栅极间隔物
234-3:第三栅极间隔物
235:第一鳍状物侧壁
236:内侧间隔物凹陷
237:第二鳍状物侧壁
239:第三鳍状物侧壁
240:第一内侧间隔物层
241:内侧间隔物结构
242:第二内侧间隔物层
244N:n型的外延的源极/漏极结构
244P:p型的外延的源极/漏极结构
245N:第一初始层
245P:第二初始层
246:接点蚀刻停止层
248:层间介电层
250:金属栅极堆叠
302:第一图案膜
304:第一光致抗蚀剂层
305:第一辅助光致抗蚀剂层
306:第二图案膜
308:第二光致抗蚀剂层
309:第二辅助光致抗蚀剂层
400:通道区
500:源极/漏极区
1000A:第一装置区
1000B:第二装置区
具体实施方式
下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件与排列的实施例用以简化本发明内容而非局限本发明。举例来说,形成第一构件于第二构件上的叙述包含两者直接接触的实施例,或两者之间隔有其他额外构件而非直接接触的实施例。此外,本发明实施例的结构形成于另一结构上、连接至另一结构、及/或耦接至另一结构中,结构可直接接触另一结构,或可形成额外结构于结构及另一结构之间(即结构未接触另一结构)。此外,本发明的多个实例可重复采用相同标号以求简洁,但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外,本发明实施例的结构形成于另一结构上、连接至另一结构、及/或耦接至另一结构中,结构可直接接触另一结构,或可形成额外结构于结构及另一结构之间。此外,空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件,而非局限于图示方向。元件亦可转动90度或其他角度,因此方向性用语仅用以说明图示中的方向。此外,当数值或数值范围的描述有“约”、“近似”、或类似用语时,除非特别说明否则其包含所述数值的+/-10%。举例来说,用语“约5nm”包含的尺寸范围介于4.5nm至5.5nm之间。
本发明实施例涉及多栅极晶体管与制作方法,更特别涉及在制作全绕式栅极晶体管时形成内侧间隔物于半导体装置的不同装置区中。
多栅极晶体管的栅极结构形成于通道区的至少两侧上。多栅极装置可包含p型金属氧化物半导体装置或n型金属氧化物半导体装置。多栅极晶体管的例子包括鳍状场效晶体管(由于其鳍状结构)以及全绕式栅极装置。全绕式栅极装置包括栅极结构或其部分形成于通道区的四侧上(比如围绕通道区的一部分)的任何装置。本发明实施例的通道区可位于纳米线通道区、棒状通道、纳米片通道、纳米结构通道、柱状通道、及/或其他合适的通道设置中。本发明实施例的装置可具有与单一的连续栅极结构相关的一或多个通道区(如纳米线、纳米片、纳米结构)。然而本技术领域中普通技术人员应理解本发明实施例中的技术可用于单一通道(如单一纳米线、单一纳米片、或单一纳米结构),或者任何数目的通道。本技术领域中普通技术人员应理解,半导体装置的其他例子可得益于本发明实施例。
随着鳍状场效晶体管中的鳍状物宽度尺寸缩小,通道宽度变化可能会造成不想要的变化与迁移率损失。研究全绕式栅极晶体管以取代鳍状场效晶体管。在全绕式栅极晶体管中,晶体管的栅极完全围绕通道以包覆通道。此晶体管的优点为以栅极改善通道的静电控制,其亦可缓解漏电流的问题。全绕式栅极晶体管包括多种间隔物,比如内侧间隔物与栅极间隔物(又称作外侧间隔物、顶间隔物、或主要间隔物)。内侧间隔物用于降低电容并避免栅极结构与源极/漏极结构之间的漏电流。全绕式栅极晶体管中的内侧间隔物整合亦面对挑战。举例来说,定义鳍状物主动区的源极/漏极沟槽的鳍状物侧壁(其含有多个纳米结构),已用于避免相邻的外延的源极/漏极结构合并,特别在鳍状物主动区的宽度与空间缩小时。当鳍状主动区的宽度缩小至特定等级,比如小于约16nm或约14nm,形成内侧间隔物的工艺可能会造成内侧间隔物材料沉积至源极/漏极沟槽中。在将沉积于内侧间隔物凹陷中的源极/漏极沟槽中的内侧间隔物材料移除时,可能难以避免损伤其他结构。源极/漏极沟槽中未移除的内侧间隔物材料,可阻碍或甚至避免形成外延的源极/漏极结构于源极/漏极沟槽中,造成有缺陷的外延的源极/漏极结构。本发明实施例提供选择性内侧间隔物的实施方式,其中内侧间隔物实施在含有第一鳍状物宽度的装置的第一装置区中,但不实施于含有第二鳍状物宽度的装置的第二装置区中,且第二鳍状物宽度小于第一鳍状物宽度。在一些应用中,第一装置区适用于逻辑装置,而第二装置区适用于存储器装置如静态随机存取存储器装置。
图1A至1C是形成半导体装置的方法100,且半导体装置具有多栅极装置的多个装置区。此处所述的用语“多栅极装置”指的是具有至少一些栅极材料于装置的至少一通道的多侧上的装置(如半导体装置)。在一些例子中,多栅极装置可视作全绕式栅极装置,其具有栅极材料于装置的至少一通道的至少四侧上。通道区可视作纳米线、纳米片、纳米结构、通道部件、或半导体通道部件,其可包含多种几何形状(比如圆柱状、棒状、或片状)与多种尺寸的通道区。
如此处所述的例示性装置与其他方法的实施例,应理解图2A至20A与图2B至20B所示的工件200的部分的制作方法可为互补式金属氧化物半导体技术工艺流程,因此此处只简述一些工艺。完成制作工艺后,可制作工件200至半导体装置中。在此意义下,用语工件200与半导体装置可交换使用。此外,例示性的半导体装置可包含多种其他装置与结构,比如其他型态的装置(包括额外晶体管、双极性接面晶体管、电阻、电容、电感、二极管、熔丝、静态随机存取存储器、及/或其他逻辑单元、或类似物),但简化半导体装置的说明以利理解本发明实施例的发明概念。在一些实施例中,例示性装置包括多个半导体装置(如晶体管),比如n型全绕式栅极晶体管、p型全绕式栅极晶体管、p型场效晶体管、n型场效晶体管、或类似物,且其可内连线。此外,值得注意的是,方法100的工艺步骤包含搭配图2A至19B的任何说明,但应理解此处提供的方法与例示性附图仅用以举例而非限制本发明实施例至权利要求未实际记载处。
附图末尾为A如图2A至20A,显示工件200(或半导体装置)的第一装置区的部分剖视图。附图末尾为B如图2B至20B,显示工件200的第二装置区的部分剖视图。如下所述,第一装置区与第二装置区中的全绕式栅极晶体管可具有不同结构、可由不同的形成工艺所形成、及/或具有不同应用。在图2A至20A的每一图中,沿着X方向的至少一剖视图位于左侧,而沿着Y方向的剖视图位于右侧。在图2B至20B的每一图中,沿着X方向的至少一剖视图位于左侧,而沿着Y方向的剖视图位于右侧。
如图1A、2A与2B所示,方法100的步骤102形成第一鳍状单元210A于第一装置区1000A中,并形成第二鳍状单元210B于第二装置区1000B中。第一装置区1000A与第二装置区1000B均位于工件200中。工件200包括基板202。在一些实施例中,基板202可为半导体基板如硅基板。基板202可包含多种层状物,比如形成于半导体基板上的导电或绝缘层。基板202可包含多种掺杂设置,端视本技术领域已知的设计需求而定。举例来说,可形成不同的掺杂轮廓(如n型阱或p型阱)于基板202上的区域中,且区域设计为用于不同装置型态(比如n型全绕式栅极晶体管或p型全绕式栅极晶体管)。合适掺杂可包含离子注入掺质及/或扩散工艺。基板202可具有隔离结构夹设于区域之间,且区域提供不同的装置型态。基板202亦可包含其他半导体如锗、碳化硅、硅锗、或钻石。在其他实施例中,基板202可包含半导体化合物及/或半导体合金。此外,基板202可视情况包含外延层,可具有应力以增进效能、可包含绝缘层上硅结构、及/或可具有其他合适的增进结构。在方法100的一实施例中,可进行反击穿注入。可在装置通道区下的区域进行反击穿注入,以避免击穿或产生不想要的扩散。
第一鳍状单元210A与第二鳍状单元210B实质上自基板202上的外延堆叠204形成。在一些实施例中,形成于基板202上的外延堆叠204包括第一半导体组成的外延层206,以及夹设于外延层206之间的第二半导体组成的外延层208。外延堆叠204亦可视作层状物的堆叠。第一半导体组成与第二半导体组成可不同。在一实施例中,外延层206为硅锗,而外延层208为硅。然而其他实施例亦属可能,比如第一组成与第二组成具有不同的氧化速率及/或蚀刻选择性。在一些实施例中,外延层206包括硅锗,而外延层208包括硅。
值得注意的是,图2A与2B显示五个外延层206与四个外延层208交错配置,但此仅用于说明目的而非局限本发明实施例至权利要求未实际记载处。应理解的是,可形成任何数目的外延层于外延堆叠204中。层状物数目取决于用于工件200的通道所需的数目。在一些实施例中,外延层208的数目介于2至10之间。
在一些实施例中,每一外延层206的厚度为2nm至约6nm,比如特定例子中的3nm。外延层206可具有实质上一致的厚度。在一些实施例中,每一外延层208的厚度为约6nm至约12nm,比如特定例子中的9nm。在一些实施例中,外延堆叠204的外延层208具有实质上一致的厚度。如下详述,外延层208或其部分可作为后续形成的多栅极装置的通道部件,其厚度选择取决于装置效能考量。通道区中的外延层206最后会被移除,且用于定义相邻的通道区(用于后续形成的多栅极装置)之间的垂直距离,且外延层206的厚度取决于装置效能考量。综上所述,外延层206亦可视作牺牲层,而外延层208亦可视作通道层。
举例来说,外延成长外延堆叠204的层状物的方法可为分子束外延工艺、有机金属化学气相沉积工艺、及/或其他合适的外延成长工艺。在一些实施例中,外延成长的层状物(如外延层208)与基板202包括相同材料。在一些实施例中,外延层206与208的材料与基板202的材料不同。如上所述,在至少一些例子中,外延层206包括外延成长的硅锗层,而外延层208包括外延成长的硅层。在其他实施例中,外延层206与208可包含其他材料如锗、半导体化合物(如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟)、半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、及/或磷砷化镓铟)、或上述的组合。如上所述,外延层206与208的材料选择依据为提供不同的氧化特性与蚀刻选择性。在一些实施例中,外延层206与208为实质上无掺质(比如非固有的掺质浓度为约0cm-3至约1x1017cm-3)。举例来说,在外延成长工艺时不刻意进行掺杂。
在步骤102中,图案化基板202上的外延堆叠204,以形成第一鳍状单元210A于第一装置区1000A中,并形成第二鳍状单元210B于第二装置区1000B中。第一鳍状单元210A与第二鳍状单元210B自基板202延伸。在一些实施例中,图案化步骤亦蚀刻至基板202中,使第一鳍状单元210A与第二鳍状单元210B的每一者包括自基板202形成的下侧部分与自外延堆叠204形成的上侧部分。上侧部分包括含有外延层206与208的外延堆叠204的每一外延层。第一鳍状单元210A与第二鳍状单元210B的制作方法可采用合适工艺,包括双重图案化或多重图案化工艺。一般而言,双重图案化或多重图案化工艺结合光微影与自对准工艺,其产生的图案间距小于采用单一的直接光微影工艺所得的图案间距。举例来说,一实施例形成牺牲层于基板上,并采用光微影工艺图案化牺牲层。可采用自对准工艺,沿着图案化的牺牲层侧部形成间隔物。接着移除牺牲层,而保留的间隔物(或芯)之后可用于蚀刻外延堆叠204以图案化第一鳍状单元210A与第二鳍状单元210B。蚀刻工艺可包含干蚀刻、湿蚀刻、反应性离子蚀刻、及/或其他合适工艺。
在图2A与2B所示的一些实施例中,形成于第一装置区1000A与第二装置区1000B中的装置具有不同用途。在一些实施方式中,第一装置区1000A用于较快开关速度与较大驱动电流的应用如逻辑装置。第二装置区1000B用于较高封装密度的应用如存储器装置。逻辑装置的例子包括反相器、NAND、NOR、AND、OR、或触发装置。存储器装置的例子包括静态随机存取存储器、动态随机存取存储器、或快闪装置。为了符合这些应用,第一装置区1000A中的每一第一鳍状单元210A的第一宽度W1介于约14nm至约30nm之间(比如介于16nm至30nm之间),且第二装置区1000B中的每一第二鳍状单元210B的第二宽度W2介于约6nm至约16nm之间(比如介于6nm至14nm之间)。如上所述,开关速度是第一装置区1000A中装置的重要特性,且不希望因源极/漏极与栅极之间的寄生电容造成延迟。然而第二装置区1000B中装置的关键需求并非速度,且源极/漏极与栅极之间的寄生电容所造成的延迟问题较小。形成内侧间隔物为降低寄生电容的技术之一。然而当鳍状物宽度缩小至介于约14nm至约16nm之间或更小时,内侧间隔物材料可能沉积于源极/漏极沟槽中,且在不损伤其他结构的情况下无法完全移除内侧间隔物材料。本发明实施例的特征之一,省略第二装置区1000B中的内侧间隔物(若此省略可减少第二装置区1000B中的装置缺陷并改善装置可信度)。举例来说,若第二装置区1000B中装置的鳍状物宽度小于临界值,则省略形成内侧间隔物于密集排列的第二装置区1000B中的步骤,因为内侧间隔物的坏处多于好处。临界值取决于多种工艺条件与设计性质。临界值的一例介于约14nm至约16nm之间。
如图2A与2B所示,在形成第一鳍状单元210A与第二鳍状单元210B之后,形成隔离结构于相邻的第一鳍状单元210A之间以及相邻的第二鳍状单元210B之间。隔离结构亦可视作浅沟槽隔离结构212。举例来说,一些实施例先沉积介电层于基板202上,以将介电材料填入鳍状单元(如第一鳍状单元210A与第二鳍状单元210B)之间的沟槽。在一些实施例中,介电层可包括氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃、低介电常数的介电层、上述的组合、及/或其他合适材料。在多种例子中,介电层的沉积方法可为化学气相沉积工艺、次压化学气相沉积工艺、可流动的化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺、及/或其他合适工艺。接着薄化与平坦化沉积的介电材料,比如进行化学机械研磨工艺。接着进一步使平坦化的介电层凹陷以形成浅沟槽隔离结构212,且凹陷方法可为干蚀刻工艺、湿蚀刻工艺、及/或上述的组合。第一鳍状单元210A与第二鳍状单元210B隆起高于浅沟槽隔离结构212。在一些实施例中,介电层(与后续形成的浅沟槽隔离结构212)可包含多层结构,比如具有一或多个衬垫层。
在一些实施例中,方法100的步骤102亦可形成介电鳍状物(未图示)。在形成介电鳍状物的工艺流程中,在浅沟槽隔离结构212中形成狭缝,其延伸方向平行于第一鳍状单元210A,接着沉积介电鳍状物材料至狭缝中。介电鳍状物材料与形成浅沟槽隔离结构212的介电材料不同。这可选择性地蚀刻浅沟槽隔离结构212所用的介电层,并保留隆起高于浅沟槽隔离结构212的介电鳍状物。在一些实施例中,介电鳍状物材料可包括氮化硅、碳氮化硅、碳化硅、氧化铝、氧化锆、或其他合适材料。在采用介电鳍状物的实施例中,介电鳍状物夹设于第一鳍状单元210A之间,或夹设于第二鳍状单元210B之间,以分开相邻装置的源极/漏极结构。介电鳍状物亦可视作虚置鳍状物或混合鳍状物。在一些其他实施例中,在栅极切割工艺时可移除介电鳍状物的上侧部分,并置换为反相材料结构(其可与介电鳍状物类似或不同)。一旦形成介电鳍状物,其可限制外延的源极/漏极结构形成,并避免相邻的外延的源极/漏极结构之间产生不想要的合并。
如图1A、2A与2B所示,方法100的步骤104形成第一虚置栅极堆叠222A于第一鳍状单元210A的通道区400上,并形成第二虚置栅极堆叠222B于第二鳍状单元210B的通道区400上。为简化标示,第一鳍状单元210A与第二鳍状单元210B可一起视作鳍状单元210。类似地,第一虚置栅极堆叠222A与第二虚置栅极堆叠222B可一起视作虚置栅极堆叠222。在一些实施例中,采用栅极置换工艺(或栅极后制工艺),其中第一虚置栅极堆叠222A与第二虚置栅极堆叠222B作为高介电常数的介电层与金属栅极的堆叠所用的占位物,之后可移除并置换为高介电常数的介电层与金属栅极的堆叠。其他工艺与设置亦属可能。在一些实施例中,第一虚置栅极堆叠222A形成于基板202上且至少部分地位于第一鳍状单元210A上,而第二虚置栅极堆叠222B形成于基板202上且至少部分地位于第二鳍状单元210B上。第一鳍状单元210A位于第一虚置栅极堆叠222A之下的部分,为第一鳍状单元210A的通道区400。类似地,第二鳍状单元210B位于第二虚置栅极堆叠222B之下的部分,为第二鳍状单元210B的通道区400。第一虚置栅极堆叠222A与第二虚置栅极堆叠222B亦可定义与通道区400相邻并位于通道区400两侧上的源极/漏极区500。
在所述实施例中,步骤104先形成虚置介电层224于鳍状单元210(包括第一鳍状单元210A与第二鳍状单元210B)上。在一些实施例中,虚置介电层224可包含氧化硅、氮化硅、高介电常数的介电材料、及/或其他合适材料。在多种例子中,虚置介电层224的沉积方法可为化学气相沉积工艺、次压化学气相沉积工艺、可流动的化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺、或其他合适工艺。举例来说,虚置介电层224可用于避免后续工艺(比如形成虚置栅极堆叠的工艺)损伤鳍状单元210。步骤104接着形成虚置栅极堆叠222的其他部分,包括虚置电极层226与硬遮罩228(其可包含氧化物层230与氮化物层232)。在一些实施例中,虚置栅极堆叠222的形成方法可为多种工艺步骤,比如沉积层状物、图案化、与蚀刻,以及其他合适工艺步骤。沉积层状物的例示性工艺包括低压化学气相沉积、化学气相沉积、电浆辅助化学气相沉积、物理气相沉积、原子层沉积、热氧化、电子束蒸镀、其他合适的沉积技术、或上述的组合。举例来说,图案化工艺可包含微影工艺(如光微影或电子束微影),其可进一步包括涂布光致抗蚀剂(如旋转涂布)、软烘烤、对准光掩模、曝光、曝光后烘烤、显影光致抗蚀剂、冲洗、干燥(如旋干及/或硬烘烤)、其他合适的微影技术、及/或上述的组合。在一些实施例中,蚀刻工艺可包括干蚀刻(如反应性离子蚀刻)、湿蚀刻、及/或其他蚀刻方法。在一些实施例中,虚置电极层226可包含多晶硅。在一些实施例中,硬遮罩228包括氧化物层230如垫氧化物层,其可包含氧化硅。在一些实施例中,硬遮罩228包括氮化物层232如垫氮化物层,其可包含氮化硅、氮氧化硅、及/或碳化硅。
如图2A与2B所示的一些实施例,在形成虚置栅极堆叠222之后,自第一鳍状单元210A的源极/漏极区500移除虚置介电层224。因此可移除虚置电极层226未覆盖的虚置介电层224。移除工艺可包含湿蚀刻、干蚀刻、及/或上述的组合。选择蚀刻工艺以选择性地蚀刻虚置介电层224,而实质上不蚀刻鳍状单元210、硬遮罩228、与虚置电极层226。
如图1A、2A与2B所示,方法100的步骤106形成栅极间隔物234于第一虚置栅极堆叠222A与第二虚置栅极堆叠222B的侧壁上。在一些实施例中,形成栅极间隔物234所用的间隔物材料可顺应性地沉积于工件200上,包括沉积于虚置栅极堆叠222(包括第一虚置栅极堆叠222A与第二虚置栅极堆叠222B)的上表面与侧壁上,以形成间隔物材料层。此处所述的用语“顺应性”指的是层状物在多种区域上具有实质上一致的厚度。栅极间隔物234可具有单层结构或包含多层。在图2A与2B所示的一些实施例中,栅极间隔物234包括第一栅极间隔物234-1、第二栅极间隔物234-2、与第三栅极间隔物234-3。在这些实施例中,第一栅极间隔物234-1可包含碳氮化硅,第二栅极间隔物234-2可包含碳氧化硅或其他低介电常数的介电层,且第三栅极间隔物234-3可包含碳氮氧化硅、氮化硅、或介电常数高于第二栅极间隔物234-2的材料。此外在这些实施例中,与第一栅极间隔物234-1与第二栅极间隔物234-2相较,第三栅极间隔物234-3的介电常数与抗蚀刻性较高,且可作为遮罩膜或图案膜。在之后的工艺中,可部分地或完全移除较高介电常数较高的第三栅极间隔物234-3,并保留介电常数较低的第一栅极间隔物234-1及/或第二栅极间隔物234-2。在一些其他实施例中,栅极间隔物234可具有单层的介电材料如氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅、碳氧化硅、碳氮氧化硅、及/或上述的组合。间隔物材料层可沉积于虚置栅极堆叠222上(包括第一虚置栅极堆叠222A与第二虚置栅极堆叠222B),其采用的工艺可为化学气相沉积工艺、次压化学气相沉积工艺、可流动的化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺、或其他合适工艺。接着在非等向蚀刻工艺中回蚀刻间隔物材料层,以形成栅极间隔物234。非等向蚀刻工艺可露出与虚置栅极堆叠222相邻但不被虚置栅极堆叠222覆盖的鳍状单元210(包含第一鳍状单元210A与第二鳍状单元210B),比如源极/漏极区中的鳍状单元210。可由非等向蚀刻工艺完全移除直接位于虚置栅极堆叠222上的间隔物材料层的部分,而栅极间隔物234保留于虚置栅极堆叠222的侧壁上。
如图1A、3A与3B所示,方法100的步骤108使第一鳍状单元210A的源极/漏极区500凹陷,以形成第一源极/漏极沟槽218A。虽然未图示,但可采用光微影工艺与至少一硬遮罩进行步骤108的步骤。在一些实施例中,蚀刻第一虚置栅极堆叠222A与栅极间隔物234未覆盖的第一鳍状单元210A的部分,以形成第一源极/漏极沟槽218A,且蚀刻方法可为干蚀刻或合适的蚀刻工艺。举例来说,干蚀刻工艺可实施含氧气体、含氟气体(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化碳、及/或三氯化硼)、含溴气体(如溴化氢及/或溴仿)、含碘气体、其他合适气体及/或电浆、及/或上述的组合。在图3A与3B所示的一些实施例中,使第一鳍状单元210A的上侧部分凹陷,以露出外延层206(如牺牲层)与外延层208(如通道层)。在一些实施方式中,亦使第一鳍状单元210A的下侧部分的至少一部分凹陷。因此第一源极/漏极沟槽218A可延伸于最底部的外延层206(如牺牲层)之下。完成步骤108之后,第一鳍状单元210A的源极/漏极区500可与浅沟槽隔离结构212的上表面齐平,或低于浅沟槽隔离结构212的上表面。如图3B所示,可由光微影图案化第三栅极间隔物234-3以覆盖第二装置区1000B,并使第一装置区1000A露出以进行步骤108的步骤。定义第一源极/漏极沟槽218A的保留栅极间隔物234,可视作第一鳍状物侧壁235。在一些例子中,第一鳍状物侧壁235的第一高度H1介于约0nm至约40nm之间。
如图1A与4A所示,方法100的步骤110使第一鳍状单元210A的外延层206(如牺牲层)凹陷,以形成内侧间隔物凹陷236于第一装置区1000A中。值得注意的是,在图4B所示的实施例中,图案化的第三栅极间隔物234-3维持遮罩第二装置区1000B,并露出第一装置区1000A以进行步骤110的步骤。在图4A所示的一些实施例中,使第一源极/漏极沟槽218A中露出的外延层206(如牺牲层)选择性与部分地凹陷,以形成内侧间隔物凹陷236,而实质上不蚀刻露出的外延层208(如通道层)。在外延层208(如通道层)基本上为硅而外延层206(如牺牲层)基本上为硅锗的实施例中,使外延层206(如牺牲层)选择性凹陷的方法可包含硅锗氧化工艺与后续的硅锗氧化物移除工艺。在这些实施例中,硅锗氧化工艺可采用臭氧。在一些实施例中,选择性凹陷步骤可为选择性等向蚀刻工艺(比如选择性干蚀刻工艺或选择性湿蚀刻工艺),且可由蚀刻工艺的时间控制外延层206(如牺牲层)的凹陷量。在一些实施例中,选择性干蚀刻工艺可采用一或多种氟为主的蚀刻剂,比如氟气或氢氟碳化物。如图4A所示,内侧间隔物凹陷236自第一源极/漏极沟槽218A向内延伸。在一些实施例中,选择性湿蚀刻工艺可包含氢氟酸或氢氧化铵的蚀刻剂。如图4A所示,内侧间隔物凹陷236自第一源极/漏极沟槽218A向内延伸。
如图1A、5A与5B所示,方法100的步骤112沉积第一内侧间隔物层240于第一装置区1000A与第二装置区1000B上。第一内侧间隔物层240的沉积方法可为化学气相沉积、电浆辅助化学气相沉积、低压化学气相沉积、原子层沉积、或其他合适方法。在一些例子中,第一内侧间隔物层240的厚度介于约1nm至约3nm之间。如图5A所示的第一装置区1000A,第一内侧间隔物层240用于在拉回(回蚀刻)内侧间隔物时,保护栅极间隔物234、硬遮罩228、与外延层208(如通道层)免于损伤。如图5B所示的第二装置区1000B,第一内侧间隔物层240沉积于第三栅极间隔物234-3上。在一些实施方式中,第一内侧间隔物层240的组成可为金属氧化物或富碳的碳氮化硅。此处的金属氧化物可包含氧化铝、氧化锆、氧化钽、氧化钇、氧化钛、氧化镧、或其他合适的金属氧化物。富碳的碳氮化硅之碳浓度大于5%。在图5A所示的实施例中,第一内侧间隔物层240可顺应性地沉积于硬遮罩228的上表面、栅极间隔物234的上表面与侧壁、以及第一源极/漏极沟槽218A中露出的基板202的部分上。在形成介电鳍状物的实施例中,第一内侧间隔物层240亦可顺应性地沉积于介电鳍状物的上表面与侧壁上。
如图1A、6A与6B所示,方法100的步骤114沉积第二内侧间隔物层242于第一装置区1000A与第二装置区1000B上。在一些实施例中,第二内侧间隔物层242的沉积方法可为化学气相沉积、电浆辅助化学气相沉积、低压化学气相沉积、原子层沉积、或其他合适方法。在一些例子中,第二内侧间隔物层242的厚度可介于约3nm至约5nm之间。在图6A所示的第一装置区1000A中,由于内侧间隔物凹陷236未填有第一内侧间隔物层240,第二内侧间隔物层242亦沉积至内侧间隔物凹陷236中。在图6B所示的第二装置区1000B中,第二内侧间隔物层242可沉积于第一内侧间隔物层240上。在一些实施方式中,第二内侧间隔物层242的组成可为氧化硅、碳氮氧化硅、碳氧化硅、或其他低介电常数材料。第二内侧间隔物层242可为孔洞状,以进一步降低介电常数。在一些例子中,第二内侧间隔物层242的碳含量,小于第一内侧间隔物层240的碳含量。
如图1B、7A与7B所示,方法100的步骤116拉回(回蚀刻)第二内侧间隔物层242。在一些实施例中,非等向且选择性地回蚀刻第二内侧间隔物层242,直到自硬遮罩228的上表面、栅极间隔物234的上表面与侧壁、第一源极/漏极沟槽218A中露出的基板202的部分、第一装置区1000A中的介电鳍状物(若存在)的上表面与侧壁、与第二装置区1000B中的第一内侧间隔物层240完全移除第二内侧间隔物层242。如上所述,第一内侧间隔物层240的组成与第二内侧间隔物层242的组成不同,因此可选择性地蚀刻第二内侧间隔物层242,而第一内侧间隔物层240的蚀刻速率慢。在一些实施方式中,步骤116中的第二内侧间隔物层242与第一内侧间隔物层240的蚀刻选择性大于5。在一些实施方式中,步骤118进行的等向蚀刻可采用氢氟酸、氟气、氢气、氨、三氟化氮、或其他含氟蚀刻剂。在图8A与8B所示的一些实施例中,蚀刻内侧间隔物凹陷236中的第二内侧间隔物层242,使第二内侧间隔物层242的外侧表面与栅极间隔物234的侧壁不共平面。在本发明其他实施例中,可省略形成第一内侧间隔物层240的步骤,且第一装置区1000A中的装置可只包含第二内侧间隔物层242于内侧间隔物凹陷236中。
如图1B、8A与8B所示,方法100的步骤118沉积第一图案膜302于第一装置区1000A与第二装置区1000B上。在一些实施例中,由下述内容可清楚得知,步骤120可图案化第一图案膜302,以作为对不同型态的装置进行不同工艺处理时的遮罩。在一些实施例中,第一图案膜302可包含氮化硅或碳氮化硅。此配置之后可选择性移除第一图案膜302,而实质上不损伤第一内侧间隔物层240。在一些实施方式中,第一图案膜302的沉积方法可采用化学气相沉积、电浆辅助化学气相沉积、低压化学气相沉积、原子层沉积、或其他合适方法。在一些例子中,第一图案膜302的厚度可介于约3nm至约5nm之间。
如图1B、9A与9B所示,方法100可图案化第一图案膜302以露出第一装置区1000A中的n型装置区10AN。在图9A所示的一些实施例中,采用光微影技术图案化第一图案膜302。第一光致抗蚀剂层304沉积于工件200上的方法,可为旋转涂布。接着以图案化射线曝光、曝光后烘烤、与显影第一光致抗蚀剂层304,以形成图案化的第一光致抗蚀剂层304,其露出第一装置区1000A中的n型装置区10AN,并遮蔽p型装置区10AP与第二装置区1000B。接着可由合适的蚀刻工艺移除n型装置区10AN上露出的第一图案膜302,以露出内侧间隔物凹陷236中的第一内侧间隔物层240与第二内侧间隔物层242。
如图1B、10A与10B所示,方法100的步骤120图案化第一图案膜302以露出第二装置区1000B中的n型装置区10BN。在图10A所示的一些实施例中,在步骤120开始之前,先沉积第一辅助光致抗蚀剂层305以遮罩第一装置区1000A中露出的n型装置区10AN。为简化附图,遮罩第一装置区1000A的光致抗蚀剂层标示为304/305。接着进行光微影工艺,以露出第二装置区中的n型装置区10BN。
如图1B、11A与11B所示,方法100的步骤122使第二装置区1000B中的n型装置区10BN的源极/漏极区500凹陷,以形成第二源极/漏极沟槽218BN。在一些实施例中,蚀刻第二虚置栅极堆叠222B与栅极间隔物234未覆盖的第二鳍状单元210B的部分,以形成第二源极/漏极沟槽218BN,且蚀刻方法可为干蚀刻或合适的蚀刻工艺。举例来说,干蚀刻工艺可实施含氧气体、含氟气体(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化碳、及/或三氯化硼)、含溴气体(如溴化氢及/或溴仿)、含碘气体、其他合适气体及/或电浆、及/或上述的组合。在图11B所示的一些实施例中,使第二鳍状单元210B的上侧部分凹陷,以露出外延层206(如牺牲层)与外延层208(如通道层)。在一些实施例中,亦使第二鳍状单元210B的下侧部分的至少一部分凹陷。因此第二源极/漏极沟槽218BN可延伸于最底部的外延层206(如牺牲层)之下。定义第二源极/漏极沟槽218BN的保留栅极间隔物234,可视作第二鳍状物侧壁237。在一些例子中,第二鳍状物侧壁237的第二高度H2介于约15nm至约40nm之间。
在本发明一些实施例中(未图示),可非等向且选择性地修整图11B中的第二装置区1000B中露出的外延层206(如牺牲层)与外延层208(如通道层),直到露出的外延层206(如牺牲层)与外延层208(如通道层)的侧壁凹陷而不再与栅极间隔物234的侧壁齐平。接着可外延成长硅层于露出的外延层206(如牺牲层)与外延层208(如通道层)之凹陷侧壁上,以形成再成长的外延硅层,其实质上与第二装置区1000B中的n型装置区10BN中的栅极间隔物234的侧壁齐平。在一些实施方式中,再成长的外延硅层可掺杂碳以用于n型装置区10BN。在这些实施例中,修整工艺有助于增加n型外延的源极/漏极结构体积,以确保施加足够的应力至通道部件上,且再成长的外延硅层可降低漏电流并增加通道部件的可信度。
如图1B、12A与12B所示,方法100的步骤124移除第一装置区1000A中的n型装置区10AN与第二装置区1000B中的n型装置区10BN上的第一内侧间隔物层240。在一些实施例中,第一装置区1000A中的n型装置区10AN与第二装置区1000B中的n型装置区10BN上的第一内侧间隔物层240的移除方法,可为湿式清洁工艺或合适方法。在一些实施方式中,湿式清洁工艺可采用硫酸与过氧化氢的混合物溶液、RCA标准清洁溶液-1、或RCA标准清洁溶液-2。在一些例子中,步骤124的湿式清洁工艺同时移除第一装置区1000A中的n型装置区10AN与第二装置区1000B中的n型装置区10BN上的第一内侧间隔物层240,以及第一光致抗蚀剂层304与第一辅助光致抗蚀剂层305。在其他例子中,步骤124的湿式清洁工艺为独立工艺,其于移除第一光致抗蚀剂层304与第一辅助光致抗蚀剂层305的独立工艺之后进行。值得注意的是,第一图案膜302维持遮罩第一装置区1000A中的p型装置区10AP与第二装置区1000B中的p型装置区10BP上的第一内侧间隔物层240,因此步骤124不会蚀刻第一内侧间隔物层240。
如图1B、13A与13B所示,方法100的步骤126形成n型的外延的源极/漏极结构244N于第一装置区1000A中的n型装置区10AN以及第二装置区1000B中的n型装置区10BN的源极/漏极区500中。步骤126所用的合适外延工艺包括化学气相沉积技术(如气相外延及/或超高真空化学气相沉积)、分子束外延、及/或其他合适工艺。外延成长工艺可采用气相或液相的前驱物,其与基板202及外延层208(如通道层)的组成作用。在图14A与14B所示的实施例中,n型外延源极/漏极结构244N直接接触第一装置区1000A中的第一源极/漏极沟槽218A中与第二装置区1000B中的第二源极/漏极沟槽218BN中露出的基板202的部分与外延层208(如通道层)。在这些实施例中,n型的外延的源极/漏极结构244N不直接接触第一装置区1000A中的外延层206(如牺牲层),因为第一内侧间隔物层240与第二内侧间隔物层242位于内侧间隔物凹陷236中。n型的外延的源极/漏极区244N直接接触沉积于内侧间隔物凹陷236中的第一内侧间隔物层240与第二内侧间隔物层242。第二装置区1000B所用的设置不同。第二装置区1000B中的n型的外延的源极/漏极结构244N可直接接触第二装置区1000B中的外延层206(如牺牲层),因为内侧间隔物凹陷不形成在第二装置区1000B中,因此外延层206(如牺牲层)与n型的外延的源极/漏极结构244N之间未隔有第一内侧间隔物层240与第二内侧间隔物层242。在图12A所示的实施例中,具有两个内侧间隔物层,且位于内侧间隔物凹陷236的每一者中的第一内侧间隔物层240与第二内侧间隔物层242,可一起视作内侧间隔物结构241。在每一内侧间隔物结构241中,第一内侧间隔物层240包覆第二内侧间隔物层242,且只露出第二内侧间隔物层242的外部侧壁。在其他实施例中,只有单一的内侧间隔物层,且每一内侧间隔物结构241具有单层结构。
在多种实施例中,n型的外延的源极/漏极结构244N可包含硅、砷化镓、磷砷化镓、磷化硅、或其他合适材料。在n型的外延的源极/漏极结构244N的外延工艺时可进行原位掺杂,以将掺杂物种如n型掺质(比如磷或砷)及/或其他合适掺质(包含上述的组合)导入n型的外延的源极/漏极结构244N。若未原位掺杂n型的外延的源极/漏极结构244N,可进行注入工艺(如接面注入工艺)以掺杂n型的外延的源极/漏极结构244N。在一例示性的实施例中,n型金属氧化物半导体装置中的n型的外延的源极/漏极结构244N包含磷化硅。
在一些实施例中,n型的外延的源极/漏极结构244N可包含多层。在图13A与13B所示的一些实施例中,第一装置区1000A中的n型的外延的源极/漏极结构244N与第二装置区1000B中的n型的外延的源极/漏极结构244N各自包含第一初始层245N。在一些实施例中,第一初始层245N可包含硅与碳,且其形成方法可采用独立的外延工艺。第一初始层245N可作为露出通道部件的工艺所用的蚀刻停止层,且可视作露出线路的停止层。第一初始层245N亦可避免漏电流。如图11B所示的一些其他实施方式,可形成再成长的外延硅层,且可省略第一初始层245N。值得注意的是,由于第一装置区1000A中的内侧间隔物与第一初始层245N的功能类似,因此可省略第一装置区1000A中的第一初始层245N而无任何负面影响。
如图1C、14A与14B所示,方法100的步骤128移除第一图案膜302。在图14A与14B所示的一些实施例中,将沉积于第一装置区1000A中的p型装置区10AP与第二装置区1000B中的p型装置区10BP上的其余第一图案膜302移除。在一些实施例中,可采用合适的干蚀刻工艺或湿蚀刻工艺选,以择择性地移除第一图案膜302。在一些例子中,合适的湿蚀刻工艺可采用磷酸溶液。
如图1C、15A、15B、16A与16B所示,方法100的步骤130形成第二图案膜306于工件200上,以露出第一装置区1000A中的p型装置区10AP。工艺的例子如下述。如图15A与15B所示,沉积第二图案膜306于工件200的第一装置区1000A与第二装置区1000B上。第二图案膜306所用的组成与形成工艺,可与第一图案膜302所用的组成与工艺类似,在此不重述。接着沉积第二光致抗蚀剂层308于第二图案膜306上,并采用光微影技术图案化第二光致抗蚀剂层308,以露出第一装置区1000A中的p型装置区10AP。接着移除第一装置区1000A中的p型装置区10AP上的第二图案膜306的部分,且移除方法可为湿蚀刻、干蚀刻、或合适方法。
如图1C、17A、17B、18A与18B所示,方法100的步骤132使第二装置区1000B中的p型装置区10BP中的第二鳍状单元210B的源极/漏极区500凹陷。在图17A所示的一些实施例中,沉积第二辅助光致抗蚀剂层309,以遮罩第一装置区1000A中露出的p型装置区10AP。接着进行光微影工艺以露出第二装置区1000B中的p型装置区10BP,如图17B所示。在一些实施例中,之后可蚀刻第二虚置栅极堆叠222B与栅极间隔物234未覆盖的第二鳍状单元210B的部分,以形成第三源极/漏极沟槽218BP,且蚀刻方法可为干蚀刻或合适的蚀刻工艺。举例来说,干蚀刻工艺可实施含氧气体、含氟气体(如四氟化碳、六氟化硫、二氟甲烷、氟仿、及/或六氟乙烷)、含氯气体(如氯气、氯仿、四氯化碳、及/或三氯化硼)、含溴气体(如溴化氢及/或溴仿)、含碘气体、其他合适气体及/或电浆、及/或上述的组合。在图18A与18B所示的一些实施例中,使第二鳍状单元210B的上侧部分凹陷,以露出外延层206(如牺牲层)与外延层208(如通道层)。在一些实施方式中,第二鳍状单元210B的下侧部分的至少一部分亦凹陷。因此第三源极/漏极沟槽218BP可延伸于最底部的外延层206(如牺牲层)之下。在进行步骤132之后,第二鳍状单元210B的源极/漏极区500可与浅沟槽隔离结构212的上表面齐平,或低于浅沟槽隔离结构212的上表面。定义第三源极/漏极沟槽218BP的保留栅极间隔物234可视作图18B中的第三鳍状物侧壁239。在一些例子中,第三鳍状物侧壁239的第三高度H3与第二高度H2类似,介于约15nm至约40nm之间。
在图17所示的实施例中,具有两个内侧间隔物层,且位于内侧间隔物凹陷236的每一者中的第一内侧间隔物层240与第二内侧间隔物层242,可一起视作内侧间隔物结构241。在p型装置区10AP中的内侧间隔物结构241的每一者中,第一内侧间隔物层240包覆第二内侧间隔物层242,且只露出第二内侧间隔物层242的一外部侧壁。在其他实施例中,只有单一的内侧间隔物层,且内侧间隔物结构241的每一者具有单层结构。如图17A所示,在形成n型的外延的源极/漏极结构244N之后,n型装置区10AN中的第二内侧间隔物层242的侧壁(未被第一内侧间隔物层240覆盖)接触n型的外延的源极/漏极结构244N或第一初始层245N。
在本发明一些实施例中(未图示),可等向且选择性地修整图17B所示的第二装置区1000B中的p型装置区10BP中露出的外延层206(如牺牲层)与外延层208(如通道层),直到露出的外延层206(如牺牲层)与外延层208(如通道层)的侧壁凹陷而不再与栅极间隔物234的侧壁齐平。接着可外延成长硅层于露出的外延层206(如牺牲层)与外延层208(如通道层)的凹陷侧壁上,以形成再成长的外延硅层,其实质上与栅极间隔物234的侧壁齐平。在一些实施方式中,形成于p型装置区10BP中的再成长外延硅层可掺杂硼。在这些实施例中,修整步骤有助于增加p型的外延的源极/漏极结构的体积,以确保施加足够应力至通道部件上,且再成长的外延硅层可降低漏电流并增加通道部件的可信度。
如图1C、19A与19B所示,方法100的步骤134形成p型的外延的源极/漏极结构244P于第一装置区1000A中的p型装置区10AP与第二装置区1000B中的p型装置区10BP中的源极/漏极区500上。步骤134所用的合适外延工艺包括化学气相沉积技术(如气相外延及/或超高真空化学气相沉积)、分子束外延、及/或其他合适工艺。外延成长工艺可采用气相及/或液相前驱物,其与基板202、外延层208(如通道层)、或初始层(若存在,比如下述的第二初始层245P)的组成作用。p型外延的源极/漏极结构244P可直接接触基板202、外延层208(如通道层)、外延层206(如牺牲层)、或初始层(若存在,比如下述的第二初始层245P)。由于第二装置区1000B中未实施内侧间隔物,第二装置区1000B中的外延层206(如牺牲层)与外延层208(如通道层)之间未隔有任何内侧间隔物。
在多种实施例中,p型的外延的源极/漏极结构244P可包含硅、锗、砷化铝镓、硅锗、掺杂硼的硅锗、或其他合适材料。在p型的外延的源极/漏极结构244P的外延工艺时可进行原位掺杂,以将掺杂物种如p型掺质(比如硼或二氟化硼及/或包含上述的组合的其他合适掺质)导入p型的外延的源极/漏极结构244P。若未原位掺杂p型的外延的源极/漏极结构244P,可进行注入工艺(如接面注入工艺)以掺杂p型的外延的源极/漏极结构244P。在一例示性实施例中,p型金属氧化物半导体装置中的p型的外延的源极/漏极结构244P包括硼化硅锗。
在一些实施例中,p型的外延的源极/漏极结构244P可包含多层。在图19A与19B所示的一些实施例中,第一装置区1000A中p型的外延的源极/漏极结构244P与第二装置区1000B中p型的外延的源极/漏极结构244P各自包含第二初始层245P。在一些实施例中,第二初始层245P包含硅与硼,且其形成方法可采用独立的外延工艺。在一些实施方式中,可修整第一源极/漏极沟槽218A与第三源极/漏极沟槽218BP中露出的外延层206(如牺牲层)与外延层208(如通道层),且可进行硅的再成长工艺以形成第二初始层245P。第二初始层245P可作为露出通道部件的工艺所用的蚀刻停止层,因此可视作露出线路的停止层。第二初始层245P亦可避免漏电流。在一些其他实施方式中,如搭配图17B所述的内容,可形成再成长的外延硅层并可省略第二初始层245P。值得注意的是,由于第一装置区1000A中的内侧间隔物与第二初始层245P的功能类似,可在第一装置区1000A中省略第二初始层245P而不会有任何负面影响。
如图19A所示,在形成p型的外延的源极/漏极结构244P之后,p型装置区10AP中的第二内侧间隔物层242的侧壁(未被第一内侧间隔物层240覆盖)接触p型的外延的源极/漏极结构244P或第二初始层245P。
如图1C、20A与20B所示,方法100的步骤136进行后续工艺。如图20A与20B所示,这些后续工艺可包括沉积接点蚀刻停止层246、沉积层间介电层248、移除第一虚置栅极堆叠222A与第二虚置栅极堆叠222B、露出外延层208(如通道层)如通道部件、形成金属栅极堆叠250、以及平坦化工件200。在一些实施例中,在形成层间介电层248之前但在移除第二图案膜306之后,形成接点蚀刻停止层246。在一些例子中,接点蚀刻停止层246包括氮化硅层、氧化硅层、氮氧化硅层、及/或本技术领域已知的其他材料。接点蚀刻停止层246的形成方法可为原子层沉积、电浆辅助化学气相沉积工艺、及/或其他合适的沉积或氧化工艺。接着沉积层间介电层248于接点蚀刻停止层246上。在一些实施例中,层间介电层248包括的材料可为四乙氧基硅烷的氧化物、未掺杂的硅酸盐玻璃、掺杂的氧化硅(如硼磷硅酸盐玻璃、掺杂氟的硅酸盐玻璃、磷硅酸盐玻璃、或硼硅酸盐玻璃)、及/或其他合适的介电材料。层间介电层248的沉积方法可为电浆辅助化学气相沉积工艺或其他合适的沉积技术。在一些实施例中,在形成层间介电层248之后,可退火工件200以改善层间介电层248的完整性。
在一些例子中,沉积层间介电层248之后可进行平坦化工艺,以移除多余的介电材料。举例来说,平坦化工艺包含化学机械研磨工艺,其移除虚置栅极堆叠222(包含第一虚置栅极堆叠222A与第二虚置栅极堆叠222B)之上的层间介电层248的部分(以及接点蚀刻停止层,若存在),并平坦化工件200的上表面。在一些实施例中,化学机械研磨工艺亦移除硬遮罩228并露出虚置电极层226。露出虚置电极层226之后,可移除虚置电极层226并露出外延层208(如通道层)。
在一些实施例中,移除虚置栅极堆叠(包括第一虚置栅极堆叠222A与第二虚置栅极堆叠222B),以形成栅极沟槽于通道区400上。接着可形成金属栅极堆叠250于栅极沟槽中,如下所述。移除虚置栅极堆叠222的方法可包含一或多道蚀刻工艺,其对虚置栅极堆叠222的材料具有选择性。举例来说,移除虚置栅极堆叠222的方法可采用选择性湿蚀刻、选择性干蚀刻、或上述的组合,其对虚置电极层226具有选择性。栅极沟槽中露出鳍状单元210(如第一鳍状单元210A与第二鳍状单元210B)的外延层206与208。
在移除虚置栅极堆叠222之后,方法100可包含选择性移除通道区400中的外延层208(如通道层)之间的外延层206(如牺牲层)。选择性移除外延层206(如牺牲层)可露出外延层208(如通道层),以形成外延层208的通道部件。值得注意的是,采用相同标号208标示外延层208的通道部件以简化说明。选择性移除外延层206(如牺牲层)的实施方法可为选择性干蚀刻、选择性湿蚀刻、或其他选择性蚀刻工艺。在一些实施例中,选择性湿式蚀刻包括以氢氧化铵-过氧化氢-水的混合物进行蚀刻。在一些实施例中,选择性移除包括氧化硅锗后移除硅锗氧化物。举例来说,可由臭氧清洁进行氧化,接着以蚀刻剂如氢氧化铵移除硅锗氧化物。
方法100可包含额外步骤以形成金属栅极堆叠250。金属栅极堆叠250可为高介电常数介电层与金属栅极的堆叠。在一些实施例中,金属栅极堆叠250形成于工件200上的栅极沟槽中,并沉积于移除外延层206(如牺牲层)所留下的空间中。在此考量下,金属栅极堆叠250包覆第一鳍状单元210A与第二鳍状单元210B的每一者中,外延层208的通道部件的每一者。在多种实施例中,金属栅极堆叠250(或高介电常数的介电层与金属栅极的堆叠)包括界面层、形成于界面层上的高介电常数的栅极介电层、及/或形成于高介电常数的栅极介电层上的栅极层。此处所述的高介电常数的栅极介电层包含的介电材料具有高介电常数,比如大于热氧化硅的介电常数(约3.9)。金属栅极堆叠250所用的栅极层可包含金属、金属合金、或金属硅化物。此外,形成金属栅极堆叠255的步骤可包含沉积形成多种栅极材料与一或多个衬垫层,并进行一或多道化学机械研磨工艺以移除多余栅极材料及平坦化工件200的上表面。
在一些实施例中,金属栅极堆叠250的界面层可包含介电材料如氧化硅、硅酸铪、或氮氧化硅。界面层的形成方法可为化学氧化、热氧化、原子层沉积、化学气相沉积、及/或其他合适方法。金属栅极堆叠250的高介电常数的栅极介电层可包含高介电常数的介电层如氧化铪。在其他实施例中,金属栅极堆叠250的高介电常数的栅极介电层可包含其他高介电常数的介电层,比如氧化钛、氧化铪锆、三氧化二钽、硅酸铪、氧化锆、氧化锆硅、氧化镧、氧化锆、氧化钛、五氧化二钽、氧化钇、钛酸锶、钛酸钡、氧化钡锆、氧化铪锆、氧化铪镧、氧化铪硅、氧化镧硅、氧化铝硅、氧化铪钽、氧化铪钛、钛酸钡锶、氧化铝、氮化硅、氮氧化硅、上述的组合、或其他合适材料。高介电常数的栅极介电层的形成方法可为原子层沉积、物理气相沉积、化学气相沉积、氧化、及/或其他合适方法。
金属栅极堆叠250的栅极可包含单层或交错的多层结构,比如具有选定功函数的金属层(用于增进装置效能的功函数金属层)、衬垫层、湿润层、黏着层、与金属合金或金属硅化物的多种组合。举例来说,金属栅极堆叠250的栅极层可包括钛、银、铝、氮化钛铝、碳化钽、碳氮化钽、氮化钽硅、锰、锆、氮化钛、氮化钽、钌、钼、铝、氮化钨、铜、钨、铼、铱、钴、镍、其他合适金属材料、或上述的组合。在多种实施例中,金属栅极堆叠250的栅极层的形成方法可为原子层沉积、物理气相沉积、化学气相沉积、电子束蒸镀、或其他合适工艺。此外,可分别形成用于n型场效晶体管与p型场效晶体管的栅极层,其可采用不同金属层以提供不同的n型与p型功函数金属层。在多种实施例中,可进行化学机械研磨工艺,以自金属栅极堆叠250的栅极层移除多余金属,进而提供金属栅极堆叠250的实质上平坦上表面。金属栅极堆叠250包括夹设于通道区400中的外延层208(如通道层)的通道部件之间的部分。
本发明的一或多个实施例对半导体装置与其形成方法提供许多优点,但这些优点并非用于局限本发明实施例。举例来说,本发明实施例可提供选择性实施内侧间隔物的方式,其实施内侧间隔物于第一装置区中而不实施内侧间隔物于第二装置区中,第一装置区的装置具有第一鳍状物宽度,第二装置区的装置具有第二鳍状物宽度,且第二鳍状物宽度小于第一鳍状物宽度。在一些应用中,第一装置区适用于逻辑装置,而第二装置区适用于静态随机存取存储器装置。
本发明一例示性的实施例关于半导体装置。半导体装置包括多个第一全绕式栅极装置位于第一装置区中,以及多个第二全绕式栅极装置位于第二装置区中。第一全绕式栅极装置的每一者包括多个通道部件的第一垂直堆叠;第一闸极结构,围绕通道部件的第一垂直堆叠并位于其上;以及多个内侧间隔物结构。第二全绕式栅极装置的每一者包括多个通道部件的第二垂直堆叠;以及第二闸极结构,围绕通道部件的第二垂直堆叠并位于其上。通道部件的第一垂直堆叠的两个相邻的通道部件之间,隔有第一栅极结构的一部分与内侧间隔物结构的至少一者。通道部件的第二垂直堆叠的两个相邻的通道部件之间,只隔有第二栅极结构的一部分。
在一些实施例中,第一装置区为逻辑装置区,且第二装置区为存储器装置区。在一些实施方式中,通道部件的第一垂直堆叠的每一者具有沿着第一栅极结构的方向的第一宽度,通道部件的第二垂直堆叠的每一者具有沿着第一栅极结构的方向的第二宽度,且第一宽度大于第二宽度。在一些实施方式中,第一宽度介于约16nm至约30nm之间。在一些例子中,第二宽度介于约6nm至约15nm之间。在一些实施例中,内侧间隔物结构的每一者包括金属氧化物、碳氮化硅、碳氮氧化硅、或碳氧化硅。在一些实施例中,第一全绕式栅极装置的每一者还包括第一源极/漏极结构以与通道部件的第一垂直堆叠相邻,且第二全绕式栅极装置的每一者还包括第二源极/漏极结构以与通道部件的第二垂直堆叠相邻。第一源极/漏极结构接触内侧间隔物结构的至少一者,且第二源极/漏极结构接触通道部件的第二垂直堆叠的两个相邻的通道部件之间的第二栅极结构的部分。
本发明另一例示性的实施例关于半导体装置。半导体装置包括:第一全绕式栅极装置与第二全绕式栅极装置。第一全绕式栅极装置包括:第一通道部件,位于第一全绕式栅极装置的通道区中;第一栅极结构,包覆第一通道部件并位于其上;以及内侧间隔物结构。第二全绕式栅极装置包括:第二通道部件,位于第二全绕式栅极装置的通道区中;以及第二栅极结构,包覆第二通道部件并位于其上。两个相邻的第一通道部件之间隔有第一栅极结构的一部分与至少一内侧间隔物结构,且两个相邻的第二通道部件之间只隔有第二栅极结构的一部分。
在一些实施例中,内侧间隔物结构各自具有单层结构。在一些实施方式中,内侧间隔物结构各自包括第一层与第二层,其中第一层包括金属氧化物或碳氮化硅,且第二层包括碳氮氧化硅或碳氧化硅。在一些实施例中,第一层的介电常数大于第二层的介电常数。在一些实施例中,第一全绕式栅极装置位于逻辑装置区中,且第二全绕式栅极装置位于静态随机存取存储器装置区中。在一些实施方式中,第一通道部件的每一者具有第一宽度,第二通道部件的每一者具有第二宽度,且第一宽度大于第二宽度。在一些实施例中,第一宽度介于约16nm至约30nm之间,且第二宽度介于约6nm至约15nm之间。在一些例子中,第一全绕式栅极装置还包括第一源极/漏极结构与第二源极/漏极结构位于第一全绕式栅极装置的通道区的每一侧上,且第一栅极结构位于两个第一通道部件之间的一部分,延伸于两个内侧间隔物结构之间。第二全绕式栅极装置还包括第三源极/漏极结构与第四源极/漏极结构位于第二全绕式栅极装置的通道区的每一侧上,且第二栅极结构位于两个第二通道部件之间的一部分,延伸于第三源极/漏极结构与第四源极/漏极结构之间且接触第三源极/漏极结构与第四源极/漏极结构。
本发明又一例示性的实施例关于半导体装置的制作方法。半导体装置的制作方法包括:形成层状物堆叠于基板上,且层状物堆叠包括交错的多个第一半导体层与多个第二半导体层;自基板的第一区中的层状物堆叠形成第一鳍状单元;自基板的第二区中的层状物堆叠形成第二鳍状单元;蚀刻第一源极/漏极沟槽,以露出第一鳍状单元中的第一半导体层与第二半导体层的侧壁,并以图案膜遮罩第二鳍状单元;选择性地使第一鳍状单元中的第二半导体层凹陷以形成内侧间隔物凹陷,并以图案膜遮罩第二鳍状单元;沉积内侧间隔物层于内侧间隔物凹陷之中与第二鳍状单元上的图案膜之上;蚀刻第二源极/漏极沟槽,以露出第二鳍状单元中的第一半导体层与第二半导体层的侧壁;以及同时形成第一外延的源极/漏极结构于第一源极/漏极沟槽中,以及第二外延的源极/漏极结构于第二源极/漏极沟槽中。
在一些实施例中,第二鳍状单元的第二宽度小于第一鳍状单元的第一宽度。在一些实施方式中,第一区为逻辑装置区,而第二区为存储器装置区。在一些实施例中,存储器装置区基本上为静态随机存取存储器装置。在一些例子中,沉积内侧间隔物层的步骤包括:沉积第一内侧间隔物层于内侧间隔物凹陷之中与第二鳍状单元上的图案膜之上;沉积第二内侧间隔物层于第一内侧间隔物层上;以及使第二内侧间隔物层凹陷。
上述实施例的特征有利于本技术领域中普通技术人员理解本发明。本技术领域中普通技术人员应理解可采用本发明作基础,设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中普通技术人员亦应理解,这些等效置换并未脱离本发明精神与范畴,并可在未脱离本发明的精神与范畴的前提下进行改变、替换、或更动。
Claims (1)
1.一种半导体装置,包括:
多个第一全绕式栅极装置,位于一第一装置区中,其中所述多个第一全绕式栅极装置的每一者包括:
多个通道部件的一第一垂直堆叠;
一第一栅极结构,围绕所述多个通道部件的该第一垂直堆叠并位于其上;以及
多个内侧间隔物结构;以及
多个第二全绕式栅极装置,位于一第二装置区中,其中所述多个第二全绕式栅极装置的每一者包括:
多个通道部件的一第二垂直堆叠;以及
一第二栅极结构,围绕所述多个通道部件的该第二垂直堆叠并位于其上;
其中所述多个通道部件的该第一垂直堆叠的两个相邻的通道部件之间,隔有该第一栅极结构的一部分与所述多个内侧间隔物结构的至少一者,
其中所述多个通道部件的该第二垂直堆叠的两个相邻的通道部件之间,只隔有该第二栅极结构的一部分。
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US11417653B2 (en) * | 2019-09-30 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method for forming the same |
US11264508B2 (en) * | 2020-01-24 | 2022-03-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Leakage prevention structure and method |
KR20210124731A (ko) * | 2020-04-07 | 2021-10-15 | 삼성전자주식회사 | 게이트 스페이서를 갖는 반도체 소자들 |
US11398550B2 (en) * | 2020-06-15 | 2022-07-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with facet S/D feature and methods of forming the same |
TW202302900A (zh) * | 2021-04-06 | 2023-01-16 | 荷蘭商Asm Ip私人控股有限公司 | 用於形成包括氮化矽之圖案化結構的方法及系統及利用方法形成的裝置結構 |
US20230064457A1 (en) * | 2021-08-27 | 2023-03-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nanostructure Device and Method of Forming Thereof |
US20230061384A1 (en) * | 2021-08-31 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated Circuit Structure with a Reduced Amount of Defects and Methods for Fabricating the Same |
WO2023030653A1 (en) * | 2021-09-03 | 2023-03-09 | Imec Vzw | A nanostructure comprising nanosheet or nanowire transistors |
US20230118779A1 (en) * | 2021-10-14 | 2023-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multigate Device Structure with Engineered Gate |
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US8963258B2 (en) | 2013-03-13 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company | FinFET with bottom SiGe layer in source/drain |
US10199502B2 (en) | 2014-08-15 | 2019-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure of S/D contact and method of making same |
US9818872B2 (en) | 2015-06-30 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
US9899387B2 (en) | 2015-11-16 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
US9754840B2 (en) | 2015-11-16 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Horizontal gate-all-around device having wrapped-around source and drain |
US10032627B2 (en) | 2015-11-16 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming stacked nanowire transistors |
US9887269B2 (en) | 2015-11-30 | 2018-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
US9899269B2 (en) | 2015-12-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-gate device and method of fabrication thereof |
US9899398B1 (en) | 2016-07-26 | 2018-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Non-volatile memory device having nanocrystal floating gate and method of fabricating same |
US10290546B2 (en) | 2016-11-29 | 2019-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Threshold voltage adjustment for a gate-all-around semiconductor structure |
US10714592B2 (en) * | 2017-10-30 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
US10971585B2 (en) * | 2018-05-03 | 2021-04-06 | International Business Machines Corporation | Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between adjacent gates |
US11088255B2 (en) * | 2019-05-17 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices |
US10879379B2 (en) * | 2019-05-30 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-gate device and related methods |
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