CN110957260A - 鳍状场效晶体管的制作方法 - Google Patents

鳍状场效晶体管的制作方法 Download PDF

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CN110957260A
CN110957260A CN201910894324.7A CN201910894324A CN110957260A CN 110957260 A CN110957260 A CN 110957260A CN 201910894324 A CN201910894324 A CN 201910894324A CN 110957260 A CN110957260 A CN 110957260A
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semiconductor
fin
layer
dielectric
fins
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林含谕
詹易叡
李芳苇
林执中
黄昭宪
林立德
林斌彦
峰地辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

鳍状场效晶体管的制作方法包括:形成至少三个半导体鳍状物于基板上,其中半导体鳍状物的第一半导体鳍状物、第二半导体鳍状物、与第三半导体鳍状物的长度方向实质上彼此平行,且第一半导体鳍状物与第二半导体鳍状物之间的空间小于第二半导体鳍状物与第三半导体鳍状物之间的空间;沉积第一介电层于半导体鳍状物的顶部与侧壁上,以形成沟槽于第二半导体鳍状物与第三半导体鳍状物之间,且沟槽的底部与两侧侧壁为第一介电层;以第一斜向离子布植工艺布植离子至沟槽的两侧侧壁的一者;以第二斜向离子布植工艺布植离子至沟槽的两侧侧壁的另一者;沉积第二介电层至沟槽中,且第一介电层与第二介电层的材料不同;以及蚀刻第一介电层。

Description

鳍状场效晶体管的制作方法
技术领域
本发明实施例关于鳍状场效晶体管,更特别关于使半导体鳍状物两侧的介电层高度一致的方法。
背景技术
半导体集成电路产业已经历指数成长。集成电路材料与设计的技术进展,使每一代的集成电路比前一代的集成电路具有更小且更复杂的电路。在集成电路演进中,功能密度(如单位芯片面积的内连线装置数目)通常随着几何尺寸(如采用的制作工艺所能产生的最小构件或线路)缩小而增加。尺寸缩小通常有利于增加产能并降低相关成本。此尺寸缩小亦增加处理与形成集成电路的复杂度。
在形成鳍状场效晶体管装置时,形成沟槽于鳍状场效晶体管装置的鳍状单元之间,接着将介电材料填入沟槽。随着沟槽宽度缩小,在填入沟槽的介电材料中可能形成缝隙(如气囊)。在后续工艺中,这些缝隙会造成多种问题,比如造成后续形成的结构中的缺陷。举例来说,缝隙可能不对称地形成于鳍状物的一侧上,而不形成于鳍状物的另一侧上,这会在介电材料凹陷工艺时,造成围绕鳍状物的介电材料的蚀刻不一致。这会影响鳍状场效晶体管装置效能的一致性。因此现有技术无法完全符合所有方面的需求。
发明内容
本发明一实施例提供的鳍状场效晶体管的制作方法,包括:形成至少三个半导体鳍状物于基板上,其中半导体鳍状物的第一半导体鳍状物、第二半导体鳍状物、与第三半导体鳍状物的长度方向实质上彼此平行,且第一半导体鳍状物与第二半导体鳍状物之间的空间小于第二半导体鳍状物与第三半导体鳍状物之间的空间;沉积第一介电层于半导体鳍状物的顶部与侧壁上,以形成沟槽于第二半导体鳍状物与第三半导体鳍状物之间,且沟槽的底部与两侧侧壁为第一介电层;以第一斜向离子布植工艺布植离子至沟槽的两侧侧壁的一者;以第二斜向离子布植工艺布植离子至沟槽的两侧侧壁的另一者;沉积第二介电层至沟槽中,且第一介电层与第二介电层的材料不同;以及蚀刻第一介电层。
本发明一实施例提供的鳍状场效晶体管的制作方法,包括:提供至少三个自基板凸起的鳍状物;沉积第一介电层于三个鳍状物的顶部与侧壁上,形成第一鳍状物与第二鳍状物之间的第一介电层中的缝隙,以及第二鳍状物与第三鳍状物之间的沟槽;布植离子至第一介电层的顶部中,其中离子布植至沟槽侧壁中的深度,大于离子布植至缝隙上的第一介电层中的深度;以及蚀刻第一介电层以形成隔离结构。
本发明一实施例提供的半导体装置,包括:半导体基板;第一半导体鳍状物、第二半导体鳍状物、与第三半导体鳍状物,自半导体基板延伸;介电材料层,位于第一半导体鳍状物与第二半导体鳍状物之间跟第二半导体鳍状物与第三半导体鳍状物之间,第一半导体鳍状物与第二半导体鳍状物之间的介电材料层具有缝隙,缝隙在介电材料层的上表面具有开口,且缝隙朝半导体基板向下延伸;以及介电鳍状物,位于第二半导体鳍状物与第三半导体鳍状物之间与介电材料层上。
附图说明
图1是本发明多种实施例中,形成半导体装置的方法的方框图。
图2、图3、图4、图5、图6、图7、图8、与图9是一些实施例中,依据图1的方法制作目标的半导体装置于中间阶段的剖视图。
附图标记说明:
θ 角度
D1、D2 空间
H0、H1、H5 高度
H2 厚度
H3、H4 深度
W0、W1、W2 宽度
10 方法
12、14、16、18、20、22、24、26 步骤
100 半导体装置
102 基板
104、104a、104b、104c 半导体鳍状物
106 硬遮罩
106a 垫氧化物层
106b 垫氮化物层
108 衬垫层
112 隔离结构
112a 布植部分
112b 未处理部分
114a、114b 介电侧壁
116 介电沟槽
118、168 缝隙
150 斜向离子布植工艺
164 介电鳍状物
180 栅极堆叠
182 栅极介电层
184 栅极
具体实施方式
下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件、与配置的实施例是用以简化本发明内容而非局限本发明。举例来说,形成第一结构于第二结构上的叙述包含两者直接接触的实施例,或两者之间隔有其他额外结构而非直接接触的实施例。此外,本发明的多个实例可重复采用相同标号以求简洁,但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外,空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件,而非局限于图示方向。元件亦可转动90°或其他角度,因此方向性用语仅用以说明图示中的方向。
本发明的多种实施例一般关于半导体装置与其形成方法。具体而言,本发明实施例关于使具有鳍状通道的场效晶体管(如鳍状场效晶体管)的介电材料一致地凹陷。在一些实施例中,围绕鳍状物的隔离结构中的缝隙(如气囊)会不对称地位于鳍状物的一侧上,这会在凹陷工艺时造成隔离结构的不一致蚀刻。本发明实施例处理隔离结构的顶部。处理如斜向离子布植,可补偿鳍状物的一侧上的隔离结构的介电材料的蚀刻速率,造成鳍状物两侧上的隔离结构具有一致的平均蚀刻速率。本发明实施例有助于增加鳍状物效能的一致性。
图1是本发明多种实施例中,形成半导体装置如鳍状场效晶体管装置的方法10的流程图。方法10仅为举例,而非局限本发明实施例至权利要求未实际记载处。在方法10之前、之中、与之后可提供额外步骤,且方法10的额外实施例可置换、省略、或调换一些所述步骤。方法10将搭配图2至9说明如下。图2至9是半导体装置100在方法10的多种阶段的例示性剖视图。
半导体装置100可为制作集成电路时的中间装置或其部分,其可包含静态随机存取存储器及/或逻辑电路、被动构件(如电阻、电容、或电感)、或主动构件(如鳍状场效晶体管、金属氧化物半导体场效晶体管、互补式金属氧化物半导体晶体管、双极晶体管、高电压晶体管、高频晶体管、其他存储单元、或上述的组合)。此外,本发明的多种实施例提供多种结构如晶体管、栅极堆叠、主动区、隔离结构、与其他结构以简化说明并使说明易于理解,但实施例不必局限于任何装置形态、任何装置数目、任何区域数目、或任何结构或区域的设置。
如图1所示,方法10的步骤12提供或接收图2所示的结构(或半导体装置100)。半导体装置100包含基板102与多种结构建构其中或其上。具体而言,半导体装置100包括凸出基板102的半导体鳍状物104(如鳍状物104a至104c),用于图案化半导体鳍状物104的硬遮罩106、与覆盖半导体鳍状物104的侧壁及基板102的表面的衬垫层108。
在所述实施例中,基板102为硅基板。在其他实施例中,基板102可包含另一半导体元素如锗、半导体化合物(如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟)、半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、及/或磷砷化镓铟)、或上述的组合。基板102可为一致的组成,或包含多种层状物,且可选择性蚀刻一些层状物以形成鳍状物。层状物可具有类似或不同组成。在多种实施例中,一些基板层可具有不一致的组成,以诱发装置应力并进而调整装置效能。层状基板的例子包含绝缘层上半导体基板102,其具有埋置介电层。在一些例子中,基板102的一层可包含绝缘层如氧化硅、氮化硅、氮氧化硅、碳化硅、及/或其他合适的绝缘材料。
半导体鳍状物104可包含一或多种半导体材料如硅、锗、或硅锗。在一实施例中,半导体鳍状物104的每一者可包含多种不同的半导体层彼此堆叠。半导体鳍状物104的制作方法可采用合适工艺,包含双重图案化或多重图案化工艺。一般而言,双重图案化或多重图案化工艺结合光刻与自对准工艺,其产生的图案间距可小于采用单一直接的光刻工艺所得的图案间距。举例来说,一实施例形成牺牲层于基板上,并采用光刻工艺图案化牺牲层。采用自对准工艺沿着图案化的牺牲层的侧部形成间隔物。接着移除牺牲层,再采用保留之间隔物或芯作为遮罩并蚀刻基板102的初始磊晶半导体层,以图案化半导体鳍状物104。蚀刻工艺可包含干蚀刻、湿蚀刻、反应性离子蚀刻、及/或其他合适工艺。
在一实施例中,步骤12可磊晶成长半导体材料于基板102的整个表面上,接着采用硬遮罩106作为蚀刻遮罩并蚀刻半导体材料,以产生半导体鳍状物104。硬遮罩层106可包含任何合适的介电材料如氮化硅。硬遮罩层106亦可包含多层,比如双层堆叠,其包含下侧层与上侧层。这些层状物可选择合适材料,且选择方式有部分依据蚀刻剂的选择性。在一实施例中,下侧层可为垫氧化物层106a,而上侧层可为垫氮化物层106b。举例来说,垫氧化物层可为含氧化硅的薄膜,其形成方法可采用热氧化工艺。垫氧化物层106a可作为基板102与垫氮化物层106b之间的粘着层,且可作为蚀刻垫氮化物层106b所用的蚀刻停止层。在一实施例中,垫氮化物层106b的组成为氮化硅,其形成方法可采用低压化学气相沉积或等离子体辅助化学气相沉积。在一些实施例中,硬遮罩106的高度H1为约20nm至约40nm,比如约22nm。
硬遮罩106的图案化方法可采用合适工艺,包括双重图案化工艺、多重图案化工艺、光刻、自对准工艺、或芯-间隔物工艺。接着采用硬遮罩106以图案化基板102的露出部分,进而形成图2所示的半导体鳍状物104。相邻的半导体鳍状物104之间的空间之后将填有介电材料,以形成隔离结构如浅沟槽隔离结构,如下详述。
半导体鳍状物104的长度方向沿着x方向延伸,且可沿着鳍状物宽度方向(如y方向)隔有一致或不一致的空间。如图2所示的实施例中,半导体装置100沿着y方向自左至右含有三个半导体鳍状物104如104a、104b、与104c。虽然图2显示三个半导体鳍状物,但半导体装置100可包含任何数目的半导体鳍状物。半导体鳍状物104a、104b、与104c的长度方向彼此实质上平行。用语“实质上平行”指的是两条线平行,或两条线的角度小于10度。在一些实施例中,半导体鳍状物104a、104b、与104c的每一者具有鳍状物高度H0。鳍状物高度H0自半导体鳍状物的上表面测量至基板的上表面。在一实施例中,鳍状物高度H0介于约100nm至约150nm之间,比如约120nm。在一些实施例中,半导体鳍状物104a、104b、与104c的每一者具有宽度W0。在一实施例中,宽度W0介于约5nm至约15nm之间,比如约12nm。半导体鳍状物104a、140b、与104c可具有实质上彼此相同或不同的鳍状物宽度。
半导体鳍状物104的每一者具有两个侧壁。对相邻的半导体鳍状物而言,相邻的半导体鳍状物的侧壁彼此相对。半导体鳍状物104a与104b彼此之间隔有空间D1。半导体鳍状物104b与104c彼此之间隔有空间D2。在一实施例中,空间D1与D2各自介于约10nm至约60nm之间。在一些例子中,半导体鳍状物104b与104c之间的空间D2,大于半导体鳍状物104a与104b之间的空间D1(比如大于约20%)。在所述实施例中,半导体鳍状物104b与104c之间的空间D2,大于或等于鳍状物104a与104b之间的空间D1的两倍(比如D2≥2D1)。由于半导体鳍状物104b与104c之间的空间较大,半导体装置100在整个所述区域的鳍状物密度不一致,其于半导体鳍状物104b与104c周围的鳍状物密度较低。如下详述,一或多个介电鳍状物可形成于鳍状物密度较低的区域中,比如半导体鳍状物104b与104c之间的区域。介电鳍状物可增加这些区域中的鳍状物密度。当半导体装置的尺寸持续下降且半导体鳍状物的高宽比随之增加时,较高鳍状物密度的优点之一为提供半导体鳍状物所需的优选支撑以抵抗鳍状物崩溃。较高鳍状物密度的其他优点包括对形成于半导体鳍状物上的结构(如源极/漏极接点金属)可提供优选支撑,而分开距离较宽的半导体鳍状物之间的区域可能会拉入结构的金属。
在所述实施例中,衬垫层108可顺应性地覆盖半导体鳍状物104的侧壁与基板102的表面。在一些实施例中,衬垫层108可顺应性地覆盖硬遮罩106的顶部与侧壁。衬垫层108有助于减少或避免半导体鳍状物中的掺质(如硼)迁移至周围区域中。衬垫层108亦有助于阻挡再形成鳍状物工艺中的锗扩散。再形成鳍状物工艺可将硅鳍状物的部分置换为不同晶格常数的其他半导体材料(如硅锗)。在一实施例中,衬垫层108的形成方法可采用氧化工艺与氮化工艺。在一些实施例中,氧化工艺包括热氧化工艺、快速热氧化工艺、化学氧化工艺、原位蒸汽产生工艺、或辅助原位蒸汽产生工艺。在一些实施例中,氮化工艺包括以炉进行热氮化,或采用氨、一氧化二氮、氮气、或类似环境的快速热退火。
上述的氧化与氮化工艺,会造成衬垫层108含有一或多个子层。氧化工艺会造成氧化物层具有确定厚度。在基板102为硅基板的实施例中,氮化工艺会造成氮原子与氧化物层反应形成氮氧化物层,比如氮氧化硅层。若选择的氮化工艺进行足够时间,氧化物层的整个厚度会转变成氮氧化物层。若选择的氮化工艺进行较短时间,则可保留氧化物层的一部分,最后形成氧化物层与上方的氮化物层。工艺条件可适于提供所需厚度的氧化物层与氮化物层。在一实施例中,衬垫层108为厚度介于约1nm至约5nm之间的氮氧化硅层。
方法10的步骤14(见图1)沉积介电材料于半导体装置100的表面上,以形成隔离结构112,如图3所示。在一些实施例中,隔离结构112为浅沟槽隔离结构。隔离结构112可沉积于基板102的上表面上,以及半导体鳍状物104与硬遮罩106的露出表面上。隔离结构112所用的合适介电材料包含氧化硅、氮化硅、碳化硅、氟化硅酸盐玻璃、低介电常数的介电材料、上述的组合、及/或其他合适的介电材料。在所述实施例中,隔离结构112包含氧化硅。在一些实施例中,隔离结构112可包含多层结构,比如具有一或多个衬垫层。在多种例子中,介电材料的沉积方法可为任何合适技术,包括热成长工艺、化学气相沉积工艺、次压化学气相沉积工艺、可流动的化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺、旋转涂布工艺、及/或其他合适工艺。
在所述实施例中,采用顺应性的沉积技术如原子层沉积工艺。在原子层沉积工艺时,沉积隔离结构112如顺应性的层状物,以覆盖半导体鳍状物104的每一者并填入相邻的半导体鳍状物104之间的空间。在原子层沉积工艺时,隔离结构112沿着y方向的宽度W1与沿着z方向的厚度H2(高于硬遮罩106)可逐渐成长,而相邻的半导体鳍状物104之间的空间将对应减少。由于半导体鳍状物104a与104b之间的空间,比半导体鳍状物104b与104c之间的空间窄,介电材料会先填满半导体鳍状物104a与104b之间的空间。作为比较,不填满半导体鳍状物104b和104c之间的空间,而是保留介电沟槽116,其具有定义于对向的介电侧壁114a和114b之间的宽度W2。隔离结构112的额外层状物可进一步填入介电沟槽116,以控制宽度W2。宽度W2可与隔离结构112的宽度W1相同或不同。此外,多种实施例的宽度W2可小于、等于、或大于半导体鳍状物104的宽度W0。在一些实施例中,隔离结构112的宽度W1(与厚度H2)为约5nm至约20nm,比如约12nm。介电沟槽116的宽度W2为约9nm至约30nm,比如约14nm。
在后续制作步骤中,介电鳍状物将填入沟槽116。如上所述,设计考量之一为一旦填入介电鳍状物,其有助于改善鳍状物的一致性。此设计考量可搭配半导体鳍状物104的宽度与间距,以控制沉积工艺时的隔离结构112的厚度。
在将介电材料填入半导体鳍状物104a与104b之间的空间时,空间的宽度会越来越小,而缝隙118(如气囊)可能密封于介电材料中。缝隙118通常位于半导体鳍状物104a与104b之间的中间处,且其长度方向沿着z方向延伸。形成缝隙118的主要原因为半导体鳍状物104a与104b之间较窄的空间的高深宽比,以及原子层沉积工艺时在隔离结构112的顶部的略高的沉积速率,这会造成介电材料在填入缝隙118之前即盖住缝隙118。在多种实施例中,缝隙118本身具有大高宽比,比如大于10:1。在一些实施例中,缝隙118的宽度介于约0.1nm至约2nm之间,比如约0.5nm。在一些实施例中,缝隙118的最顶部高于垫氧化物层106a,但低于垫氮化物层106b的最顶部。
缝隙118通常是不想要的现象,其于制作半导体装置时以及在完成的装置中都会产生问题。在一些例子中,缝隙118具有预期之外的尺寸与高宽比。此外,缝隙118会不对称地存在于一些半导体鳍状物104周围,比如半导体鳍状物104b周围。缝隙118形成于半导体鳍状物104b的一侧上,但不形成于半导体鳍状物104b的另一侧上,这会对隔离结构112造成无法预期且不一致的沉积后工艺,比如不一致的蚀刻、研磨、及/或退火。举例来说,在使隔离结构112凹陷以露出半导体鳍状物104的顶部的后续制作步骤中,半导体鳍状物104的左侧上的介电材料的蚀刻速率,可能高于半导体鳍状物104的右侧上的介电材料的蚀刻速率。蚀刻速率差异主要来自于左侧上的平均介电材料密度较低,一旦蚀刻剂渗入缝隙118中即加快蚀刻。半导体鳍状物104b的两侧上的蚀刻速率差异,会造成左侧上的介电材料凹陷程度大于右侧上的介电材料凹陷程度。如此一来,半导体鳍状物104b的两侧上所露出的鳍状物长度不一致。露出的鳍状物长度不一致,会劣化装置效能与良率。实施后续步骤中的处理,以缓解不对称的缝隙所造成的蚀刻速率变异。
方法10的步骤16(见图1)对介电沟槽116的介电侧壁114a进行第一方向性处理,比如沿着自基板102的上表面的法线倾斜的第一方向进行第一方向性处理(见图4)。方法10的步骤18(见图1)对介电沟槽116的介电侧壁114b进行第二方向性处理,比如沿着自基板102的上表面的法线倾斜的第二方向进行第二方向性处理(见图5)。在一实施例中,可在一处理工艺时同时进行步骤16与18,其可同时提供第一方向性处理与第二方向性处理。
在多种实施例中,第一方向性处理与第二方向性处理包含斜向离子布植工艺150,其可减少隔离结构112的顶部的抗蚀刻性。离子穿入隔离结构112至一定的深度。接收离子的隔离结构112的顶部标示为布植部分112a。实质上不含离子的隔离结构112的底部标示为未处理部分112b。采用斜向离子布植工艺150可确保离子布植至隔离结构112的不同区域上的多种所需深度,使与介电沟槽116相邻的布植部分112a的深度,因遮荫效应而大于缝隙118上的布植部分112a的深度。在许多实施例中,可改变斜向剂量源的角度θ以控制布植程度(如离子轰击),而角度θ相对于Z方向可介于约15度至约25度之间,比如约20度。特定角度θ的选择依据介电侧壁114a与114b的所需布植深度,以及半导体鳍状物104b两侧上所需的深度差异。在一些例子中,若角度θ大于约25度,则布植深度过浅而不适用于后续制作工艺。在一些例子中,若角度θ小于约15度,半导体鳍状物104b的两侧上的布植深度可能过深,而遮荫效应所造成的深度差异会减少。同样地,若角度小于约15度,离子可能自顶部穿入半导体鳍状物104,这会将杂质导入鳍状物。在所述实施例中,对与介电沟槽116相邻的布植部分112a而言,离子布植的深度H3低于半导体鳍状物104b的上表面。对高于缝隙118的布植部分112a而言,离子布植的深度H4低于硬遮罩106的上表面但不低于半导体鳍状物104b的上表面。面对介电沟槽116的衬垫层108的顶部亦可布植离子。衬垫层108完全减少或避免离子进入半导体鳍状物104。在一些例子中,深度H3为约5%至约15%的鳍状物高度H0。在一例中,深度H3为约5nm至约15nm。在一些例子中,深度H4为约一半的硬遮罩的高度H1。在一例中,深度H4小于约15nm。在所述实施例中,半导体鳍状物104a与104b之间的布植部分112a的下表面,高于缝隙118的最顶部。在其他实施例中,半导体鳍状物104a与104b之间的布植部分112a的下表面,低于缝隙118的最顶部。
在多种实施例中,第一与第二斜向离子布植工艺所布植至隔离结构112中的离子,可含氩、氦、氢、或上述的组合。布植离子会造成布植部分112a的介电材料的分子无规。离子轰击产生悬吊键于分子结构中。此外,离子轰击产生孔洞于分子结构中,其降低布植部分112a的平均材料密度。为了至少这些理由,布植部分112a的抗蚀刻性小于未处理部分112b的抗蚀刻性。大于氩、氦、或氢的分子指的是质量与尺寸较大的分子,比如二氟化硼、磷、或上述的组合,其可用于布植工艺。越大的分子越能有效地产生介电材料中的悬吊键与孔洞。在一些实施例中,每一斜向布植工艺采用的离子剂量密度为约1.5×1016cm-2至约3.5×1016cm-2。离子剂量密度会造成布植离子对介电材料的分子无规的影响。在一些例子中,若离子剂量密度低于约1.5×1016cm-2,则对布植部分112a与未处理部分112b之间的蚀刻速率差异影响不大。另一方面,若离子剂量密度大于约3.5×1016cm-2,则剂量成本可能过高。在一些实施例中,每一斜向离子布植工艺采用的离子布植能量为约1keV至约3keV。离子布植能量会影响布植的垂直与水平深度。在一些例子中,若离子布植能量低于约1keV,则布植深度可能过浅而不适于后续的制作工艺。另一方面,若离子布植能量高于3keV,离子将穿入并损伤半导体鳍状物104,并对鳍状物的功能产生负作用。
在步骤16与18之后,半导体鳍状物104b与104c之间的布植部分112a比半导体鳍状物104a与104b之间的布植部分112a厚。综上所述,半导体鳍状物104b与104c之间的未处理部分112b,比半导体鳍状104a与104b之间的未处理部分112b薄。由于布植部分112a的蚀刻速率因分子无规(如下所述)而比未处理部分112b的蚀刻速率快,较厚的布植部分112a在后续凹陷工艺时可弥补半导体鳍状物104b与104c之间的隔离结构112的整体蚀刻速率。
方法10的步骤20(见图1)沉积一或多种介电材料于半导体装置100及隔离结构112上,以填入介电沟槽116,如图6所示。一或多种介电材料可包含碳氮化硅、碳氮氧化硅、碳氧化硅、金属氧化物(如氧化铪或氧化锆)、或上述的组合,且其沉积方法可采用原子层沉积、化学气相沉积、物理气相沉积、或其他合适方法。介电沟槽116中的一或多种介电材料转变成介电鳍状物164。在多种实施例中,介电鳍状物164的宽度W2可小于、等于、或大于半导体鳍状物104的宽度W0。在一例中,介电鳍状物164的宽度W2为约9nm至约30nm,比如约14nm。一旦形成介电鳍状物164,其有助于改善鳍状物的一致性。如图6所示,与只有半导体鳍状物104相较,半导体鳍状物104与介电鳍状物164可较一致地沿着y方向分布。在多种实施例中,介电鳍状物164与隔离结构112具有不同的材料组成。在一例中,隔离结构112包含氧化硅,而介电鳍状物164包含硅、氧化物、碳、或氮化物。
在一例中,介电鳍状物164包括氧化铝,其沉积方法可为原子层沉积工艺。在原子层沉积工艺时,沉积介电鳍状物164的介电材料如顺应性的层状物,以覆盖隔离结构112并填入介电沟槽116。介电材料可沉积至比隔离结构112的上表面高出高度H5,且高度H5可为约5nm至约20nm,比如约12nm。在原子层沉积工艺时,介电沟槽116的宽度会对应减少。随着介电沟槽116的宽度缩小,可密封介电鳍状物164的介电材料中的缝隙168(如气囊)。缝隙168通常位于介电鳍状物164的中间处,且其长度方向沿着z方向延伸。缝隙168的形成主因为介电沟槽116中的狭窄空间的高深宽比,以及原子层沉积工艺时在介电材料顶部的略高沉积速率,其造成介电材料在填满缝隙168之前即盖住缝隙168。在多种实施例中,缝隙168本身的高宽比可大于10:1。在一些实施例中,缝隙168的宽度为约0.1nm至约2nm,比如约0.5nm。在一些实施例中,缝隙168的最顶部高于隔离结构112的上表面。
方法10的步骤22(见图1)进行一或多道化学机械研磨工艺,以移除多余的介电材料,如图7所示。在一些实施例中,硬遮罩106可作为化学机械研磨停止层。在所述实施例中,化学机械研磨工艺中亦移除硬遮罩106。化学机械研磨工艺之后可打开缝隙118与168。由于步骤16与18中的离子布植未达半导体鳍状物104的上表面的下之下的深度,在化学机械研磨工艺之后的半导体鳍状物104a与104b之间,只保留隔离结构112的未处理部分112b。与此相较,半导体鳍状物104b与104c之间的布植部分112a仍保留于未处理部分112b上。在一些例子中,保留的布植部分112a的深度H3为约5%至约15%的鳍状物高度H0
在方法10的步骤24中(见图1),使隔离结构112凹陷,如图8所示。举例来说,隔离结构112的凹陷方法可为干蚀刻工艺或湿蚀刻工艺,其对隔离结构112的介电材料具有选择性,而不蚀刻半导体鳍状物104或介电鳍状物164。在使隔离结构112凹陷同时或之后,亦可使半导体鳍状物104的侧壁上的衬垫层108凹陷。在一实施例中,步骤24进行无等离子体的氢氟酸干蚀刻工艺,使隔离结构112凹陷。干蚀刻工艺的温度可为约30℃至约90℃,而压力可为约0.2Torr至约2.5Torr。化学蚀刻剂可包含氢氟酸与氨,而氢氟酸与氨之间的流速比例可为约0.5至约5。在一些实施例中,氢氟酸的流速为约50sccm至约500sccm,而氨的流速可为约15sccm至约200sccm。氨作为触媒以降低隔离结构112的介电材料的能障,使氢氟酸与介电材料可在较低温度与较低压力下有效反应。在干蚀刻工艺时,可产生氟硅酸铵((NH4)2SiF6)如蚀刻副产物。由于缝隙118与168的高深宽比,氟硅酸铵易于累积在这些缝隙的开口并盖住缝隙。以氟硅酸铵盖住缝隙118与168,有助于阻挡其他杂质进入这些缝隙。由于氟硅酸铵盐的低熔点为约100℃,一些实施例可控制干蚀刻工艺时的温度低于100℃(比如低于90℃),以维持盖住缝隙118与168。
使隔离结构112凹陷的干蚀刻工艺可视为含有两个时间阶段。在第一阶段中蚀刻工艺开始时,半导体鳍状物104b与104c之间的隔离结构112的部分,比半导体鳍状物104a与104b之间的隔离结构112的部分更快凹陷。这是因为蚀刻剂先与半导体鳍状物104b与104c之间的布植部分112a反应,其抗蚀刻性较小并因此其蚀刻速率高于具有缝隙118的未处理部分112b的蚀刻速率,在一些实施例中可高约50%至约100%。因此在第一阶段时,半导体鳍状物104b与104c之间的凹陷的隔离结构112的上表面,维持低于半导体鳍状物104a与104b之间的凹陷的隔离结构112的上表面。在第二阶段中,已完全移除布植部分112a。蚀刻剂开始与半导体鳍状物104b与104c之间以及半导体鳍状物104a与104b之间的未处理部分112b反应。由于缝隙118的存在,半导体鳍状物104a与104b之间的未处理部分112b具有较小的材料密度。此外,蚀刻剂可渗入缝隙118并具有较大的蚀刻表面。如此一来,半导体鳍状物104a与104b之间的隔离结构112的部分凹陷的速度,比半导体鳍状物104b与104c之间的隔离结构112的部分凹陷的速度快。半导体鳍状物104a与104b之间以及半导体鳍状物104b与104c之间的凹陷的隔离结构112之上表面的高度差异开始减少。在一些实施例中,可由计时器控制干蚀刻工艺。在第二阶段结束时,自半导体鳍状物104a至104c的所有区域中,凹陷的隔离结构112的上表面实质上共平面。换言之,在步骤16与18的斜向离子布植之后,整个半导体装置100的隔离结构112在凹陷时的平均蚀刻速率变得实质上相同,不论缝隙118存在于隔离结构112的何处。
如图8所示,步骤24之后的半导体鳍状物104与介电鳍状物164自凹陷的隔离结构112向上延伸。每一半导体鳍状物104的两侧上露出实质上相同的鳍状物长度,其可增加半导体鳍状物效能的一致性。半导体鳍状物104与介电鳍状物164延伸高于隔离结构112的高度H5大致相同。在一些实施例中,高度H5为约30nm至约80nm,比如约58nm。缝隙118的高宽比下降至低于约6:1,比如约5:1。类似地,缝隙168的高宽比下降至低于约8:1,比如约6:1。缝隙168的长度可大于缝隙118的长度。缝隙118在隔离结构112的上表面具有开口,且向下延伸的方向通常垂直于基板102的上表面。类似地,缝隙168在介电鳍状物164的上表面具有开口并向下延伸,且向下延伸的方向通常垂直于基板102的上表面。缝隙118与168的长度方向通常平行。此外,缝隙168的最底部可高于缝隙118的最顶部,使缝隙168的最底部高于凹陷的隔离结构112的上表面。在其他实施例中,缝隙168的最底部可低于缝隙118的最顶部,使缝隙168的最底部低于凹陷的隔离结构112的上表面。方法10亦可包含步骤24之后的烘烤工艺,其温度高于氟硅酸铵的分解温度,以打开缝隙118与168。
方法10的步骤26(见图1)进行后续步骤以完成最终装置,如图9所示。此包含多种工艺。在一例中,步骤26形成虚置栅极堆叠(未图示),接着将虚置栅极堆叠置换成最终栅极堆叠180。对此例而言,虚置栅极堆叠为具有虚置栅极介电层(如氧化硅)与虚置栅极层(如多晶硅)的占位器,而最终栅极堆叠180为高介电常数的介电层与金属栅极,其具有高介电常数的栅极介电层182与栅极184。栅极184可包含数个子层,比如合适的n型或p型功函数层与金属填充层。
在一些实施例中,高介电常数的栅极介电层182沉积于半导体装置100上的方法可为任何合适技术,比如原子层沉积、化学气相沉积、有机金属化学气相沉积、物理气相沉积、热氧化、上述的组合、及/或其他合适技术。高介电常数的栅极介电层182可包含金属氧化物(如氧化镧、氧化铝、氧化锆、氧化钛、氧化钽、氧化钇、钛酸锶、钛酸钡、氧化钡锆、氧化铪锆、氧化铪镧、氧化铪钽、氧化铪钛、钛酸钡锶、氧化铝、或类似物)、金属硅酸盐(如硅酸铪、硅酸镧、硅酸铝、或类似物)、金属或半导体的氮化物、金属或半导体的氮氧化物、上述的组合、及/或其他合适材料。在一些实施例中,高介电常数的栅极介电层182盖住缝隙118与168。同样地,栅极184沉积于半导体装置100的通道区上。具体而言,栅极184可沉积于高介电常数的栅极介电层182上。在多种例子中,栅极184可包含单层或多层,比如金属层、衬垫层、湿润层、及/或粘着层。在所述实施例中,栅极184包含功函数层与金属填充层。功函数层可包含p型功函数层或n型功函数层。p型功函数层包含的金属可为但不限于氮化钛、氮化钽、钌、钼、钨、铂、或上述的组合。n型功函数层包含的金属可为但不限于钛、铝、碳化钽、碳氮化钽、氮化钽硅、或上述的组合。p型功函数层或n型功函数层可进一步包含多层,且其沉积方法可为化学气相沉积、物理气相沉积、及/或其他合适工艺。金属填充层可包含铝、钨、铜、及/或其他合适材料。金属填充层的形成方法可为化学气相沉积、物理气相沉积、电镀、及/或其他合适工艺。
步骤26可进行后续步骤以完成制作半导体装置100。举例来说,方法10可形成接点与通孔以电性连接源极/漏极结构(未图示)与栅极堆叠180,并形成金属内连线连接多种晶体管以形成完整的集成电路。
本发明的一或多个实施例可提供许多优点至半导体装置与其形成方法,但不局限于此。举例来说,在形成介电鳍状物以增加鳍状物密度时,缝隙(如气囊)可能不对称地只出现在半导体鳍状物的一侧上,这会造成半导体鳍状物的两侧上的介电材料的蚀刻不一致。在本发明实施例中,处理可调整半导体鳍状物两侧上的介电材料的蚀刻速率,使半导体鳍状物周围的介电材料达到一致的平均蚀刻速率。本发明实施例有助于增加鳍状物的效能一致性。本发明多种实施例易于整合至现有的形成工艺。
本发明一例示性的实施例关于鳍状场效晶体管的制作方法。方法包括形成至少三个半导体鳍状物于基板上,其中半导体鳍状物的第一半导体鳍状物、第二半导体鳍状物、与第三半导体鳍状物的长度方向实质上彼此平行,且第一半导体鳍状物与第二半导体鳍状物之间的空间小于第二半导体鳍状物与第三半导体鳍状物之间的空间;沉积第一介电层于半导体鳍状物的顶部与侧壁上,以形成沟槽于第二半导体鳍状物与第三半导体鳍状物之间,且沟槽的底部与两侧侧壁为第一介电层;以第一斜向离子布植工艺布植离子至沟槽的两侧侧壁的一者;以第二斜向离子布植工艺布植离子至沟槽的两侧侧壁的另一者;沉积第二介电层至沟槽中,且第一介电层与第二介电层的材料不同;以及蚀刻第一介电层。在一些实施例中,第一介电层与第二介电层的沉积工艺采用原子层沉积。在一些实施例中,方法还包括在蚀刻第一介电层之前,至少对第一介电层与第二介电层进行化学机械研磨工艺。在一些实施例中,第一斜向离子布植工艺与第二斜向离子布植工艺相对于基板法线的倾斜角度各自为约15度至25度。在一些实施例中,第一斜向离子布植工艺与第二斜向离子布植工艺采用的离子布植能量各自为约1keV至约3keV。在一些实施例中,第一斜向离子布植工艺与第二斜向离子布植工艺的离子剂量各自为约1.5×1016cm-2至约3.5×1016cm-2。在一些实施例中,第一介电层包含氧化硅,且第一与第二斜向离子布植工艺布植至第一介电层中的离子包括硼、磷、或上述的组合。在一些实施例中,第一介电层包括氧化硅,且第一与第二斜向离子布植工艺布植至第一介电层中的离子包括氩、氦、氢、或上述的组合。在一些实施例中,蚀刻第一介电层的步骤包括无等离子体的氢氟酸干蚀刻。在一些实施例中,蚀刻第一介电层的步骤还包括采用氨作为无等离子体的氢氟酸干蚀刻的触媒。在一些实施例中,氢氟酸与氨之间的比例为约0.5至约5。在一些实施例中,蚀刻第一介电层的温度为约30℃至约90℃,而压力为约0.2Torr至约2.5Torr。
本发明另一实施例关于鳍状场效晶体管的制作方法。方法包括提供至少三个自基板凸起的鳍状物;沉积第一介电层于三个鳍状物的顶部与侧壁上,形成第一鳍状物与第二鳍状物之间的第一介电层中的缝隙,以及第二鳍状物与第三鳍状物之间的沟槽;布植离子至第一介电层的顶部中,其中离子布植至沟槽侧壁中的深度,大于离子布植至缝隙上的第一介电层中的深度;以及蚀刻第一介电层以形成隔离结构。在一些实施例中,方法还包括在蚀刻第一介电层之前,沉积第二介电层至沟槽中,其中第一介电层与第二介电层的材料不同。在一些实施例中,第一介电层包括氧化硅,而第二介电层包括碳与氮。在一些实施例中,布植离子的步骤包括采用斜向离子布植工艺。在一些实施例中,斜向离子布植工艺的斜向角度相对于基板的法线为约15度至25度。在一些实施例中,沉积第一介电层的步骤包括原子层沉积工艺。
本发明又一例示性的实施例关于半导体装置。半导体装置包括半导体基板;第一半导体鳍状物、第二半导体鳍状物、与第三半导体鳍状物,自半导体基板延伸;介电材料层,位于第一半导体鳍状物与第二半导体鳍状物之间跟第二半导体鳍状物与第三半导体鳍状物之间,第一半导体鳍状物与第二半导体鳍状物之间的介电材料层具有缝隙,缝隙在介电材料层的上表面具有开口,且缝隙朝半导体基板向下延伸;以及介电鳍状物,位于第二半导体鳍状物与第三半导体鳍状物之间与介电材料层上。在一些实施例中,第二半导体鳍状物与第三半导体鳍状物之间的空间,大于第一半导体鳍状物与第二半导体鳍状物之间的空间的两倍。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础,设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解,这些等效置换并未脱离本发明构思与范围,并可在未脱离本发明的构思与范围的前提下进行改变、替换、或变动。

Claims (1)

1.一种鳍状场效晶体管的制作方法,包括:
形成至少三个半导体鳍状物于一基板上,其中所述半导体鳍状物的一第一半导体鳍状物、一第二半导体鳍状物、与一第三半导体鳍状物的长度方向实质上彼此平行,且该第一半导体鳍状物与该第二半导体鳍状物之间的空间小于该第二半导体鳍状物与该第三半导体鳍状物之间的空间;
沉积一第一介电层于所述半导体鳍状物的顶部与侧壁上,以形成一沟槽于该第二半导体鳍状物与该第三半导体鳍状物之间,且该沟槽的底部与两侧侧壁为该第一介电层;
以一第一斜向离子布植工艺布植离子至该沟槽的两侧侧壁的一者;
以一第二斜向离子布植工艺布植离子至该沟槽的两侧侧壁的另一者;
沉积一第二介电层至该沟槽中,且该第一介电层与该第二介电层的材料不同;以及
蚀刻该第一介电层。
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