TWI776514B - 半導體裝置及方法 - Google Patents
半導體裝置及方法 Download PDFInfo
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- TWI776514B TWI776514B TW110118124A TW110118124A TWI776514B TW I776514 B TWI776514 B TW I776514B TW 110118124 A TW110118124 A TW 110118124A TW 110118124 A TW110118124 A TW 110118124A TW I776514 B TWI776514 B TW I776514B
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- gate electrode
- work function
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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Abstract
根據本發明的一些實施例,一種裝置包含:一閘極介電質,其在一基板上方;一閘極電極,其在該閘極介電質上方,該閘極電極包含:一功函數調諧層,其在該閘極介電質上方;一膠合層,其在該功函數調諧層上方;一填充層,其在該膠合層上方;及一空隙,其由該填充層、該膠合層及該功函數調諧層之至少一者之內表面定義,該等內表面處之該閘極電極之一材料包含一功函數調諧元素。
Description
本發明實施例係有關半導體裝置及方法。
半導體裝置用於多種電子應用中,諸如例如個人電腦、蜂巢式電話、數位相機及其他電子設施。通常藉由以下步驟製造半導體裝置:在一半導體基板上方循序沉積絕緣或介電層、導電層及半導體材料層;及使用微影術圖案化各種材料層以在其上形成電路組件及元件。
半導體工業繼續藉由不斷減小最小構件大小來改良各種電子組件(例如,電晶體、二極體、電阻器、電容器等)之整合密度,此容許將更多組件整合至一給定區域中。
根據本發明的一實施例,一種裝置包括:一閘極介電質,其在一基板上方;一閘極電極,其在該閘極介電質上方,該閘極電極包括:一功函數調諧層,其在該閘極介電質上方;一膠合層,其在該功函數調諧層上方;一填充層,其在該膠合層上方;及一空隙,其由該填充層、該膠合層及該功函數調諧層之至少一者之內表面定義,該等內表面處之該閘極電極之一材料包含一功函數調諧元素。
根據本發明的一實施例,一種裝置包括:一第一電晶體,其包括:一第一通道區,該第一通道區具有一第一長度;及一第一閘極結構,其在該第一通道區上方,該第一閘極結構包括一第一閘極電極,該第一閘極電極具有在其中之一空隙;及一第二電晶體,其包括:一第二通道區,該第二通道區具有一第二長度,該第二長度大於該第一長度;及一第二閘極結構,其在該第二通道區上方,該第二閘極結構包括一第二閘極電極,該第二閘極電極不具有空隙,該第二閘極電極具有不同於該第一閘極電極之一功函數。
根據本發明的一實施例,一種方法包括:移除一虛設閘極以在閘極間隔件之間形成一凹槽;將一閘極介電層沉積於該凹槽中;將閘極電極層沉積於該閘極介電層上,該等閘極電極層之內表面定義一空隙;平坦化該等閘極電極層之頂表面,直至在該等閘極電極層之該等頂表面處暴露該空隙;及在該空隙中執行一第一閘極處理製程,該第一閘極處理製程增加定義該空隙之該等閘極電極層之該等內表面處之一功函數調諧元素之一濃度。
下列揭露提供用於實施本揭露之不同構件之許多不同實施例或實例。在下文描述組件及配置之特定實例以簡化本揭露。當然,此等僅為實例且不旨在為限制性。例如,在下列描述中之在一第二構件上方或其上形成一第一構件可包含其中第一構件及第二構件形成直接接觸之實施例,且亦可包含其中可在第一構件與第二構件之間形成額外構件以使得第一構件及第二構件可不直接接觸之實施例。另外,本揭露可在各種實例中重複參考數字及/或字母。此重複係出於簡單及清晰之目的且本身並不指示所論述之各種實施例及/或構形之間的一關係。
此外,為便於描述,諸如「在……下方」、「在……下」、「下」、「在……上方」、「上」及類似者之空間相對術語在本文中可用來描述如圖中繪示之一個元件或構件與另一(些)元件或構件之關係。除圖中描繪之定向外,空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或按其他定向)且因此可同樣解釋本文中使用之空間相對描述符。
根據各種實施例,裝置經形成具有短長度通道區及長長度通道區。在通道區上方形成閘極電極。短長度通道區上方之閘極電極經形成具有空隙,且長長度通道區上方之閘極電極經形成不具有空隙(或至少具有較小空隙)。執行一或多個閘極處理製程以修改裝置之功函數。該(等)閘極處理製程對具有空隙之閘極電極(例如,短長度通道區上方之彼等)之影響大於對不具有空隙之閘極電極(例如,長長度通道區上方之彼等)之影響。因此,即使在跨一整個基板執行該(等)閘極處理製程時,該(等)閘極處理製程仍可用於選擇性地調諧一些裝置之臨限電壓。
圖1繪示根據一些實施例之一三維視圖中之簡化鰭式場效電晶體(FinFET)之一實例。為繪示清晰起見,省略FinFET之一些其他構件(下文論述)。所繪示FinFET可電連接或耦合,使得作為例如一個電晶體或多個電晶體(諸如兩個電晶體)操作。
FinFET包含從一基板50延伸之鰭片52。淺溝槽隔離(STI)區56放置於基板50上方,且鰭片52在相鄰STI區56上方且從相鄰STI區56之間突出。儘管STI區56被描述/繪示為與基板50分離,然如本文中使用,術語「基板」可用於指代僅半導體基板或包含隔離區之一半導體基板。另外,儘管鰭片52被繪示為基板50之一單一連續材料,然鰭片52及/或基板50可包含一單一材料或複數個材料。在此內容脈絡中,鰭片52指代在相鄰STI區56之間延伸之部分。
閘極介電質112沿著側壁且在鰭片52之頂表面上方,且閘極電極114在閘極介電質112上方。源極/汲極區88放置於鰭片52相對於閘極介電質112及閘極電極114之相對側中。閘極間隔件82將源極/汲極區88與閘極介電質112及閘極電極114分離。一層間介電質(ILD) 92放置於源極/汲極區88及STI區56上方。在其中形成多個電晶體之實施例中,可在各種電晶體之間共用源極/汲極區88。在其中由多個鰭片52形成一個電晶體之實施例中,相鄰源極/汲極區88可電連接,諸如透過藉由磊晶生長來合併源極/汲極區88,或透過使用一相同源極/汲極接點耦合源極/汲極區88。
圖1進一步繪示若干參考剖面。剖面A-A沿著一鰭片52之一縱向軸且在例如FinFET之源極/汲極區88之間的一電流流動之一方向上。剖面B-B垂直於剖面A-A且沿著一閘極電極114之一縱向軸且在例如垂直於FinFET之源極/汲極區88之間的電流流動方向之一方向上。剖面C-C平行於剖面B-B且延伸穿過FinFET之源極/汲極區88。為清晰起見,隨後圖參考此等參考剖面。
圖2至圖19B係根據一些實施例之製造FinFET之中間階段之各種視圖。圖2、圖3及圖4係三維視圖。圖5A、圖6A、圖7A、圖8A、圖9A、圖10A、圖10B、圖11A、圖11B、圖12A、圖12B、圖13A、圖13B、圖14A、圖14B、圖18A及圖19A係沿著與圖1中之參考剖面A-A類似之一剖面繪示之剖面圖。圖5B、圖6B、圖7B、圖8B、圖9B、圖15A、圖15B、圖16A、圖16B、圖17A、圖17B、圖18B及圖19B係沿著與圖1中之參考剖面B-B類似之一剖面繪示之剖面圖。圖6C及圖6D係沿著與圖1中之參考剖面C-C類似之一剖面繪示之剖面圖。
在圖2中,提供一基板50。基板50可為一半導體基板,諸如一塊狀半導體、一絕緣體上覆半導體(SOI)基板或類似物,其可經摻雜(例如,具有一p型或一n型摻雜劑)或無摻雜。基板50可為一晶圓,諸如一矽晶圓。一般言之,一SOI基板係形成於一絕緣體層上之一半導體材料之一層。絕緣體層可為例如一埋入式氧化物(BOX)層、氧化矽層或類似物。在一基板(通常,一矽基板或玻璃基板)上提供絕緣體層。亦可使用其他基板,諸如一多層或梯度基板。在一些實施例中,基板50之半導體材料可包含:矽;鍺;一化合物半導體,其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;一合金半導體,其包含矽鍺、磷砷化鎵、砷化鋁鎵、砷化銦鎵、磷化銦鎵及/或磷砷化銦鎵;或其等之組合。
基板50具有一n型區50N及一p型區50P。n型區50N可用於形成n型裝置,諸如NMOS電晶體,例如,n型FinFET。p型區50P可用於形成p型裝置,諸如PMOS電晶體,例如,p型FinFET。n型區50N可與p型區50P實體地分離,且任何數目個裝置構件(例如,其他作用裝置、摻雜區、隔離結構等)可放置於n型區50N與p型區50P之間。
在基板50中形成鰭片52。鰭片52係半導體條。在一些實施例中,可藉由在基板50中蝕刻溝槽而在基板50中形成鰭片52。蝕刻可為任何可接受蝕刻製程,諸如一反應離子蝕刻(RIE)、中性射束蝕刻(NBE)、類似物或其等之一組合。蝕刻可為非等向性的。
可藉由任何適合方法圖案化鰭片52。例如,可使用一或多個光微影製程(包含雙重圖案化或多重圖案化製程)圖案化結構。一般言之,雙重圖案化或多重圖案化製程組合光微影與自對準製程,從而容許產生具有例如小於原本可使用一單一直接光微影製程獲得之間距之圖案。例如,在一項實施例中,在一基板上方形成一犧牲層且使用一光微影製程圖案化該犧牲層。使用一自對準製程與圖案化犧牲層並排形成間隔件。接著移除犧牲層,且接著可使用剩餘間隔件以圖案化鰭片52。在一些實施例中,遮罩(或其他層)可保留在鰭片52上。
在基板50上方及相鄰鰭片52之間形成STI區56。作為形成STI區56之一實例,可在基板50上方及相鄰鰭片52之間形成一絕緣材料。絕緣材料可為氧化物(諸如氧化矽)、氮化物、類似物或其等之一組合,且可藉由一高密度電漿化學氣相沉積(HDP-CVD)、可流動CVD (FCVD) (例如,一遠端電漿系統中之一基於CVD之材料沉積及後固化以使其轉換為另一材料,諸如氧化物)、類似物或其等之一組合形成。可使用藉由任何可接受製程形成之其他絕緣材料。在一些實施例中,絕緣材料係藉由FCVD形成之氧化矽。一旦形成絕緣材料,便可執行一退火製程。在一實施例中,絕緣材料經形成,使得過量絕緣材料覆蓋鰭片52。儘管STI區56被繪示為一單一層,然一些實施例可利用多個層。例如,在一些實施例中,可首先沿著基板50及鰭片52之一表面形成一襯層(未展示)。此後,可在襯層上方形成一填充材料,諸如上文論述之彼等。接著將一移除製程應用於絕緣材料以移除鰭片52上方之過量絕緣材料。在一些實施例中,可利用一平坦化製程,諸如一化學機械拋光(CMP)、一深蝕刻製程、其等之組合或類似物。平坦化製程暴露鰭片52,使得在平坦化製程完成之後,鰭片52及絕緣材料之頂表面共面(在製程變化內)。在其中一遮罩保留在鰭片52上之實施例中,平坦化製程可暴露遮罩或移除遮罩,使得在平坦化製程完成之後,遮罩或鰭片52 (分別)及絕緣材料之頂表面共面(在製程變化內)。接著使絕緣材料凹陷以形成STI區56。絕緣材料經凹陷,使得n型區50N及p型區50P中之鰭片52之上部部分從相鄰STI區56之間突出。此外,STI區56之頂表面可具有如繪示之一平坦表面、一凸表面、一凹表面(諸如碟形)或其等之一組合。STI區56之頂表面可藉由一適當蝕刻形成為平坦、凸的及/或凹的。可使用一可接受蝕刻製程使STI區56凹陷,諸如對絕緣材料之材料具有選擇性(例如,以比鰭片52之材料更快之一速率蝕刻絕緣材料之材料)之蝕刻製程。例如,可使用例如稀氫氟酸(dHF)移除氧化物。
關於圖2描述之製程僅為可如何形成鰭片52之一個實例。在一些實施例中,可藉由一磊晶生長製程形成鰭片52。例如,可在基板50之一頂表面上方形成一介電層,且可使溝槽蝕刻穿過介電層以暴露下層基板50。可在溝槽中磊晶地生長同質磊晶結構,且可使介電層凹陷,使得同質磊晶結構從介電層突出以形成鰭片。另外,在一些實施例中,異質磊晶結構可用於鰭片52。例如,鰭片52可為凹陷的,且可在凹陷材料上方磊晶地生長不同於鰭片52之一材料。在此等實施例中,鰭片52包括凹陷材料以及放置於凹陷材料上方之磊晶生長材料。在一甚至進一步實施例中,可在基板50之一頂表面上方形成介電層,且可使溝槽蝕刻穿過介電層。接著可使用不同於基板50之一材料在溝槽中磊晶地生長異質磊晶結構,且可使介電層凹陷,使得異質磊晶結構從介電層突出以形成鰭片52。在其中磊晶地生長同質磊晶或異質磊晶結構之一些實施例中,可在生長期間原位摻雜磊晶生長材料,此可避免先前及隨後植入,但原位及植入摻雜可一起使用。
仍此外,在n型區50N (例如,一NMOS區)中磊晶地生長不同於p型區50P (例如,一PMOS區)中之材料之一材料可為有利的。在各種實施例中,鰭片52之上部部分可由矽鍺(SiX
Ge1-x
,其中x可在0至1之範圍內)、碳化矽、純或實質上純鍺、一III-V族化合物半導體、一II-VI族化合物半導體或類似物形成。例如,用於形成III-V族化合物半導體之可用材料包含(但不限於)砷化銦、砷化鋁、砷化鎵、磷化銦、氮化鎵、砷化銦鎵、砷化銦鋁、銻化鎵、銻化鋁、磷化鋁、磷化鎵及類似物。
此外,可在鰭片52及/或基板50中形成適當阱(未展示)。在一些實施例中,可在n型區50N中形成一p型阱,且可在p型區50P中形成一n型阱。在一些實施例中,在n型區50N及p型區50P兩者中形成p型阱或一n型阱。
在具有不同阱類型之實施例中,n型區50N及p型區50P之不同植入步驟可使用一光阻劑及/或其他遮罩(未展示)來達成。例如,可在n型區50N中之鰭片52及STI區56上方形成一光阻劑。圖案化光阻劑以暴露p型區50P。可使用一旋塗技術形成光阻劑且可使用可接受光微影技術對其圖案化。一旦圖案化光阻劑,便在p型區50P中執行一n型雜質植入,且光阻劑可用作一遮罩以實質上防止n型雜質植入至n型區50N中。n型雜質可為磷、砷、銻或類似物,其等在該區中植入至等於或小於約1018
cm-3
(諸如在約1016
cm-3
至約1018
cm-3
之範圍內)之一濃度。在植入之後,諸如藉由一可接受灰化製程移除光阻劑。
在p型區50P之植入之後,在p型區50P中之鰭片52及STI區56上方形成一光阻劑。圖案化光阻劑以暴露n型區50N。可使用一旋塗技術形成光阻劑且可使用可接受光微影技術對其圖案化。一旦圖案化光阻劑,便可在n型區50N中執行一p型雜質植入,且光阻劑可用作一遮罩以實質上防止p型雜質植入至p型區50P中。p型雜質可為硼、氟化硼、銦或類似物,其等在該區中植入至等於或小於1018
cm-3
(諸如在約1016
cm-3
至約1018
cm-3
之範圍內)之一濃度。在植入之後,可諸如藉由一可接受灰化製程移除光阻劑。
在n型區50N及p型區50P之植入之後,可執行一退火以修復植入損傷且活化所植入之p型及/或n型雜質。在一些實施例中,可在生長期間原位摻雜磊晶鰭片之生長材料,此可避免植入,但原位及植入摻雜可一起使用。
在圖3中,在鰭片52上形成一虛設介電層62。虛設介電層62可為例如氧化矽、氮化矽、其等之一組合或類似物,且可根據可接受技術沉積或熱生長。在虛設介電層62上方形成一虛設閘極層64,且在虛設閘極層64上方形成一遮罩層66。虛設閘極層64可沉積於虛設介電層62上方,且接著諸如藉由一CMP來平坦化。遮罩層66可沉積於虛設閘極層64上方。虛設閘極層64可為一導電或非導電材料且可選自包含非晶矽、多晶矽(polycrystalline-silicon/polysilicon)、多晶矽鍺(多晶SiGe)、金屬氮化物、金屬矽化物、金屬氧化物及金屬之一群組。虛設閘極層64可藉由物理氣相沉積(PVD)、CVD、濺鍍沉積或用於沉積選定材料之其他技術來沉積。虛設閘極層64可由具有對蝕刻隔離區(例如,STI區56及/或虛設介電層62)之一高蝕刻選擇性之其他材料製成。遮罩層66可包含例如氮化矽、氧氮化矽或類似物之一或多個層。在此實例中,跨n型區50N及p型區50P形成一單一虛設閘極層64及一單一遮罩層66。在所繪示實施例中,虛設介電層62覆蓋STI區56,在STI區56上方及虛設閘極層64與STI區56之間延伸。在另一實施例中,虛設介電層62僅覆蓋鰭片52。
在圖4中,可使用可接受光微影及蝕刻技術圖案化遮罩層66以形成遮罩76。接著,可將遮罩76之圖案轉移至虛設閘極層64以形成虛設閘極74。在一些實施例中,亦可藉由一可接受蝕刻技術將遮罩76之圖案轉移至虛設介電層62以形成虛設介電質72。虛設閘極74覆蓋鰭片52之各自通道區58。遮罩76之圖案可用於實體地分離虛設閘極74與鄰近虛設閘極74。虛設閘極74亦可具有實質上垂直於鰭片52之長度方向之一長度方向。
圖5A至圖19B繪示製造實施例裝置之各種額外步驟。圖5A至圖19B繪示n型區50N及p型區50P之任一者中之構件。例如,圖5A至圖19B中繪示之結構可適用於n型區50N及p型區50P兩者。在各圖隨附之文字中描述n型區50N及p型區50P之結構中之差異(若存在)。
在圖5A及圖5B中,在虛設閘極74及遮罩76之側壁上形成閘極間隔件82。可藉由保形地沉積一或多個絕緣材料且隨後蝕刻該(等)絕緣材料來形成閘極間隔件82。該(等)絕緣材料可由低介電係數材料形成,諸如氧化矽、氮化矽、碳氮化矽、氧碳氮化矽、其等之一組合或類似物,其等可藉由一保形沉積製程形成,諸如化學氣相沉積(CVD)、電漿輔助化學氣相沉積(PECVD)、原子層沉積(ALD)或類似物。當蝕刻時,該(等)絕緣材料具有留在虛設閘極74及遮罩76之側壁上之部分(因此形成閘極間隔件82)。在蝕刻之後,閘極間隔件82可具有筆直側壁(如繪示)或可具有彎曲側壁(未繪示)。在一些實施例中,閘極間隔件82之該(等)絕緣材料係氧碳氮化矽(例如,SiOx
Ny
C1-x-y
,其中x及y在0至1之範圍內)。例如,絕緣材料之各層可具有一類似或不同氧碳氮化矽組合物。
亦可執行用於輕摻雜汲極/汲極(LDD)區86之植入。在具有不同裝置類型之實施例中,類似於先前論述之用於阱之植入,可在n型區50N上方形成一遮罩(諸如一光阻劑),同時暴露p型區50P,且可將適當類型(例如,p型)雜質植入至p型區50P中之經暴露鰭片52中。接著,可移除遮罩。隨後,可在p型區50P上方形成一遮罩(諸如一光阻劑),同時暴露n型區50N,且可將適當類型雜質(例如,n型)植入至n型區50N中之經暴露鰭片52中。接著,可移除遮罩。n型雜質可為先前論述之n型雜質之任何者,且p型雜質可為先前論述之p型雜質之任何者。LDD區86可具有在約1015
cm-3
至約1019
cm-3
之範圍內之一雜質濃度。一退火可用於修復植入損傷且活化所植入雜質。
在圖6A及圖6B中,在鰭片52中形成磊晶汲極/汲極區88。在鰭片52中形成磊晶源極/汲極區88,使得各虛設閘極74放置於磊晶源極/汲極區88之各自相鄰對之間。在一些實施例中,磊晶源極/汲極區88可延伸至鰭片52中且亦可穿透鰭片52。在一些實施例中,閘極間隔件82用於將磊晶源極/汲極區88與虛設閘極74分離一適當橫向距離,使得磊晶源極/汲極區88不會使所得FinFET之隨後形成閘極短路。可選擇磊晶源極/汲極區88之一材料以在各自通道區58中施加應力,藉此改良效能。
可藉由遮蔽p型區50P且蝕刻n型區50N中之鰭片52之源極/汲極區以在鰭片52中形成凹槽而形成n型區50N中之磊晶源極/汲極區88。凹槽可延伸穿過LDD區86 (參見圖5A)。接著,在凹槽中磊晶地生長n型區50N中之磊晶源極/汲極區88。磊晶源極/汲極區88可包含任何可接受材料,諸如適合於n型FinFET。例如,若鰭片52係矽,則n型區50N中之磊晶源極/汲極區88可包含在通道區58中施加一拉伸應變之材料,諸如矽、碳化矽、磷摻雜碳化矽、磷化矽或類似物。n型區50N中之磊晶源極/汲極區88可具有從鰭片52之各自表面凸起之表面,且可具有小面。
可藉由遮蔽n型區50N且蝕刻p型區50P中之鰭片52之源極/汲極區以在鰭片52中形成凹槽而形成p型區50P中之磊晶源極/汲極區88。凹槽可延伸穿過LDD區86 (參見圖5A)。接著,在凹槽中磊晶地生長p型區50P中之磊晶源極/汲極區88。磊晶源極/汲極區88可包含任何可接受材料,諸如適合於p型FinFET者。例如,若鰭片52係矽,則p型區50P中之磊晶源極/汲極區88可包含在通道區58中施加一壓縮應變之材料,諸如矽鍺、硼摻雜矽鍺、鍺、鍺錫或類似物。p型區50P中之磊晶源極/汲極區88可具有從鰭片52之各自表面凸起之表面,且可具有小面。
磊晶源極/汲極區88及/或鰭片52可經植入摻雜劑以形成源極/汲極區,類似於先前論述之用於形成LDD區86之製程,其後接著一退火。源極/汲極區可具有在約1019
cm-3
與約1021
cm-3
之間的一雜質濃度。用於源極/汲極區之n型及/或p型雜質可為先前論述之雜質之任何者。在一些實施例中,可在生長期間原位摻雜磊晶源極/汲極區88。
由於用於在n型區50N及p型區50P中形成磊晶源極/汲極區88之磊晶製程,磊晶源極/汲極區之上表面具有橫向向外擴展超過鰭片52之側壁之小面。在一些實施例中,此等小面導致鄰近磊晶源極/汲極區88合併,如由圖6C繪示。在一些實施例中,鄰近磊晶源極/汲極區88在磊晶製程完成之後保持分離,如由圖6D繪示。用於形成閘極間隔件82之間隔件蝕刻可經調整以亦在鰭片52之側壁上形成鰭片間隔件84。在所繪示實施例中,鰭片間隔件84覆蓋在STI區56上方延伸之鰭片52之側壁之部分,藉此阻止磊晶生長。鄰近鰭片52之間的鰭片間隔件84可合併(如展示),或可分離。在另一實施例中,調整用於形成閘極間隔件82之間隔件蝕刻以不在STI區56上形成鰭片間隔件84,以便容許磊晶生長區延伸至STI區56之表面。
在圖7A及圖7B中,將一第一ILD 92沉積於磊晶源極/汲極區88、閘極間隔件82、STI區56及遮罩76 (若存在)或虛設閘極74上方。第一ILD 92可由一介電材料形成,且可藉由任何適合方法沉積,諸如CVD、電漿輔助CVD (PECVD)或FCVD。可接受介電材料可包含磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、無摻雜矽酸鹽玻璃(USG)或類似物。可使用藉由任何可接受製程形成之其他絕緣材料。
在一些實施例中,在第一ILD 92與磊晶源極/汲極區88、閘極間隔件82、STI區56及遮罩76 (若存在)或虛設閘極74之間形成一接觸蝕刻停止層(CESL) 90。CESL 90可包括具有低於第一ILD 92之材料之一蝕刻速率之一介電材料,諸如氮化矽、氧化矽、氧氮化矽或類似物。
在圖8A及圖8B中,可執行一平坦化製程(諸如一CMP)以使第一ILD 92之頂表面與遮罩76 (若存在)或虛設閘極74之頂表面齊平。平坦化製程亦可移除虛設閘極74上之遮罩76及沿著遮罩76之側壁之閘極間隔件82之部分。在平坦化製程之後,虛設閘極74、閘極間隔件82及第一ILD 92之頂表面共面(在製程變化內)。因此,虛設閘極74之頂表面透過第一ILD 92暴露。在一些實施例中,遮罩76可保留,在此情況中,平坦化製程使第一ILD 92之頂表面與遮罩76之頂表面齊平。
在圖9A及圖9B中,移除遮罩76 (若存在)及虛設閘極74及視情況虛設介電質72且替換為替換閘極結構。替換閘極結構包含閘極介電質112及閘極電極114。如下文將更詳細論述,在不同區中形成具有不同通道長度之替換閘極結構,且將在閘極替換製程期間執行各種處理製程,使得在不同區中形成具有不同臨限電壓之裝置。
圖10A至圖15B係根據一些實施例之形成替換閘極結構之中間階段之剖視圖。繪示類似於圖9A中之一區50R之區中之構件。在所繪示製程中,替換虛設介電質72及虛設閘極74。在一些實施例中,虛設介電質72在一晶粒之一第一區(例如,一核心邏輯區)中被移除且保留在晶粒之一第二區(例如,一輸入/輸出區)中。換言之,可在晶粒之第一區(例如,核心邏輯區)中執行所繪示閘極替換製程,且可在晶粒之第二區中執行其中未移除虛設介電質72之一閘極替換製程。
圖10A、圖11A、圖12A、圖13A及圖14A繪示一密緻區50D,其中形成替換閘極結構。密緻區50D中之閘極結構具有擁有短長度(諸如小於約10 nm之通道長度)之通道區58。對於一些類型之裝置,諸如高速操作之裝置,可期望短通道長度。圖10B、圖11B、圖12B、圖13B及圖14B繪示一稀疏區50S,其中形成替換閘極結構。稀疏區50S中之閘極結構具有擁有長長度(諸如大於約18 nm之通道長度)之通道區58。對於一些類型之裝置,諸如以高功率操作之裝置或在需要低洩漏之應用中,可期望長通道長度。更一般言之,密緻區50D中之裝置之通道長度比稀疏區50S中之裝置之通道長度更短。因此,密緻區50D中之閘極間隔件82比稀疏區50S中之閘極間隔件82彼此更靠近地放置。此外,密緻區50D中之閘極結構具有大於稀疏區50S中之閘極結構之一密度。同時處理且一起論述區50D、50S。在區50D、50D之各者中繪示一單一鰭片52,但應瞭解,區50D、50S之各者可包含來自區50N、50P兩者之鰭片52。換言之,密緻區50D及稀疏區50S可各包含n型裝置及p型裝置。
在圖10A及圖10B中,在一或多個蝕刻步驟中移除遮罩76 (若存在)及虛設閘極74,使得在閘極間隔件82之相對部分之間形成凹槽94。凹槽94暴露閘極間隔件82之側壁。在一些實施例中,藉由一非等向性乾蝕刻製程移除虛設閘極74。例如,蝕刻製程可包含使用(若干)反應氣體之一乾蝕刻製程,該等反應氣體以比第一ILD 92或閘極間隔件82更快之一速率選擇性地蝕刻虛設閘極74。各凹槽94覆蓋一各自鰭片52之一通道區58。在移除期間,當蝕刻虛設閘極74時,虛設介電質72可被用作蝕刻停止層。接著,在移除虛設閘極74之後,可視情況移除虛設介電質72。
在虛設閘極74之圖案化期間,圖案負載效應可導致虛設閘極74接近鰭片52之部分之側壁被蝕刻得少於虛設閘極74遠離鰭片52之部分之側壁。圖案負載效應在密緻區50D中比在稀疏區50S中更顯著,且可隨著技術按比例縮小(例如,隨著虛設閘極74之縱橫比增加)而加劇。因此,密緻區50D中之凹槽94D可具有一瓶狀輪廓形狀,而稀疏區50S中之凹槽94S可具有一四邊形輪廓形狀。在一些實施例中,密緻區50D中之閘極間隔件82之側壁係彎曲側壁,而稀疏區50S中之閘極間隔件82之側壁係筆直側壁(或至少不如密緻區50D中之閘極間隔件82之側壁彎曲)。
凹槽94D之瓶狀輪廓形狀由圖10A中展示之寬度W1
、W2
定義。特定言之,凹槽94D各具有擁有一第一寬度W1
之主要部分94DM
及擁有一第二寬度W2
之一頸部部分94DN
。寬度W1
可在約5 nm至約30 nm之範圍內,且寬度W2
可在約3 nm至約20 nm之範圍內。第一寬度W1
大於第二寬度W2
。此外,第一寬度W1
在延伸遠離於鰭片52之頂表面之一方向D1
上透過主要部分94DM
增加,直至其達到一最大寬度,且接著在方向D1
上透過主要部分94DM
減小。第二寬度W2
可為沿著方向D1
穿過頸部部分94DN
之一恆定寬度。
凹槽94S之四邊形輪廓形狀由圖10B中展示之寬度W3
定義。特定言之,凹槽94S各具有擁有一第三寬度W3
之一單一部分。第三寬度W3
可在約20 nm至約80 nm之範圍內。第三寬度W3
大於第一寬度W1
及第二寬度W2
。第三寬度W3
可為沿著延伸遠離於鰭片52之頂表面之一方向D1
之一恆定寬度。
在圖11A及圖11B中,將一閘極介電層102及閘極電極層104沉積於凹槽94中。閘極介電層102及閘極電極層104包含複數個子層。根據各種實施例,在圖29A至圖29C中展示且結合圖11A及圖11B描述用於閘極介電層102及閘極電極層104之例示性膜堆疊。
閘極介電層102沉積於凹槽94中,諸如沉積於鰭片52之頂表面及閘極間隔件82之側壁上。亦可在第一ILD 92之頂表面上形成閘極介電層102。在一些實施例中,閘極介電層102包含氧化矽、氮化矽、金屬氧化物、金屬矽酸鹽或類似物之一或多個層。儘管閘極介電層102在此實施例中被展示為單層,然在一些實施例中,閘極介電層102可包含多個子層。例如,閘極介電層102可包含藉由熱或化學氧化形成之氧化矽之一界面層102A (圖29A至圖29C)及一上覆高介電係數材料102B (圖29A至圖29C),諸如鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛及其等之組合之金屬氧化物或矽酸鹽。閘極介電層102可包含具有大於約7.0之一介電係數值(k值)之一介電層。閘極介電層102之形成方法可包含分子束沉積(MBD)、ALD、PECVD及類似物。在其中虛設介電質72之部分保留在凹槽94中之實施例中,閘極介電層102包含虛設介電質72之一材料(例如,氧化矽)。
視情況,閘極介電層102之部分經摻雜具有一偶極誘導元素。例如,可在閘極介電層102上方形成一偶極誘導元素之一摻雜層,且執行一退火以將偶極誘導元素從摻雜層驅動至閘極介電層102中。摻雜層可由一偶極誘導元素(諸如鑭、鋁、鈧、釕、鋯、鉺、鎂、鍶或類似物)之氧化物、氮化物或碳化物形成,其可藉由ALD、CVD、PVD或其他適合沉積方法形成。在一些實施例中,摻雜層由鑭之氧化物(例如,LaOX
)形成。一些實施例可利用多個摻雜層。例如,可在一第一區(例如,密緻區50D)中形成一第一摻雜層,且可在一第二區(例如,稀疏區50S)中形成一第二摻雜層。不同區中之摻雜層可具有不同厚度及/或包含不同偶極誘導元素。摻雜層之存在、厚度及材料可基於待形成裝置之所要臨限電壓而變化。例如,使閘極介電層102之部分摻雜具有鑭可降低經形成具有閘極介電層102之經摻雜部分之裝置之臨限電壓。一旦退火完成,閘極介電層102便摻雜具有偶極誘導元素(例如,鑭),且接著可諸如藉由一可接受蝕刻製程移除該(等)摻雜層。
上文描述之製程僅為可如何形成閘極介電層102且摻雜具有偶極誘導元素之一個實例。可使用其他技術形成經摻雜閘極介電層。例如,可形成一第一閘極介電子層,在第一閘極介電子層上方沉積一摻雜層,且執行一退火以將偶極誘導元素從摻雜層驅動至第一閘極介電子層中。接著可移除所移除之摻雜層,且可在第一閘極介電子層上方沉積一第二閘極介電子層。因此,第一閘極介電子層可經摻雜,而第二閘極介電子層係無摻雜的。
閘極電極層104沉積於閘極介電層102上方及凹槽94中。閘極電極層104可包含一含金屬材料,諸如氮化鈦、氧化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、鎢、其等之組合或其等之多層。更特定言之,閘極電極層104包含任何數目個功函數調諧層104A、任何數目個膠合層104B及一填充層104C。
功函數調諧層104A包含任何可接受材料以鑑於待形成裝置之應用將一裝置之一功函數調諧至一所要量,且可使用任何可接受沉積製程來沉積。例如,功函數調諧層104A可由鋁、氮化鋁、鋁化鈦、鉭鋁、氮化鈦碳或類似物形成,其可藉由ALD、CVD、PVD或類似物沉積。在一些實施例中,藉由諸如ALD之一保形製程沉積功函數調諧層104A,此容許一更一致膜厚度。在一些實施例中,藉由諸如PVD之一非保形製程沉積功函數調諧層104A,此容許更大製造處理量。儘管功函數調諧層104A在此實施例中被展示為單層,然在一些實施例中,功函數調諧層104A可包含多個子層。例如,功函數調諧層104A可包含一第一調諧層104A1
(參見圖29A至圖29C),可包含一第二調諧層104A2
(參見圖29B及圖29C),且可進一步包含一第三調諧層104A3
(參見圖29C)。在一些實施例中,在膠合層104B與填充層104C之間僅形成一單一功函數調諧層104A (參見圖29A)。在一些實施例中,在膠合層104B與填充層104C之間形成複數個功函數調諧層104A (參見圖29B及圖29C)。可基於裝置之所要臨限電壓形成功函數調諧層104A。
可在不同區中形成功函數調諧層104A之不同結構。作為形成功函數調諧層104A之一實例,一第一調諧層104A1
可沉積於全部區中且接著被蝕刻以移除非所要區中之第一調諧層104A1
之部分。一第二調諧層104A2
可接著沉積於全部區中(及第一調諧層104A1
上),接著被蝕刻以移除非所要區中之第二調諧層104A2
之部分。一第三調諧層104A3
可接著沉積於全部區中(及第二調諧層104A2
上),接著被蝕刻以移除非所要區中之第三調諧層104A3
之部分。因此,一些區可含有第一調諧層104A1
,其他區可含有第一調諧層104A1
及第二調諧層104A2
,且又其他區可含有第一調諧層104A1
、第二調諧層104A2
及第三調諧層104A3
。
可在功函數調諧層104A之前形成一或多個封蓋層。在一些實施例中,沉積、移除(例如,藉由蝕刻)及再沉積封蓋層,此幫助移除可能保留在閘極介電層102之頂表面上之殘餘偶極誘導元素(例如,鑭)。可在移除封蓋層之後且在再沉積封蓋層之前執行一退火,以幫助移除殘餘偶極誘導元素。
膠合層104B包含任何可接受材料以促進黏附且防止擴散。例如,膠合層104B可由一金屬或金屬氮化物形成,諸如氮化鈦、鋁化鈦、氮化鈦鋁、矽摻雜氮化鈦、氮化鉭或類似物,其可藉由ALD、CVD、PVD或類似物沉積。在一些實施例中,藉由諸如ALD之一保形製程沉積膠合層104B,此容許一更一致膜厚度。在一些實施例中,藉由諸如PVD之一非保形製程沉積膠合層104B,此容許更大製造處理量。
填充層104C包含具有一低電阻之任何可接受材料。例如,填充層104C可由一金屬形成,諸如鎢(W)、鋁(Al)、鈷(Co)、釕(Ru)、其等之組合或類似物,其可藉由ALD、CVD、PVD或類似物沉積。在一些實施例中,藉由諸如ALD之一保形製程沉積填充層104C,此容許一更一致膜厚度。在一些實施例中,藉由諸如PVD之一非保形製程沉積填充層104C,此容許更大製造處理量。如下文將更詳細論述,填充層104C完全填充凹槽94S之剩餘部分,但填充層104C僅部分填充凹槽94D之剩餘部分,使得形成空隙104D。
在閘極電極層104之沉積期間,在凹槽94D之頸部部分94DN
中發生夾斷,使得閘極電極層104在凹槽94D中之形成不完整,藉此形成空隙104D。閘極電極層104完全填充凹槽94D之頸部部分94Dn
,但閘極電極層104僅部分填充凹槽94D之主要部分94DM
以定義空隙104D。空隙104D包含未被閘極電極層104填充之凹槽94D之剩餘部分。在功函數調諧層104A (例如,調諧層104A1
、104A2
、104A3
)、膠合層104B或填充層104C之任何者之沉積期間可發生夾斷。其中發生夾斷之層取決於凹槽94D之寬度、所沉積層之數目及用於沉積層之沉積製程之保形性。例如,當形成較少功函數調諧層104A (例如,圖29A之實施例)或其中使用保形沉積製程時,可在處理後期發生夾斷,諸如在填充層104C之沉積期間。相反地,當形成較多功函數調諧層104A (例如,圖29B及圖29C之實施例)或其中使用非保形沉積製程時,可在處理前期發生夾斷,諸如在膠合層104B或功函數調諧層104A之一者之沉積期間。
在此實施例中,在一些填充層104C沉積於凹槽94D之主要部分94DM
中之後,在填充層104C之沉積期間發生夾斷。在其中形成一個功函數調諧層(例如,圖29A之實施例)或其中使用保形沉積製程之實施例中,可發生此夾斷。因此,空隙104D暴露填充層104C之表面,且填充層104C將空隙104D與膠合層104B及功函數調諧層104A分離。在此等實施例中,空隙104D最初形成具有淚滴形輪廓形狀。空隙104D之淚滴形輪廓形狀可具有在約5 nm至約80 nm之範圍內之一高度及在約2 nm至約8 nm之範圍內之一最大寬度。
在圖12A及圖12B中,執行一閘極處理製程106以修改閘極電極層104之功函數。閘極處理製程106將一或多個功函數調諧元素併入至一或多個閘極電極層104中,此可增加閘極電極114之功函數。功函數調諧元素亦可穿透閘極電極層104且併入至閘極介電層102中。閘極處理製程106包含一氟化處理製程(其併入氟)、一氮化處理製程(其併入氮)、一氧化處理製程(其併入氧)、一沉積製程(其併入氯、硼及/或矽)、其等之組合或類似物。藉由閘極處理製程106併入之功函數調諧元素之類型及數量可基於待形成裝置之所要臨限電壓來控制。例如,併入氟可增加p型裝置之閘極電極層104之功函數,藉此降低裝置之臨限電壓。
在一些實施例中,閘極處理製程106包含一氟化處理製程,其中閘極介電層102及/或閘極電極層104暴露至氟。氟化處理製程可在諸如一蝕刻腔之一腔中執行。在腔中施配一氣體源。氣體源包含一氟源氣體及一載氣。氟源氣體可為氟(F2
)氣體、三氟化氮(NF3
)、氟化鎢(VI) (WF6
)、其等之組合或類似物。載氣可為一惰性氣體,諸如氬(Ar)、氦(He)、氙(Xe)、氖(Ne)、氪(Kr)、氡(Rn)、其等之組合或類似物。在一些實施例中,氟源氣體係氣體源之約10%至約50%,且載氣係氣體源之約50%至約90%。氣體源可以從約50 sccm至約1000 sccm之一流速施配。氣體源中之氟經併入至閘極電極層104 (例如,功函數調諧層104A、膠合層104B及/或填充層104C)中,藉此改變受影響之閘極電極層104之功函數。氣體源中之氟亦可併入至閘極介電層102中,藉此改良閘極介電層102之品質。例如,氟可使閘極介電層102中之氧空位鈍化,從而減少其洩漏且增加裝置之可靠性。氣體源被保持在腔中,直至閘極介電層102及/或閘極電極層104已被氟化一所要量。在一些實施例中,氟化處理製程在從約25°C至約550°C之一溫度下執行,且達到從約10秒至約2700秒之一持續時間。
在一些實施例中,閘極處理製程106包含一氮化處理製程,其中閘極介電層102及/或閘極電極層104暴露至氮。氮化處理製程可在諸如一蝕刻腔之一腔中執行。在腔中施配一氣體源。氣體源包含一氮源氣體及一載氣。氮源氣體可為氨(NH3
)、裂解氨、氮(N2
)與氫(H2
)氣體之一組合、其等之組合或類似物。載氣可為一惰性氣體,諸如氬(Ar)、氦(He)、氙(Xe)、氖(Ne)、氪(Kr)、氡(Rn)、其等之組合或類似物。在一些實施例中,氮源氣體係氣體源之約10%至約50%,且載氣係氣體源之約50%至約90%。氣體源可以從約500 sccm至約5000 sccm之一流速施配。在一些實施例中,諸如當氮源氣體係N2
與H2
之一組合時,從氣體源產生一電漿,使得產生氮自由基及對應離子。氣體源/電漿中之氮經併入至閘極電極層104 (例如,功函數調諧層104A、膠合層104B及/或填充層104C)中,藉此改變受影響之閘極電極層104之功函數。氣體源/電漿被保持在腔中,直至閘極介電層102及/或閘極電極層104已被硝化一所要量。在一些實施例中,氮化處理製程在從約100°C至約650°C之一溫度下執行,且達到從約10秒至約2700秒之一持續時間。
在一些實施例中,閘極處理製程106包含一氧化處理製程,其中閘極介電層102及/或閘極電極層104暴露至氧。例如,可在含有氧及一惰性氣體之一環境中執行一低溫退火。惰性氣體可為氬(Ar)、氦(He)、氙(Xe)、氖(Ne)、氪(Kr)、氡(Rn)、其等之組合或類似物。在一些實施例中,氧係環境之約1%至約10%,且惰性氣體係環境之約90%至約99%。低溫退火可在從約150°C至約500°C之一溫度下執行,且達到從約10秒至約2700秒之一持續時間。氧化處理製程亦可諸如藉由使閘極電極層104密緻而增加待形成裝置之可靠性。
在一些實施例中,閘極處理製程106包含一沉積製程,其中閘極介電層102及/或閘極電極層104暴露至氯、硼及/或矽。例如,可藉由CVD在閘極電極層104上沉積含有氯、硼及/或矽之一薄層。沉積製程可在諸如一沉積腔之一腔中執行。在腔中施配一氣體源。氣體源包含(若干)前驅氣體及一載氣。該(等)前驅氣體可為三氯化硼(BCl3
)、矽烷(SiH4
)、二矽烷(Si2
H6
)、二硼烷(B2
H6
)、其等之組合或類似物。載氣可為一惰性氣體,諸如氬(Ar)、氦(He)、氙(Xe)、氖(Ne)、氪(Kr)、氡(Rn)、其等之組合或類似物。在一些實施例中,該(等)前驅氣體係氣體源之約1%至約10%,且載氣係氣體源之約90%至約99%。氣體源可以從約50 sccm至約500 sccm之一流速施配。該(等)前驅氣體可組合以將包含所要元素(例如,氯、硼、矽等)之一層沉積於閘極電極層104上,藉此改變受影響之閘極電極層104之功函數。氣體源被保持在腔中,直至一所要量之元素已沉積於閘極介電層102及/或閘極電極層104上。在一些實施例中,沉積製程在從約300°C至約650°C之一溫度下執行,且達到從約10秒至約1000秒之一持續時間。
在圖13A及圖13B中,執行一平坦化製程(諸如一CMP)以移除閘極介電層102及閘極電極層104之過量部分,該等過量部分位於第一ILD 92之頂表面上方。凹槽94中之閘極介電層102之剩餘部分形成閘極介電質112。凹槽94中之閘極電極層104之剩餘部分形成閘極電極114。在平坦化製程完成之後,閘極電極114、閘極介電質112、第一ILD 92及閘極間隔件82之頂表面共面(在製程變化內)。閘極介電質112及閘極電極114形成FinFET之替換閘極結構。閘極介電質112及閘極電極114可各被統稱為一「閘極堆疊」。閘極結構沿著鰭片52之一通道區58之側壁延伸。
密緻區50D中之閘極電極114D具有放置於其中之空隙104D。定時平坦化製程可用於在閘極結構達到一所要高度之後停止閘極介電層102及閘極電極層104之平坦化。在所繪示實施例中,控制閘極結構之高度,使得空隙104D被平坦化製程破壞,此有效地改造凹槽94D (參見圖10A及圖11A)。例如,可執行平坦化製程,直至移除凹槽94D之頸部部分94DN
中之閘極電極層104之部分(參見圖13A)且在閘極電極114D之頂表面處暴露空隙104D,使得閘極電極114D之頂表面在閘極電極114D之側壁之間不連續地延伸。在另一實施例中,控制閘極結構之高度,使得空隙104D不會被平坦化製程破壞。例如,可停止平坦化製程,同時保留凹槽94D之頸部部分94DN
中之閘極電極層104之部分(參見圖13A)且不在閘極電極114S之頂表面處暴露空隙104D,使得閘極電極114D之頂表面在閘極電極114D之側壁之間連續地延伸。
稀疏區50S中之閘極電極114S可不具有設置於其中之空隙。因此,不在閘極電極114S之頂表面處暴露空隙,使得閘極電極114S之頂表面在閘極電極114S之側壁之間連續地延伸。在另一實施例中,閘極電極114S亦具有空隙,但具有小於閘極電極114D之空隙。
在圖14A及圖14B中,執行一閘極處理製程116以修改閘極電極114之功函數。閘極處理製程116將一或多個功函數調諧元素併入至一或多個閘極電極層104中,此可增加閘極電極114之功函數。閘極處理製程116可包含選自上文針對圖12A及圖12B論述之閘極處理製程106之相同候選製程群組之製程。閘極處理製程106及閘極處理製程116可為相同製程,或可包含不同製程。例如,執行閘極處理製程116可包含重複閘極處理製程106,或可包含執行一不同閘極處理製程。由閘極處理製程116併入之功函數調諧元素之類型及數量可基於待形成裝置之所要臨限電壓來控制。例如,併入氟可增加p型裝置之閘極電極114之功函數,藉此降低裝置之臨限電壓。
如上文提及,閘極電極114D具有可暴露於閘極電極114D之頂表面處之空隙104D,而閘極電極114S可不具有空隙(或至少具有較小空隙)。當空隙104D暴露於閘極電極114D之頂表面處時,空隙104D暴露閘極電極114D之內表面,且在空隙104D中執行閘極處理製程116。因此,閘極電極114D與閘極電極114S相比具有暴露至閘極處理製程116之更多表面積。因此,閘極處理製程116對閘極電極114D之功函數之修改多於其對閘極電極114S之功函數之修改。特定言之,閘極處理製程116增加閘極電極114D及閘極電極114S兩者中之功函數調諧元素之濃度,但其對閘極電極114D中之功函數調諧元素之濃度之增加大於其對閘極電極114S中之功函數調諧元素之濃度之增加。在一些實施例中,閘極處理製程116修改閘極電極114D之功函數,而歸因於閘極電極114S中缺乏空隙,實質上不發生閘極電極114S之功函數之修改。此外,閘極處理製程116在閘極電極114D之內表面處引入功函數調諧元素104E (或至少增加其等之一濃度),使得內表面包括功函數調諧元素104E。例如,閘極電極114D之內表面附近之閘極電極114D之部分可包含閘極電極114D及功函數調諧元素104E之材料。閘極電極114S可實質上不具有功函數調諧元素104E。
圖15A至圖17B係根據一些實施例之形成替換閘極結構之進一步中間階段之剖視圖。繪示類似於圖9B之區中之構件,惟展示四個閘極結構除外。圖15A、圖16A及圖17A繪示密緻區50D,而圖15B、圖16B及圖17B繪示稀疏區50S。在所繪示製程中,形成隔離區以劃分閘極電極114。因此,隔離區分離具有相同縱向軸之閘極電極114。隔離區提供不同裝置之閘極電極114之間的實體及電隔離。
在圖15A及圖15B中,開口122經形成穿過閘極電極114。開口122亦可經形成穿過閘極介電質112,在此情況中,暴露STI區56。可使用可接受光微影及蝕刻技術形成開口122。蝕刻可為使用具有開口122之一圖案之一蝕刻遮罩(諸如一光阻劑)之任何可接受蝕刻製程,諸如一反應離子蝕刻(RIE)、中性射束蝕刻(NBE)、類似物或其等之一組合。蝕刻可為非等向性的。
在圖16A及圖16B中,執行一閘極處理製程126以修改閘極電極114之功函數。閘極處理製程126將一或多個功函數調諧元素併入至一或多個閘極電極層104中,此可增加閘極電極114之功函數。閘極處理製程126可包含選自上文針對圖12A及圖12B論述之閘極處理製程之相同候選製程群組之製程。閘極處理製程106及閘極處理製程126可為相同製程,或可包含不同製程。例如,執行閘極處理製程126可包含重複閘極處理製程106,或可包含執行一不同閘極處理製程。藉由閘極處理製程126併入之功函數調諧元素之類型及數量可基於待形成裝置之所要臨限電壓來控制。例如,併入氟可增加p型裝置之閘極電極114之功函數,藉此降低裝置之臨限電壓。
如上文提及,閘極電極114D具有空隙104D,而閘極電極114S可不具有空隙(或至少具有較小空隙)。空隙104D暴露閘極電極114D之內表面(參見圖14A),使得閘極電極114D與閘極電極114S相比具有暴露至閘極處理製程126之更多表面積。開口122為閘極電極114D之端部處之空隙104D提供一額外入口。因而,可在閘極電極114D之頂表面及/或側壁處暴露空隙104D,藉此增加閘極處理製程126處理閘極電極114D之內表面之機會。此外,當未在閘極電極114D之頂表面處暴露空隙104D時,形成開口122可容許在閘極電極114D之側壁處暴露空隙104D。類似於上文針對圖14A及圖14B論述之閘極處理製程116,閘極處理製程126對閘極電極114D之功函數之修改多於其對閘極電極114S之功函數之修改。特定言之,閘極處理製程126增加閘極電極114D及閘極電極114S兩者中之功函數調諧元素之濃度,但其對閘極電極114D中之功函數調諧元素之濃度之增加大於其對閘極電極114S中之功函數調諧元素之濃度之增加。在一些實施例中,閘極處理製程126修改閘極電極114D之功函數,而歸因於閘極電極114S中缺乏空隙,實質上不發生閘極電極114S之功函數之修改。此外,閘極處理製程126在閘極電極114D之內表面處引入功函數調諧元素104E (或至少增加其等之一濃度) (參見圖14A)。例如,閘極電極114D之內表面附近之閘極電極114D之部分可包含閘極電極114D及功函數調諧元素104E之材料。閘極電極114S可實質上不具有功函數調諧元素104E。
在所繪示實施例中,執行閘極處理製程116、126兩者。可省略閘極處理製程116、126之一者。在一些實施例中,執行閘極處理製程116且省略閘極處理製程126。在一些實施例中,執行閘極處理製程126且省略閘極處理製程116。基於是否在閘極電極114D之頂表面處暴露空隙104D,可包含或省略閘極處理製程116、126。例如,當在閘極電極114D之頂表面處暴露空隙104D時,可執行閘極處理製程116且可省略閘極處理製程126,或當未在閘極電極114D之頂表面處暴露空隙104D時,可執行閘極處理製程126且可省略閘極處理製程116。基於待形成裝置之所要功函數調諧元素濃度(及因此臨限電壓),亦可包含或省略閘極處理製程116、126。如上文提及,由於閘極處理製程116、126,實質上可不發生閘極電極114S之功函數之修改。在其中執行閘極處理製程116、126兩者之實施例中,閘極電極114D可具有在約1 at.%至約28 at.%之範圍內之功函數調諧元素(例如,氟、氮、氧、氯、硼、矽等)之一濃度,諸如至少5×1016
cm-3
之一濃度,而閘極電極114S可具有實質上為零之功函數調諧元素之一濃度。在閘極電極114D、114S中包含功函數調諧元素至此等範圍內之濃度可容許形成具有充分不同(例如,可區分)臨限電壓之裝置。在閘極電極114D、114S中包含功函數調諧元素至此等範圍外之濃度可不容許形成具有充分不同(例如,可區分)臨限電壓之裝置。
在圖17A及圖17B中,在開口122中形成一絕緣材料以形成隔離區128。隔離區128提供閘極電極114之間的隔離。絕緣材料可為氧化物(諸如氧化矽)、氮化物、類似物或其等之一組合,且可藉由一HDP-CVD、FCVD (例如,一遠端電漿系統中之一基於CVD之材料沉積及後固化以使其轉換為另一材料,諸如氧化物)、類似物或其等之一組合形成。可使用藉由任何可接受製程形成之其他絕緣材料。隔離區128之絕緣材料可相同於STI區56之絕緣材料,或可為一不同絕緣材料。在所繪示實施例中,絕緣材料係氮化矽。
在圖18A及圖18B中,將一第二ILD 132沉積於閘極間隔件82、CESL 90、第一ILD 92、閘極介電質112及閘極電極114上方。在一些實施例中,第二ILD 132係藉由一可流動CVD方法形成之一可流動膜。在一些實施例中,第二ILD 132由一介電材料形成,諸如PSG、BSG、BPSG、USG或類似物,且可藉由任何適合方法沉積,諸如CVD及PECVD。
在一些實施例中,在第二ILD 132與閘極間隔件82、CESL 90、第一ILD 92、閘極介電質112及閘極電極114之間形成一蝕刻停止層(ESL) 130。ESL 130可包含具有對蝕刻第二ILD 132之一高蝕刻選擇性之一介電材料,諸如氮化矽、氧化矽、氧氮化矽或類似物。
在圖19A及圖19B中,源極/汲極接點134及閘極接點136經形成以分別接觸磊晶源極/汲極區88及閘極電極114。用於源極/汲極接點134之開口經形成穿過CESL 90、第一ILD 92、ESL 130及第二ILD 132。用於閘極接點136之開口經形成穿過ESL 130及第二ILD 132。可使用可接受光微影及蝕刻技術形成開口。在開口中形成一襯層(未展示) (諸如一擴散阻障層、一黏附層或類似物)及一導電材料。襯層可包含鈦、氮化鈦、鉭、氮化鉭或類似物。導電材料可為銅、一銅合金、銀、金、鎢、鈷、鋁、鎳或類似物。可執行一平坦化製程(諸如一CMP)以從第二ILD 132之一表面移除過量材料。剩餘襯層及導電材料形成開口中之源極/汲極接點134及閘極接點136。可執行一退火製程以在磊晶源極/汲極區88與源極/汲極接點134之間的界面處形成矽化物。源極/汲極接點134實體且電耦合至磊晶源極/汲極區88,且閘極接點136實體且電耦合至閘極電極114。源極/汲極接點134及閘極接點136可在不同製程中形成,或可在相同製程中形成。儘管展示為以相同剖面形成,但應瞭解,源極/汲極接點134及閘極接點136之各者可以不同剖面形成,此可避免接點短路。
圖20A及圖20B係根據一些實施例之FinFET之剖面圖。展示由包含圖2至圖19B之步驟之一製程導致之裝置。圖20A及圖20B繪示類似於圖19A中之一區50R之區中之構件(以類似於圖10A至圖14B之一方式)。閘極電極114D具有空隙104D,該等空隙104D在頂部處由ESL 130及/或閘極接點136密封(且因此由其等定義),且該等空隙104D在側處由隔離區128之側壁密封(且因此由其等定義) (參見圖17A及圖17B)。功函數調諧元素104E位於空隙104D中,諸如在定義空隙104D之閘極電極114D之內表面處。功函數調諧元素104E可不位於定義空隙104D之ESL 130及/或閘極接點136之內表面處。此外,閘極電極114S可不具有空隙(或至少具有較小空隙)。由於閘極處理製程116、126,閘極電極114D具有大於閘極電極114S之一功函數調諧調諧元素濃度。因此,密緻區50D中之FinFET具有不同於密緻區50S中之FinFET之臨限電壓。例如,當FinFET係p型裝置時,密緻區50D中之FinFET具有小於密緻區50S中之FinFET之一臨限電壓。
圖21A至圖22B係根據一些其他實施例之形成替換閘極結構之中間階段之剖視圖。圖21A及圖21B展示類似於圖11A及圖11B之一處理步驟。圖22A及圖22B展示類似於圖13A及圖13B之一處理步驟。在此實施例中,在任何填充層104C沉積於凹槽94D之主要部分94DM
中之前,在填充層104C之沉積期間發生夾斷(參見圖21A及圖21B)。在其中形成多個功函數調諧層(例如,圖29B及圖29C之實施例)或其中使用非保形沉積製程之實施例中,可發生此夾斷。因此,空隙104D暴露填充層104C之表面及膠合層104B之表面。在此實施例中,控制閘極結構之高度,使得保留凹槽94D之頸部部分94DN
中之閘極電極層104之部分(參見圖21A)且閘極電極114D在平坦化之後仍包含一些填充層104C (參見圖22A及圖22B)。因此,閘極電極114S包含一保形填充層104C,且閘極電極114D包含凹槽94D之頸部部分94DN
中之填充層104C。在此等實施例中,空隙104D經形成具有瓶狀輪廓形狀。空隙104D之瓶狀輪廓形狀可具有在約5 nm至約80 nm之範圍內之一高度、具有在約2 nm至約8 nm之範圍內之一寬度之一主要部分及具有在約1 nm至約7 nm之範圍內之一寬度之一頸部部分。頸部部分之寬度可比主要部分之底部處之寬度小多達約88%。主要部分之最大寬度可比主要部分之底部處之寬度大多達約33%。在另一實施例中,控制閘極結構之高度,使得空隙104D被平坦化製程破壞。因此,閘極電極114S包含填充層104C,但閘極電極114D不包含一填充層。
圖23A及圖23B係根據一些其他實施例之FinFET之剖面圖。展示由包含圖21A至圖22B之步驟之一製程導致之裝置。圖23A及圖23B繪示類似於圖19A中之一區50R之區中之構件(以類似於圖10A至圖14B之一方式)。
圖24A至圖25B係根據一些其他實施例之形成替換閘極結構之中間階段之剖視圖。圖24A及圖24B展示類似於圖11A及圖11B之一處理步驟。圖25A及圖25B展示類似於圖13A及圖13B之一處理步驟。在此實施例中,在任何膠合層104B沉積於凹槽94D之主要部分94DM
中之前,在膠合層104B之沉積期間發生夾斷(參見圖24A及圖24B)。在其中形成多個功函數調諧層(例如,圖29B及圖29C之實施例)或其中使用非保形沉積製程之實施例中,可發生此夾斷。因此,空隙104D暴露膠合層104B之表面及功函數調諧層104A之表面。在此實施例中,控制閘極結構之高度,使得保留凹槽94D之頸部部分94DN
中之閘極電極層104之部分(參見圖24A)且閘極電極114D在平坦化之後仍包含一些膠合層104B (參見圖25A及圖25B)。因此,閘極電極114S包含一保形膠合層104B及一保形填充層104C,且閘極電極114D包含凹槽94D之頸部部分94DN
中之膠合層104B。閘極電極114D不包含一填充層。在此等實施例中,空隙104D經形成具有瓶狀輪廓形狀。空隙104D之瓶狀輪廓形狀可具有在約5 nm至約80 nm之範圍內之一高度、具有在約2 nm至約8 nm之範圍內之一寬度之一主要部分及具有在約1 nm至約7 nm之範圍內之一寬度之一頸部部分。頸部部分之寬度可比主要部分之底部處之寬度小多達約88%。主要部分之最大寬度可比主要部分之底部處之寬度大多達約33%。在另一實施例中,控制閘極結構之高度,使得空隙104D被平坦化製程破壞。因此,閘極電極114S包含膠合層104B及填充層104C,但閘極電極114D不包含一膠合層或一填充層。
圖26A及圖26B係根據一些其他實施例之FinFET之剖面圖。展示由包含圖24A至圖25B之步驟之一製程導致之裝置。圖26A及圖26B繪示類似於圖19A中之一區50R之區中之構件(以類似於圖10A至圖14B之一方式)。
圖27係展示閘極處理製程116、126之後的閘極電極114之組合物之一光譜圖。一第一組資料202展示在未使用閘極處理製程116、126的情況下形成之一閘極電極之一填充層之組合物。一第二組資料204展示使用閘極處理製程116、126形成之一閘極電極之一填充層之組合物。如展示,藉由閘極處理製程116、126,在閘極電極中量測之功函數調諧元素104E之數量顯著增加。
圖28係展示所得裝置之臨限電壓之一圖表。一第一組資料302展示在未使用閘極處理製程116、126的情況下形成之裝置之臨限電壓。一第二組資料304展示使用閘極處理製程116、126形成之裝置之臨限電壓。如可見,閘極處理製程116、126導致具有較短通道長度之裝置比具有較長通道長度之裝置經歷一更大臨限電壓增加。此增加係歸因於在具有較短通道長度之裝置之閘極電極中形成空隙。在一個實例中,具有較短通道長度之裝置經歷從約20 mV至約100 mV之臨限電壓增加。
所揭示FinFET實施例亦可應用於奈米結構裝置,諸如奈米結構(例如,奈米薄片、奈米線、環繞式閘極或類似物)場效電晶體(NSFET)。在一NSFET實施例中,由藉由圖案化通道層及犧牲層之交替層之一堆疊而形成之奈米結構替換鰭片。以類似於上文描述之實施例之一方式形成虛設閘極結構及源極/汲極區。在移除虛設閘極結構之後,可在通道區中部分或完全移除犧牲層。以類似於上文描述之實施例之一方式形成替換閘極結構,替換閘極結構可部分或完全填充藉由移除犧牲層而留下之開口,且替換閘極結構可部分或完全包圍NSFET裝置之通道區中之通道層。以類似於上文描述之實施例之一方式形成至替換閘極結構及源極/汲極區之ILD及接點。可形成一奈米結構裝置,如美國專利申請公開案第2016/0365414號中揭示,該案之全部內容以引用的方式併入本文中。
實施例可達成優點。在閘極電極114D中形成空隙104D容許閘極處理製程116、126藉由由空隙104D暴露之閘極電極114D之增加表面積之性質而對閘極電極114D之影響大於對閘極電極114S之影響。因此,閘極處理製程116、126可將比閘極電極114S更多之功函數調諧元素(例如,氟、氮、氧、氯、硼、矽等)併入至閘極電極114D中。因而,即使當在密緻區50D及稀疏區50S兩者中執行閘極處理製程116、126時,閘極處理製程116、126仍可用於選擇性地調諧裝置在密緻區50D中之臨限電壓。因此,經形成具有閘極電極114D之FinFET具有不同於經形成具有閘極電極114S之FinFET之臨限電壓。例如,當FinFET係p型裝置時,經形成具有閘極電極114D之FinFET可具有小於經形成具有閘極電極114S之FinFET之一臨限電壓。
在一實施例中,一種裝置包含:一閘極介電質,其在一基板上方;一閘極電極,其在該閘極介電質上方,該閘極電極包含:一功函數調諧層,其在該閘極介電質上方;一膠合層,其在該功函數調諧層上方;一填充層,其在該膠合層上方;及一空隙,其由該填充層、該膠合層及該功函數調諧層之至少一者之內表面定義,該等內表面處之該閘極電極之一材料包含一功函數調諧元素。在該裝置之一些實施例中,該等內表面係該填充層之該等內表面,且該功函數調諧層係該膠合層與該閘極介電質之間的唯一功函數調諧層。在該裝置之一些實施例中,該等內表面係該膠合層之該等內表面,且該功函數調諧層係該膠合層與該閘極介電質之間的複數個功函數調諧層之一者。在該裝置之一些實施例中,該等內表面係該功函數調諧層之該等內表面,且該功函數調諧層係該膠合層與該閘極介電質之間的複數個功函數調諧層之一者。在該裝置之一些實施例中,該功函數調諧元素係氟、氮、氧、氯、硼或矽。在該裝置之一些實施例中,該等內表面處之該閘極電極之該材料包含在1 at.%至28 at.%之範圍內之一濃度之該功函數調諧元素。在一些實施例中,該裝置進一步包含:該閘極電極上方之一接點,該空隙由該接點之一底表面進一步定義。在一些實施例中,該裝置進一步包含:鄰近於該閘極電極之一端部之一隔離區,該空隙由該隔離區之一側壁進一步定義。
在一實施例中,一種裝置包含:一第一電晶體,其包含:一第一通道區,該第一通道區具有一第一長度;及一第一閘極結構,其在該第一通道區上方,該第一閘極結構包含一第一閘極電極,該第一閘極電極具有在其中之一空隙;及一第二電晶體,其包含:一第二通道區,該第二通道區具有一第二長度,該第二長度大於該第一長度;及一第二閘極結構,其在該第二通道區上方,該第二閘極結構包含一第二閘極電極,該第二閘極電極不具有空隙,該第二閘極電極具有不同於該第一閘極電極之一功函數。在該裝置之一些實施例中,該第一閘極電極包含一金屬及一功函數調諧元素,且該第二閘極電極包含該金屬且不具有該功函數調諧元素。在該裝置之一些實施例中,該金屬係鎢且該功函數調諧元素係氟、氮、氧、氯、硼或矽。在一些實施例中,該裝置進一步包含:一第一閘極間隔件,其鄰近於該第一閘極結構,該第一閘極間隔件具有彎曲側壁;及一第二閘極間隔件,其鄰近於該第二閘極結構,該第二閘極間隔件具有筆直側壁。在一些實施例中,該裝置進一步包含:一第一閘極遮罩,其在該第一閘極結構上方;及一隔離區,其鄰近於該第一閘極結構之一端部,該空隙由該隔離區、該第一閘極遮罩及該第一閘極電極之表面定義。
在一實施例中,一種方法包含:移除一虛設閘極以在閘極間隔件之間形成一凹槽;將一閘極介電層沉積於該凹槽中;將閘極電極層沉積於該閘極介電層上,該等閘極電極層之內表面定義一空隙;平坦化該等閘極電極層之頂表面,直至在該等閘極電極層之該等頂表面處暴露該空隙;及在該空隙中執行一第一閘極處理製程,該第一閘極處理製程增加定義該空隙之該等閘極電極層之該等內表面處之一功函數調諧元素之一濃度。在該方法之一些實施例中,該凹槽具有主要部分及一頸部部分,該等閘極電極層完全填充該凹槽之該頸部部分,該等閘極電極層部分填充該凹槽之該主要部分以定義該空隙。在該方法之一些實施例中,該功函數調諧元素係氟且該第一閘極處理製程係一氟化處理製程。在該方法之一些實施例中,該功函數調諧元素係氮且該第一閘極處理製程係一氮化處理製程。在該方法之一些實施例中,該功函數調諧元素係氧且該第一閘極處理製程係一氧化處理製程。在該方法之一些實施例中,該功函數調諧元素係氯、硼或矽且該第一閘極處理製程係一沉積製程。在一些實施例中,該方法進一步包含:在該等閘極電極層中形成一開口,在形成該開口之後在該等閘極電極層之一側壁處暴露該空隙;及在該空隙中執行一第二閘極處理製程,該第二閘極處理製程增加定義該空隙之該等閘極電極層之該等內表面處之該功函數調諧元素之該濃度。
前文概述若干實施例之特徵,使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應瞭解,其等可容易地使用本揭露作為設計或修改用於實行本文中介紹之實施例之相同目的及/或達成相同優點之其他製程及結構之一基礎。熟習此項技術者亦應認知,此等等效構造不脫離本揭露之精神及範疇,且其等可在不脫離本揭露之精神及範疇的情況下在本文中進行各種改變、替換及更改。
50:基板
50D:密緻區
50N:n型區
50P:p型區
50R:區
50S:稀疏區
52:鰭片
56:淺溝槽隔離(STI)區
58:通道區
62:虛設介電層
64:虛設閘極層
66:遮罩層
72:虛設介電質
74:虛設閘極
76:遮罩
82:閘極間隔件
84:鰭片間隔件
86:輕摻雜汲極/汲極(LDD)區
88:源極/汲極區
90:接觸蝕刻停止層(CESL)
92:層間介電質(ILD)
94:凹槽
94D:凹槽
94DM
:主要部分
94DN
:頸部部分
94S:凹槽
102:閘極介電層
102A:界面層
102B:上覆高介電係數材料
104:閘極電極層
104A:功函數調諧層
104A1
:第一調諧層
104A2
:第二調諧層
104A3
:第三調諧層
104B:膠合層
104C:填充層
104D:空隙
104E:功函數調諧元素
106:閘極處理製程
112:閘極介電質
114:閘極電極
114D:閘極電極
114S:閘極電極
116:閘極處理製程
122:開口
126:閘極處理製程
128:隔離區
130:蝕刻停止層(ESL)
132:第二層間介電質(ILD)
134:源極/汲極接點
136:閘極接點
202:第一組資料
204:第二組資料
302:第一組資料
304:第二組資料
D1
:方向
W1
:第一寬度
W2
:第二寬度
W3
:第三寬度
當結合隨附圖式閱讀時自下列實施方式更好理解本揭露之態樣。應注意,根據行業中之標準實踐,各種構件不按比例繪製。事實上,為清晰論述,各種構件之尺寸可任意增大或減小。
圖1繪示一三維視圖中之一FinFET之一實例。
圖2至圖19B係根據一些實施例之製造FinFET之中間階段之各種視圖。
圖20A及圖20B係根據一些實施例之FinFET之剖面圖。
圖21A至圖22B係根據一些其他實施例之製造FinFET之中間階段之剖視圖。
圖23A及圖23B係根據一些其他實施例之FinFET之剖面圖。
圖24A至圖25B係根據一些其他實施例之製造FinFET之中間階段之剖視圖。
圖26A及圖26B係根據一些其他實施例之FinFET之剖面圖。
圖27係展示根據一些實施例之閘極電極之組合物之一光譜圖。
圖28係展示根據一些實施例之裝置之臨限電壓之一圖表。
圖29A至圖29C係根據一些實施例之閘極結構膜堆疊之剖面圖。
50:基板
52:鰭片
56:淺溝槽隔離(STI)區
82:閘極間隔件
88:源極/汲極區
92:層間介電質(ILD)
112:閘極介電質
114:閘極電極
Claims (10)
- 一種半導體裝置,其包括:一閘極介電質,其在一基板上方;一閘極電極,其在該閘極介電質上方,該閘極電極包括:一功函數調諧層,其在該閘極介電質上方;一膠合層,其在該功函數調諧層上方;一填充層,其在該膠合層上方;及一空隙,其由該填充層、該膠合層及該功函數調諧層之至少一者之內表面定義,用於定義該空隙之該等內表面處之該閘極電極之一材料包含一功函數調諧元素。
- 如請求項1之裝置,其中該等內表面係該填充層之該等內表面,且其中該功函數調諧層係該膠合層與該閘極介電質之間的唯一功函數調諧層。
- 如請求項1之裝置,其中該等內表面係該膠合層之該等內表面,且其中該功函數調諧層係該膠合層與該閘極介電質之間的複數個功函數調諧層之一者。
- 如請求項1之裝置,其中該等內表面係該功函數調諧層之該等內表面,且其中該功函數調諧層係該膠合層與該閘極介電質之間的複數個功函數調諧層之一者。
- 一種半導體裝置,其包括:一第一電晶體,其包括:一第一通道區,該第一通道區具有一第一長度;及一第一閘極結構,其在該第一通道區上方,該第一閘極結構包括一第一閘極電極,該第一閘極電極具有在其中之一空隙;及一第二電晶體,其包括:一第二通道區,該第二通道區具有一第二長度,該第二長度大於該第一長度;及一第二閘極結構,其在該第二通道區上方,該第二閘極結構包括一第二閘極電極,該第二閘極電極不具有空隙,該第二閘極電極具有不同於該第一閘極電極之一功函數。
- 如請求項5之裝置,其進一步包括:一第一閘極間隔件,其鄰近於該第一閘極結構,該第一閘極間隔件具有彎曲側壁;及一第二閘極間隔件,其鄰近於該第二閘極結構,該第二閘極間隔件具有筆直側壁。
- 如請求項5之裝置,其進一步包括:一第一閘極遮罩,其在該第一閘極結構上方;及一隔離區,其鄰近於該第一閘極結構之一端部,該空隙由該隔離區、該第一閘極遮罩及該第一閘極電極之表面定義。
- 一種半導體製造方法,其包括:移除一虛設閘極以在閘極間隔件之間形成一凹槽;將一閘極介電層沉積於該凹槽中;將閘極電極層沉積於該閘極介電層上,該等閘極電極層之內表面定義一空隙;平坦化該等閘極電極層之頂表面,直至在該等閘極電極層之該等頂表面處暴露該空隙;及在該空隙中執行一第一閘極處理製程,該第一閘極處理製程增加定義該空隙之該等閘極電極層之該等內表面處之一功函數調諧元素之一濃度。
- 如請求項8之方法,其中該凹槽具有主要部分及一頸部部分,該等閘極電極層完全填充該凹槽之該頸部部分,該等閘極電極層部分填充該凹槽之該主要部分以定義該空隙。
- 如請求項8之方法,其進一步包括:在該等閘極電極層中形成一開口,在形成該開口之後在該等閘極電極層之一側壁處暴露該空隙;及在該空隙中執行一第二閘極處理製程,該第二閘極處理製程增加定義該空隙之該等閘極電極層之該等內表面處之該功函數調諧元素之該濃度。
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