CN109273373A - 电连接电容插塞的硅化钴层的制作方法 - Google Patents

电连接电容插塞的硅化钴层的制作方法 Download PDF

Info

Publication number
CN109273373A
CN109273373A CN201710584713.0A CN201710584713A CN109273373A CN 109273373 A CN109273373 A CN 109273373A CN 201710584713 A CN201710584713 A CN 201710584713A CN 109273373 A CN109273373 A CN 109273373A
Authority
CN
China
Prior art keywords
substrate
cobalt
silicon
manufacture craft
silicon cobalt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710584713.0A
Other languages
English (en)
Inventor
吴佳臻
陈意维
许启茂
张凯钧
蔡志杰
陈品宏
郑存闵
黄怡安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
Original Assignee
Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujian Jinhua Integrated Circuit Co Ltd, United Microelectronics Corp filed Critical Fujian Jinhua Integrated Circuit Co Ltd
Priority to CN201710584713.0A priority Critical patent/CN109273373A/zh
Priority to US15/990,837 priority patent/US10707214B2/en
Publication of CN109273373A publication Critical patent/CN109273373A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/0682—Silicides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58—After-treatment
    • C23C14/5806—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Abstract

本发明公开一种电连接电容插塞的硅化钴层的制作方法。其硅化钴层的制作方法，包含提供一基底放置于一腔室中，然后进行一沉积制作工艺，在基底温度介于50℃至100℃之间以及腔室温度介于300℃至350℃之间时，形成一钴材料层覆盖基底，然后在沉积制作工艺之后，进行一退火制作工艺，在基底维持于300℃至350℃之间时，进行退火制作工艺50秒至60秒之间，使得钴材料层反应成为一硅化钴层。

Description

电连接电容插塞的硅化钴层的制作方法
技术领域
本发明涉及一种硅化钴的制作方法，特别是涉及电连接电容插塞的硅化钴层。
背景技术
随着半导体元件集成度的增加，元件中的图案与线宽也逐渐缩小，因而导致元件中的接触电阻增高，进而影响元件操作速度。由于金属硅化物的电阻较多晶硅(Polysilicon)低，并且其热稳定性也比一般内连线材料高，因此在形成进阶半导体装置过程中，将存在于栅极、源极及漏极结构中的部分硅转变成低电阻率金属硅化物。此转变一方面实现具有低体积电阻率的导电路径，且另一方面确保良好接触电阻。
值得注意的是，一般金属硅化物层的制作需要两次热处理制作工艺，然而在完成第二次热处理制作工艺之后，形成于基底表面的金属硅化物层却存在有轮廓不均匀的问题，严重影响金属硅化物层的品质。因此，如何改善金属硅化物层的品质实为相关技术者所欲改进的课题。
发明内容
根据本发明的一优选实施例，一种硅化钴层的制作方法，包含以下步骤：首先，提供一基底放置于一腔室中，基底可以是已经完成晶体管制作，将要形成金属硅化物于源极/漏极掺杂区上的基底，然后进行一沉积制作工艺，在基底温度介于50℃至100℃之间以及腔室温度介于300℃至350℃之间时，形成一钴材料层覆盖基底，然后在沉积制作工艺之后，进行一退火制作工艺，在基底维持于300℃至350℃之间时，进行退火制作工艺50秒至60秒之间，使得钴材料层反应成为一硅化钴层，此硅化钴层即作为源极/漏极掺杂区上的金属硅化物，接续进行一快速加热制作工艺，快速加热制作工艺的操作温度介于600℃至650℃之间，操作时间介于30秒至60秒之间，快速加热制作工艺可以让硅化钴层的分布更加均匀，最后将未反应成硅化钴层的钴材料层完全移除。
附图说明
图1为本发明的一优选实施例所绘示的动态随机存取存储器的示意图；
图2至图5为本发明的一优选实施例所绘示的一种电容插塞上的硅化钴层的制作方法的示意图。
主要元件符号说明
10 基底 12 存储单元
14 晶体管 16 电容结构
18 埋藏式栅极 20 源极/漏极掺杂区
22 硅化钴 24 导电插塞
26 缓冲层 30 介电层
50 腔室 52 晶片载台
54 钴靶材 56 氩气
58 钴材料层 60 氢化氩
具体实施方式
图1为根据本发明的一优选实施例所绘示的动态随机存取存储器(DynamicRandom Access Memory,DRAM)，其中动态随机存取存储器中的硅化钴层，是采用本发明的硅化钴层的制作方法所制成。如图1所示，提供一基底10，多个动态随机存取存储器的存储单元12设置于基底10上，各个存储单元12包含有一晶体管14和一电容结构16。在图1中以多个存储单元12为例，各个晶体管14包含埋藏式栅极18以及源极/漏极掺杂区20，埋藏式栅极18设置于基底10中，而源极/漏极掺杂区20则位于埋藏式栅极18的两侧，源极/漏极掺杂区20可以为一外延层或是直接注入于基底10中的掺杂区(图未示)，外延层可以例如为一磷化硅(SiP)、硅锗(SiGe)、锗(Ge)等外延材料。各个源极/漏极掺杂区20上各自设有一金属硅化物层，在本实施例中所采用的金属硅化物层为一硅化钴(cobalt silicide)层22，在硅化钴层22上设置有一导电插塞24电连接电容结构16，导电插塞24和硅化钴层20之间可选择性设置有一缓冲层26。导电插塞24可以为钨，缓冲层26可以包含钛和氮化钛。在各个导电插塞24之间设置有介电层30。
图2至图5为根据本发明的一优选实施例所绘示的一种硅化钴层的制作方法，其中具有相同功能或特征的元件将使用如图1中相同的元件符号。本发明的硅化钴层的制作方法适用于制作图1中的硅化钴层22，以下将叙述硅化钴层22的制作方式，如图1和图2所示，提供一腔室50，腔室50中具有一晶片载台52用于承载基底10，一钴靶材54固定在腔室50的内壁面，基底10可以是已经完成如图1中晶体管14的制作工艺，目前正要进行形成硅化钴层22于源极/漏极掺杂区20上的阶段，首先将氩气56通入腔室50，氩气56在后续将会解离成为等离子体中的离子，用于轰击钴靶材54，然后加热腔室50至300℃至350℃之间。如图1和图3所示，进行一沉积制作工艺，启动等离子体，并且在钴靶材54和晶片载台52加上电压，使得钴靶材54形成阴极而晶片载台52形成阳极，然后利用等离子体在基底10表面沉积一层钴材料层58，在形成钴材料层58时，腔室50内的温度介于300℃至350℃之间，值得注意的是：由于加热腔室50至300℃至350℃的时间跟沉积制作工艺之间的时间间隔很短，在基底10的温度尚未升高至和腔室50同温前，就进行沉积制作工艺，因此沉积制作工艺时基底10的温度维持在50℃至100℃之间，在基底10上的元件例如源极/漏极掺杂区20的温度也和基底10的温度相同，所以钴材料层58在基底10上不会因为温度过高而反应成为硅化钴层，也就是说，在沉积制作工艺中所形成的材料层完全是钴材料层，不含有硅化钴层。
如图1和图4所示，进行一退火制作工艺，通过通入氢化氩60加热基底10至300℃至350℃之间，此退火制作工艺维持50秒至60秒之间，退火制作工艺时，腔室50的温度介于300℃至350℃之间，使得钴材料层58和源极/漏极掺杂区20反应成为硅化钴层22，在本实施例中，钴材料层58未完全反应成硅化钴，尚有一些钴材料层58余留在硅化钴层22的表面。如图1和图5所示，进行一快速加热制作工艺，快速加热制作工艺的操作温度介于600℃至650℃之间，快速加热制作工艺时基底10和腔室50的温度都是介于600℃至650℃之间，操作时间介于30秒至60秒之间，快速加热制作工艺可以让硅化钴层22的分布更加均匀。之后，移除剩余的钴材料层58。至此硅化钴层22业已完成，后续可接续形成缓冲层26和导电插塞24与硅化钴层22电连接。虽然上述实施例制作位于源极/漏极掺杂区20上的硅化钴层22，但本发明的方式也可以用于制作其它位置的硅化钴层，例如栅极上的硅化钴层或是其它需要降低片电阻的位置。
一般而言，在基底的温度在高温时沉积钴材料层，在沉积的同时钴材料层会和其所接触的含硅材料反应成为硅化钴层，但如此反应而成的硅化钴层表面较粗糙，粗糙表面会造成后续形成的导电插塞和硅化钴层之间的片电阻增加，因此本发明特意在沉积制作工艺时将基底的温度维持在50℃至100℃之间，确保沉积时钴材料层不会反应成为硅化钴层，在沉积完成后才利用退火制作工艺加温让钴材料层反应成硅化钴层，如此所制作出来的硅化钴层会具有平坦的表面。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (7)

1.一种电连接电容插塞的硅化钴层的制作方法，包含：
提供一基底放置于一腔室中；
进行一沉积制作工艺，在该基底温度介于50℃至100℃之间以及该腔室温度介于300℃至350℃之间时，形成一钴材料层覆盖该基底；以及
在该沉积制作工艺之后，进行一退火制作工艺，在该基底维持于300℃至350℃之间时，进行该退火制作工艺50秒至60秒之间，使得该钴材料层反应成为一硅化钴层。
2.如权利要求1所述的电连接电容插塞的硅化钴层的制作方法，另包含：在形成该硅化钴层后，进行一快速加热制作工艺，该快速加热制作工艺的操作温度介于600℃至650℃之间，操作时间介于30秒至60秒之间。
3.如权利要求3所述的电连接电容插塞的硅化钴层的制作方法，另包含在该快速加热制作工艺之后，移除未反应的该钴材料层。
4.如权利要求1所述的电连接电容插塞的硅化钴层的制作方法，其中在该退火制作工艺时，只有部分的该钴材料层反应为该硅化钴层。
5.如权利要求1所述的电连接电容插塞的硅化钴层的制作方法，其中在该沉积制作工艺时，该钴材料层未反应为硅化钴。
6.如权利要求1所述的电连接电容插塞的硅化钴层的制作方法，另包含在该硅化钴层完成后，形成一电容插塞和该硅化钴层电连接。
7.如权利要求1所述的电连接电容插塞的硅化钴层的制作方法，其中该基底上设置有一晶体管和一电容结构，该晶体管包含一埋藏式栅极以及一源极/漏极掺杂区，该硅化钴层和该源极/漏极掺杂区接触，一导电插塞电连接该电容结构和该硅化钴层。
CN201710584713.0A 2017-07-18 2017-07-18 电连接电容插塞的硅化钴层的制作方法 Pending CN109273373A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201710584713.0A CN109273373A (zh) 2017-07-18 2017-07-18 电连接电容插塞的硅化钴层的制作方法
US15/990,837 US10707214B2 (en) 2017-07-18 2018-05-29 Fabricating method of cobalt silicide layer coupled to contact plug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710584713.0A CN109273373A (zh) 2017-07-18 2017-07-18 电连接电容插塞的硅化钴层的制作方法

Publications (1)

Publication Number Publication Date
CN109273373A true CN109273373A (zh) 2019-01-25

Family

ID=65023428

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710584713.0A Pending CN109273373A (zh) 2017-07-18 2017-07-18 电连接电容插塞的硅化钴层的制作方法

Country Status (2)

Country Link
US (1) US10707214B2 (zh)
CN (1) CN109273373A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11222818B2 (en) * 2018-07-13 2022-01-11 Taiwan Semiconductor Manufacturing Co., Ltd. Formation method of semiconductor device structure with metal-semiconductor compound region

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050092598A1 (en) * 2003-11-05 2005-05-05 Industrial Technology Research Institute Sputtering process with temperature control for salicide application
US20070178696A1 (en) * 2006-01-30 2007-08-02 Chii-Ming Wu Method for silicide formation on semiconductor devices
CN101211781A (zh) * 2006-12-28 2008-07-02 中芯国际集成电路制造(上海)有限公司 自对准金属硅化物的制造方法
CN105374688A (zh) * 2014-08-21 2016-03-02 台湾积体电路制造股份有限公司 嵌入式晶体管

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100278665B1 (ko) 1998-06-08 2001-01-15 윤종용 디램 및 로직 혼합소자에서 화학기계적 연마에 의한 자기정렬 방식의 선택적 실리사이드층 형성방법
US6184132B1 (en) * 1999-08-03 2001-02-06 International Business Machines Corporation Integrated cobalt silicide process for semiconductor devices
US6306698B1 (en) * 2000-04-25 2001-10-23 Advanced Micro Devices, Inc. Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same
US20080268635A1 (en) * 2001-07-25 2008-10-30 Sang-Ho Yu Process for forming cobalt and cobalt silicide materials in copper contact applications
KR100485386B1 (ko) * 2003-04-08 2005-04-27 삼성전자주식회사 금속막 증착용 조성물 및 이를 이용한 금속막 형성 방법
TW200746268A (en) * 2006-04-11 2007-12-16 Applied Materials Inc Process for forming cobalt-containing materials
KR101728135B1 (ko) 2010-06-11 2017-04-18 삼성전자 주식회사 반도체 소자의 제조방법
US8871600B2 (en) * 2011-11-11 2014-10-28 International Business Machines Corporation Schottky barrier diodes with a guard ring formed by selective epitaxy
DE102011118638B4 (de) * 2011-11-15 2021-12-30 Zahoransky Ag Spannkluppe
JP2013219202A (ja) * 2012-04-09 2013-10-24 Elpida Memory Inc 半導体装置、その設計方法及び製造方法
US9869024B2 (en) * 2014-07-17 2018-01-16 Applied Materials, Inc. Methods and apparatus for depositing a cobalt layer using a carousel batch deposition reactor
US10043709B2 (en) * 2014-11-07 2018-08-07 Applied Materials, Inc. Methods for thermally forming a selective cobalt layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050092598A1 (en) * 2003-11-05 2005-05-05 Industrial Technology Research Institute Sputtering process with temperature control for salicide application
US20070178696A1 (en) * 2006-01-30 2007-08-02 Chii-Ming Wu Method for silicide formation on semiconductor devices
CN101211781A (zh) * 2006-12-28 2008-07-02 中芯国际集成电路制造(上海)有限公司 自对准金属硅化物的制造方法
CN105374688A (zh) * 2014-08-21 2016-03-02 台湾积体电路制造股份有限公司 嵌入式晶体管

Also Published As

Publication number Publication date
US10707214B2 (en) 2020-07-07
US20190027479A1 (en) 2019-01-24

Similar Documents

Publication Publication Date Title
US11444028B2 (en) Contact structure and formation thereof
CN100547739C (zh) 半导体晶片的热处理方法
KR20050009761A (ko) 반도체 공정에 대하여 실리사이드 접촉부들을 이용하는 방법
CN100481348C (zh) 盐化物处理过程以及制造半导体器件的方法
JP2005167249A (ja) 熱的安定性に優れるシリサイド膜の形成方法、その方法で形成されたシリサイド膜を備える半導体素子と半導体メモリ素子およびそれらの素子の製造方法
TW466707B (en) Formation method of collar silicon oxide
CN1937181B (zh) 具有镍硅化物的半导体元件与制作镍硅化物的方法
CN109273373A (zh) 电连接电容插塞的硅化钴层的制作方法
US20090079010A1 (en) Nickel silicide formation for semiconductor components
CN101443901B (zh) 带有多晶硅晶粒的硅化物源极/漏极电极
JP2009513822A (ja) Ｆｅｔデバイスにおいて低欠陥密度のニッケルシリサイドを形成するための方法及び装置
CN107068771B (zh) 低温多晶硅薄膜晶体管及其制造方法
JP2004193447A (ja) 半導体集積回路装置の製造方法
CN103021865A (zh) 金属硅化物薄膜和超浅结的制作方法及半导体器件
CN103915326B (zh) 自对准金属硅化物的形成方法和半导体器件
CN109637976B (zh) 3d nand闪存的制作方法和连接结构
US20150311090A1 (en) Method of manufacturing a semiconductor device
CN108428628B (zh) 一种可降低功率mos器件栅极电阻的制造方法
KR100587609B1 (ko) 반도체 소자의 트랜지스터 제조방법
JP4102709B2 (ja) 半導体装置の製造方法
CN103377894A (zh) 金属硅化物制造方法
KR20070090620A (ko) 반도체 캐패시터의 스토리지 노드 형성방법
KR20020050422A (ko) 반도체 소자의 캐패시터 및 그의 제조 방법
KR100443517B1 (ko) 반도체 소자의 비트라인 형성방법
US9385005B2 (en) Semiconductor device and method of making

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20190125