CN101443901B - 带有多晶硅晶粒的硅化物源极/漏极电极 - Google Patents
带有多晶硅晶粒的硅化物源极/漏极电极 Download PDFInfo
- Publication number
- CN101443901B CN101443901B CN2005800464679A CN200580046467A CN101443901B CN 101443901 B CN101443901 B CN 101443901B CN 2005800464679 A CN2005800464679 A CN 2005800464679A CN 200580046467 A CN200580046467 A CN 200580046467A CN 101443901 B CN101443901 B CN 101443901B
- Authority
- CN
- China
- Prior art keywords
- source
- polysilicon
- silicon layer
- drain
- drain regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 54
- 229910021332 silicide Inorganic materials 0.000 title claims description 41
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052710 silicon Inorganic materials 0.000 claims description 34
- 239000010703 silicon Substances 0.000 claims description 33
- 150000003624 transition metals Chemical class 0.000 claims description 17
- 239000002019 doping agent Substances 0.000 claims description 13
- 229910052723 transition metal Inorganic materials 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000008859 change Effects 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 125000004429 atom Chemical group 0.000 description 18
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 238000000151 deposition Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000009466 transformation Effects 0.000 description 6
- 229910017052 cobalt Inorganic materials 0.000 description 5
- 239000010941 cobalt Substances 0.000 description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 206010010144 Completed suicide Diseases 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 125000001309 chloro group Chemical group Cl* 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910021350 transition metal silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明提供一种半导体器件,其包括用于晶体管(105)的源极/漏极电极(100)。源极/漏极电极(100)包含位于源极/漏极区(115)上方的多个多晶硅晶粒(110)。金属硅化物层(120)共形地涂覆所述多个多晶硅晶粒。本发明还阐述一种制作所述器件的方法。
Description
技术领域
本发明涉及半导体器件,且更具体而言,涉及一种源极或漏极(下文中称为“源极/漏极电极”)及其制作方法。
背景技术
对增大的计算机和存储器空间的持续需求正促使集成电路及其组件部件的微型化。例如,金属氧化物半导体(MOS)关键尺寸的不断按比例缩小已将源极/漏极电极的长度和宽度尺寸缩小到纳米范围。由该按比例缩小引起人们关心的一个问题是,通过自对准硅化物工艺所形成的较小尺寸源极/漏极电极的增大的薄膜电阻将减小给定栅漏电容的MOS晶体管的驱动电流。(“硅化”是用于自对准硅化工艺的术语,其中硅化物接触仅在沉积金属与硅直接接触的那些区域中形成。从硅化中得到的硅化物材料有时称为“硅化物”)。
先前当MOS晶体管的关键尺寸按比例减小时用于将驱动电流维持在可接受范围内的努力一直着重于改变源极/漏极电极中使用的金属。具体而言,随着技术节点的每一减小,已使用了电阻率更低的金属。因而,金属硅化物源极/漏极电极已从硅化钛转变到硅化钴,且目前已转变到硅化镍。然而,转变到不同的金属硅化物不会发生任何问题。由于在小于约90纳米的器件特征尺寸上观察到的众所周知的颈缩现象,硅化钴会承受电阻率降低。硅化镍尽管具有小于硅化钛或硅化钴的电阻率,但也会遭受热不稳定性并形成掺料缺陷,所述掺料缺陷扩展到晶体管的沟道区域,导致短路及泄漏电流增大。
相应地,所属领域所需的是一种与现有金属硅化物源极/漏极电极制作方案相兼容的增大半导体器件中的驱动电流的方法,所述方法可克服上述问题,且具体而言减小约90纳米或更小的技术节点处的源极/漏极电极电阻率。
发明内容
为解决现有技术的上述缺陷,本发明提供用于晶体管的源极/漏极电极。所述源极/漏极电极具有位于源极/漏极区上方的多个多晶硅晶粒。金属硅化物层共形地涂覆(conformally coating)所述多个多晶硅晶粒。
在另一实施例中,本发明提供一种制造用于半导体器件的源极/漏极电极的方法。所述方法包括在源极/漏极区上形成硅层,及在所述硅层上沉积种子原子。将所述种子原子和硅层转变为在所述源极/漏极区上方形成多个多晶硅晶粒。
本发明的再一实施例提供一种集成电路。所述集成电路包括:半导体器件,其具有源极/漏极电极,所述源极/漏极电极包括位于源极/漏极区上方的多个多晶硅晶粒;和金属硅化物层,其共形地涂覆所述多个多晶硅晶粒。所述集成电路进一步包括位于所述半导体器件上方的多个绝缘层中的一者上的互连金属线。所述互连金属线将半导体器件的各源极/漏极电极互连以形成可工作的器件。
前文中已概述了本发明的优选和替代的特征,以使所属领域的普通技术人员可更好地理解下文中对本发明的详细说明。下文中将说明本发明的额外的特征,其构成本发明的权利要求项。所属领域的技术人员应了解,其易于使用所揭示的概念和具体实施例作为设计和修改用于实现本发明的相同目的的其他结构的依据。所属领域的技术人员还应认识到,这些类似的结构不背离本发明的范围。
附图说明
参照附图来说明本发明的各实施例,所述附图中:
图1图解说明用于根据本发明的教示的晶体管的源极/漏极电极的一实例的剖面图;
图2至图7图解说明在根据本发明的原理用于制造半导体器件的源极/漏极电极的一实例方法中所选步骤的剖面图;及
图8提供本发明的一实例性集成电路的剖面图。
具体实施方式
本发明认识到在源极/漏极电极中使用多晶硅晶粒来增大其有效表面积却不增大所述极的周长这一优点。本发明的源极/漏极电极包括共形地涂覆于源极/漏极区表面的上方或上面的多个多晶硅晶粒的金属硅化物层。因为所述源极/漏极电极的金属硅化物层的有效表面积增加,所以所述源极/漏极电极具有较低的薄膜电阻。因此,与具有常规的源极/漏极电极的晶体管相比,具有这些源极/漏极电极的晶体管具有较高的驱动电流。
根据本发明的原理,制作具有高等值面的电极最为理想,因为这可增大源极/漏极电极内金属硅化物层的有效表面积。这与源极/漏极电极制作中的常规设计原理相反,所述常规设计原理致力于生产大体上为平面的金属硅化物层。定制常规的源极/漏极电极制作工艺,以避免将金属硅化物层弄得粗糙,因为被弄得粗糙的表面可在金属互连与金属硅化物层之间的接口处具有不可接受的高接触电阻。
作为本发明的一部分,认识到可将源极/漏极电极的表面表征为具有微观粗糙度和宏观粗糙度两者。为了本发明的目的,将微观粗糙度界定为所述表面的高度波动的RMS(均方根)小于约1纳米,而宏观粗糙度的RMS为1纳米或更大。另外,将微观粗糙度制作为半导体器件制造中各个步骤(例如,等离子体工艺、清洁步骤及蚀刻程序)的人为产物。相反,在本发明中,通过形成多晶硅晶粒来故意产生宏观粗糙度,所述多晶硅晶粒的尺寸足够大而不会增加金属硅化物表面的微观粗糙度。本发明第一次认识到,通过减小微观粗糙度来减小接触电阻,而同时通过提供特定的宏观粗糙度来增大电极的有效表面积以减小薄膜电阻是可取的。
图1中显示本发明的一个实施例,其图解说明晶体管105的一源极/漏极电极100的实例的剖面图。多个多晶硅晶粒110定位在源极/漏极区115的上方,且金属硅化物层120共形地涂覆多个多晶硅晶粒110。
所属领域的技术人员应了解如何使用n型或p型掺杂剂来掺杂半导体衬底125的一部分,随后对其进行激活退火以形成源极/漏极区115。所属领域的技术人员还熟知,为所关心的技术节点调节源极/漏极区115的尺寸。在某些情况下,源极/漏极区115的长度130作为栅极140的长度135的函数按比例调节。在某些设计中,源漏极区115的长度130是栅极长度135的1倍到2倍。例如,对于约65纳米的栅极长度135,在某些实施例中,源极/漏极区115具有约110纳米的长度130。
在某些优选实施例中,晶体管105是MOS晶体管,例如nMOS晶体管或pMOS晶体管。晶体管105可具有任何数量的普通晶体管元件,包括绝缘结构145(例如浅沟槽隔离或场氧化物结构)、栅极侧壁150和掺杂阱152。
用于形成多晶硅晶粒110的工艺导致大体上成球形的晶粒,且因此将其称为球形多晶硅晶粒(HSG)。例如,在某些优选实施例中,HSG 110具有至少约2纳米的平均直径155。在这些实施例中,所述表面粗糙度将大于约1纳米,且更优选地大于约2纳米。在其他优选实施例中,HSG 110具有约10纳米和约30纳米之间的平均直径155。
如下情况是理想的:源极/漏极区115上的HSG 110的密度足够大以增大区115的有效表面积,但所述密度不足以使涂覆各个HSG 110的金属硅化物层120彼此接触。例如,考虑具有约90纳米的长度130和对应于来自图1中所示的剖面图页面的尺寸的宽度—等于约150纳米。据估计,675个具有约10纳米的平均直径155的HSG可形成于源极/漏极区115上—相当于密度为每22平方纳米面积的区上约1个HSG(例如,(150nm×90nm)/675个HSG)。对于该配置,据进一步估计,源极/漏极区115的有效表面积约为16200nm2,比由区115的尺寸所界定的面积(例如,150nm×90nm=13500nm2)相比增大约20%。据预测,具有该配置的源极/漏极电极100的经减小的薄膜电阻使晶体管105的驱动电流增大至少约4%至约7%。
源极/漏极区115上HSG 110的宽范围的密度是在本发明的范围内。作为非限制性实例,对于具有宽度约180纳米和长度130约200纳米的源极/漏极区115,可在所述源极/漏极区上以每4nm2 1个HSG的密度形成具有约2纳米的平均直径155的HSG110,且相当于区115上约9000个HSG。作为另一实例,对于具有宽度约65纳米和长度130约100纳米的源极/漏极区115,可在所述源极/漏极区115上以每1625nm2约1个HSG的密度形成具有约40纳米的平均直径的HSG,且相当于区115上约4个HSG155。
如下文中进一步解释,多晶硅晶粒110的本体由来自硅层165的原子构成,且更优选由非晶硅层的原子构成。在某些情况下,硅层165不一定完全通过形成多晶硅晶粒110而被消耗,且因此硅层165的各部分保持在如图1所示的源极/漏极电极100的最终结构。可通过调节硅层165的厚度170来控制多晶硅晶粒110的尺寸。例如,多晶硅晶粒110可具有等于硅层165的厚度170约0.6至约0.9倍的平均直径155。
也可通过在多晶硅晶粒110内包含掺杂剂(例如n型或p型掺杂剂)来调节多晶硅晶粒110的尺寸。在形成多晶硅晶粒110期间,掺杂到源极/漏极区115内的掺杂剂可扩散进入硅层165,且可将那些掺杂剂原子掺入多晶硅晶粒110内。或者,可将在形成硅层165时所包含的掺杂剂掺入多晶硅晶粒110内。在某些实例中,例如砷或磷等n型掺杂剂促进较大多晶硅晶粒110的形成。在其他实例中,p型掺杂剂(例如硼)的存在促进较小多晶硅晶粒110的形成。另外,可有利地使用掺杂剂来掺杂硅层165和多晶硅晶粒110以提高其导电性。
在源极/漏极电极100的某些有利的实施例中,金属硅化物层120包括过渡金属。在某些优选实施例中,金属硅化物层120包括硅化镍。然而,在其他实施例中,所述金属硅化物层包括硅化钴或硅化钨。源极/漏极电极100的某些实施例进一步包括金属硅化物层120上方的金属层175。在某些情况下,金属层175包括与金属硅化物层120中相同的金属,而在其他情况下金属层175包括不同的金属。
本发明的另一方面是制造源极/漏极电极的方法。图2至图7图解说明在根据本发明的原理制造用于半导体器件205的源极/漏极电极200的一实例方法中所选步骤的剖面图。所述方法可包括上文中所述及图1中所示的源极/漏极电极的任何实施例。
首先转到图2,其中图解说明在利用常规方法形成各器件组件后的半导体装置205—其在本文中实施为MOS晶体管。半导体装置205包括半导体衬底210、隔离结构215、栅极220、侧壁隔片225、掺杂阱227和源极/漏极区230。当然,半导体器件205可包括使用所属领域的技术人员所熟悉的常规工艺制作的各种其他器件组件。
现在转到图3,其中显示在源极/漏极区230的上方形成硅层300后部分构造的源极/漏极电极200。优选地,硅层300是非晶硅层。可通过化学气相沉积(CVD)或原子层沉积(ALD)来沉积硅原子而形成硅层300。在某些情况下,优选使用CVD,因为在现有半导体制作工厂内易于获得CVD工具。
将硅层300选择性地仅沉积到源极/漏极区上是有利的。选择性沉积可省去对额外的屏蔽步骤的需求,以避免在侧壁隔片225和隔离结构215或其他器件组件上不期望的硅沉积。在某些情况下,通过在低温下及在超高真空(UHV)条件下实施CVD工艺来促进选择性的沉积。例如,优选使用低于约600℃、且更优选低于约500℃的温度。实例性UHV条件包括小于约1×10-6Torr的CVD腔压力。或者,如果在沉积腔内包括含氯物质(例如盐酸),则可在低压(LP)CVD条件下(例如腔压力介于约1×10-3Torr与约1×10-6Torr之间)进行选择性沉积。如上所述,在硅层300的沉积中可包含n型和p型掺杂剂。
现在参见图4,其中绘示在硅层300上沉积种子原子400后部分构建的源极/漏极电极200。种子原子400的优选实施例包括硅、锗或硅锗。然而,种子原子可包括促进多晶硅晶粒形成的任何原子。优选地通过CVD来沉积种子原子400。在某些情况下,使用同一CVD工具来沉积硅层300和种子原子400。所属领域的技术人员熟悉用于沉积种子原子400的常规程序。例如,在一些实施例中,是通过在LP或UHV条件下将含硅的CVD前驱体(例如乙硅烷气体)引入CVD腔结合加热到介于约550℃与约650℃之间以分解乙硅烷分子来沉积包含硅的种子原子400。
现在转到图5,其中显示在转变硅层300和种子原子400以在源极/漏极区230的上方形成多个多晶硅晶粒500后部分构建的源极/漏极电极200。转变指一种其中硅层300的原子的至少一部分迁移并耦接到种子原子400并彼此形成各多晶硅晶粒500的工艺。从而,将硅层300和种子原子400的一部分转变为多晶硅晶粒500。当然,在一些实施例中,将整个硅层300和种子原子400转变为多晶硅晶粒500。
如上所述,在某些优选实施例中,多晶硅晶粒500是HSG,且所述HSG的尺寸将取决于硅层300的厚度。HSG 500的尺寸还取决于实施所述转变的条件。在某些情况下,在与用于沉积种子原子相同的沉积工具(例如CVD工具)内实施所述转变,因为这可减少半导体器件205的制作成本。在一些情况下,使所述转变包括通过将硅层300和种子原子400加热到介于约500℃到约650的温度来对其进行的退火(优选在专用的退火腔或炉中)是理想的。优选地,在超清洁的条件下实施转变。超清洁条件实例包括水分压小于约1×10-7H2O分子/cm3和甚至更优选地小于约1×10-8O2分子/cm3。在一些情况下,在UHV条件下进行所述转变,而在其他情况下使用LP条件进行所述转变是理想的。
现在参考图6,其中显示在多晶硅晶粒500的上方沉积过渡金属层600后部分构建的源极/漏极电极200。在一些实施例中,过渡金属层600是沉积在半导体器件205的整个表面上方的覆盖层。在一些实例中,在沉积过渡金属层600之前,优选地进行预清洁以除去源极/漏极区230和多晶硅晶粒500的表面上的氧化物和其他杂质。预清洁条件的实例包括包含盐酸的湿法刻蚀。
过渡金属原子优选地通过物理气相沉积(PVD)来进行沉积。在一些有利的实施例中,过渡金属层600具有介于约1纳米和约30纳米之间的厚度。在所述方法的一些优选实施例中,所述过渡金属原子包括镍且硅化导致形成硅化镍且更优选地形成单硅化镍层。然而,过渡金属原子还可包括钛、钴、铂和钯,以及这些或其他过渡金属的组合。
一种优选的PVD方法是从过渡金属靶溅射。所属领域的一般技术人员将了解如何调节及选择用于沉积过渡金属原子的溅射方法和条件。当然,可使用其他技术(包括交变电流、无线电频率、磁控或其他市售溅射系统)来完成溅射。另外,其他常规的PVD技术(包括蒸发沉积、分子束外延、离子镀膜、使用电子束蒸发器的离子束辅助沉积和弧气相沉积)也在本发明的范围内。
现在转到图7,其中图解说明在反应掉至少一部分过渡金属层600和多晶硅晶粒500以形成共形地涂覆多晶硅晶粒500的金属硅化物层700之后部分构建的源极/漏极电极200。
在所述方法的一些有利的实施例中,所述形成金属硅化物层700的反应包括将多晶硅晶粒500和过渡金属层600加热到介于约250℃到约550℃的温度至少约0.1秒钟。在其他有利的实施例中,加热包括加热到介于约250℃到约350℃的温度至少约0.1秒钟以形成金属硅化物层700的第一加热步骤和加热到介于350℃和550℃的温度至少约0.1秒钟以将金属硅化物层700进行退火的第二加热步骤。所属领域的一般技术人员将了解如何调节加热温度和持续时间以实现不同过渡金属的硅化。所属领域的技术人员将进一步了解金属硅化可进一步包括使用常规的干法或湿法刻蚀程序以选择性地除去过渡金属层600的未反应部分、同时使金属硅化物电极大体上保持原封不动。
在一些优选实施例中,可使用与其他金属相比相对的低温来有利地实施硅化镍形成,而此又减小了在所述器件的制作期间其所经受的热预算,从而降低制造成本。例如,在一些情况下,将加热维持在低于约400℃的温度,以阻碍二硅化镍的形成。在一些实例中,硅化镍层也优选,因为与许多其他过渡金属硅化物相比,硅化镍具有较低的电阻率。
本发明的再一方面是集成电路。图8绘示实例集成电路800的剖面图,实例集成电路800包括半导体器件805,半导体器件805具有形成于半导体衬底812的上方或内部的源极/漏极电极810。源极/漏极电极810可包括上文中所述和图1和2-7中所示的任何实施例。例如,源极/漏极电极810具有位于源极/漏极区820的上方的多个多晶硅晶粒815,金属硅化物层825共形地涂覆多个多晶硅晶粒815。
半导体器件805的优选实施例包括MOS晶体管,且更优选地,包括一个或多个nMOS晶体管830和pMOS晶体管832。在某些情况下,半导体器件805包括CMOS器件。然而,半导体器件805还可包括结型场效应晶体管、双极晶体管、biCMOS晶体管或其他可从具有本发明的电极810中获益的常规器件组件及其组合。
如图8中进一步图解说明,集成电路800进一步包括位于半导体器件805上方的绝缘层855、860、865中的一者或多者上的互连835、840、845、850。将互连835、840、845、850中的一者或多者连接到源极/漏极电极810以由此互连半导体器件805并形成可操作的器件。
尽管已详细地说明了本发明,但所属领域的一般技术人员应了解,其可在本文中进行各种修改、替代和变更而不背离本发明的范围。
Claims (7)
1.一种包括用于晶体管的源极/漏极电极的半导体器件,其包括:
多个多晶硅晶粒,其位于源极/漏极区上方;
金属硅化物层,其共形地涂覆所述多个多晶硅晶粒;及
硅层,其位于所述多个多晶硅晶粒与所述源极/漏极区之间;
其中所述多个多晶硅晶粒的平均直径在所述硅层的厚度的约0.6倍与约0.9倍之间。
2.如权利要求1所述的器件,其中所述多晶硅晶粒包括具有至少约2纳米的平均直径的半球形多晶硅晶粒(HSG)。
3.如权利要求2所述的器件,其中所述多个HSG具有所述源极/漏极区约每4nm21个HSG与所述源极/漏极区约每1625nm2 1个HSG之间的密度。
4.如权利要求1至3中任一权利要求所述的器件,其中所述多个多晶硅晶粒进一步包括n型或p型掺杂剂。
5.如权利要求1至3中任一权利要求所述的器件,其进一步包括所述金属硅化物层上的金属层。
6.如权利要求1至3中任一权利要求所述的器件,其呈集成电路的形式,其包括多个所述源极/漏极电极,且进一步包括位于所述半导体器件上方的多个绝缘层中的一者上的互连金属线,所述互连金属线互连所述源极/漏极电极以形成可操作器件。
7.一种制造用于半导体器件的源极/漏极电极的方法,其包括:
在源极/漏极区上形成硅层;
在所述硅层上沉积种子原子;
转变所述种子原子和所述硅层以在所述源极/漏极区上方形成多个多晶硅晶粒;及
在多晶硅晶粒上沉积过渡金属层,且反应所述过渡金属层的至少一部分和所述多晶硅晶粒以形成共形地涂覆多晶硅晶粒的金属硅化物层,
其中所述多个多晶硅晶粒的平均直径在所述硅层的厚度的约0.6倍与约0.9倍之间。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/989,480 | 2004-11-16 | ||
US10/989,480 US7109556B2 (en) | 2004-11-16 | 2004-11-16 | Method to improve drive current by increasing the effective area of an electrode |
PCT/US2005/041933 WO2006055828A2 (en) | 2004-11-16 | 2005-11-16 | Silicided source/drain electrode with polysilicon grains |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101443901A CN101443901A (zh) | 2009-05-27 |
CN101443901B true CN101443901B (zh) | 2012-04-25 |
Family
ID=36386898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2005800464679A Active CN101443901B (zh) | 2004-11-16 | 2005-11-16 | 带有多晶硅晶粒的硅化物源极/漏极电极 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7109556B2 (zh) |
CN (1) | CN101443901B (zh) |
WO (1) | WO2006055828A2 (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005332993A (ja) * | 2004-05-20 | 2005-12-02 | Sanyo Electric Co Ltd | 半導体装置および半導体装置の製造方法 |
US8450807B2 (en) | 2010-03-09 | 2013-05-28 | International Business Machines Corporation | MOSFETs with reduced contact resistance |
CN105679671B (zh) * | 2014-11-17 | 2020-01-03 | 上海华力微电子有限公司 | 一种降低源极和漏极电阻的方法 |
CN106298487A (zh) * | 2015-06-11 | 2017-01-04 | 旺宏电子股份有限公司 | 电路与形成该电路的方法 |
US10541172B2 (en) * | 2016-08-24 | 2020-01-21 | International Business Machines Corporation | Semiconductor device with reduced contact resistance |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5907789A (en) * | 1994-01-19 | 1999-05-25 | Sony Corporation | Method of forming a contact-hole of a semiconductor element |
US5937314A (en) * | 1997-02-28 | 1999-08-10 | Micron Technology, Inc. | Diffusion-enhanced crystallization of amorphous materials to improve surface roughness |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US687029A (en) * | 1901-08-19 | 1901-11-19 | William B Hughes | Method of manufacturing steel. |
US3830657A (en) * | 1971-06-30 | 1974-08-20 | Ibm | Method for making integrated circuit contact structure |
US5112773A (en) * | 1991-04-10 | 1992-05-12 | Micron Technology, Inc. | Methods for texturizing polysilicon utilizing gas phase nucleation |
US5554566A (en) * | 1994-09-06 | 1996-09-10 | United Microelectronics Corporation | Method to eliminate polycide peeling |
US6121081A (en) * | 1994-11-15 | 2000-09-19 | Micron Technology, Inc. | Method to form hemi-spherical grain (HSG) silicon |
US5612558A (en) * | 1995-11-15 | 1997-03-18 | Micron Technology, Inc. | Hemispherical grained silicon on refractory metal nitride |
US6218260B1 (en) * | 1997-04-22 | 2001-04-17 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby |
KR100255662B1 (ko) * | 1997-05-03 | 2000-05-01 | 윤종용 | 반구형그레인의다결정실리콘막을갖는반도체장치의제조방법 |
US6043124A (en) * | 1998-03-13 | 2000-03-28 | Texas Instruments-Acer Incorporated | Method for forming high density nonvolatile memories with high capacitive-coupling ratio |
JP2000058790A (ja) * | 1998-08-17 | 2000-02-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6764916B1 (en) * | 1999-03-23 | 2004-07-20 | Hitachi Kokusai Electric Inc. | Manufacturing method for semiconductor device |
US6461915B1 (en) * | 1999-09-01 | 2002-10-08 | Micron Technology, Inc. | Method and structure for an improved floating gate memory cell |
KR100345053B1 (ko) * | 1999-10-01 | 2002-07-19 | 삼성전자 주식회사 | Hsg-si 제조 방법 및 상기 방법을 수행하는 장치 |
US6521515B1 (en) * | 2000-09-15 | 2003-02-18 | Advanced Micro Devices, Inc. | Deeply doped source/drains for reduction of silicide/silicon interface roughness |
US6709945B2 (en) * | 2001-01-16 | 2004-03-23 | Micron Technology, Inc. | Reduced aspect ratio digit line contact process flow used during the formation of a semiconductor device |
US6872622B1 (en) * | 2002-04-09 | 2005-03-29 | Taiwan Semiconductor Manufacturing Company | Method of forming a capacitor top plate structure to increase capacitance and to improve top plate to bit line overlay margin |
-
2004
- 2004-11-16 US US10/989,480 patent/US7109556B2/en active Active
-
2005
- 2005-11-16 CN CN2005800464679A patent/CN101443901B/zh active Active
- 2005-11-16 WO PCT/US2005/041933 patent/WO2006055828A2/en active Application Filing
-
2006
- 2006-08-07 US US11/462,914 patent/US7427543B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5907789A (en) * | 1994-01-19 | 1999-05-25 | Sony Corporation | Method of forming a contact-hole of a semiconductor element |
US5937314A (en) * | 1997-02-28 | 1999-08-10 | Micron Technology, Inc. | Diffusion-enhanced crystallization of amorphous materials to improve surface roughness |
Also Published As
Publication number | Publication date |
---|---|
WO2006055828A2 (en) | 2006-05-26 |
CN101443901A (zh) | 2009-05-27 |
US7427543B2 (en) | 2008-09-23 |
WO2006055828A3 (en) | 2009-05-07 |
US20060105512A1 (en) | 2006-05-18 |
US20060275992A1 (en) | 2006-12-07 |
US7109556B2 (en) | 2006-09-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100362751B1 (ko) | 반도체소자의콘택트홀및그형성방법 | |
US6777275B1 (en) | Single anneal for dopant activation and silicide formation | |
CN101154576A (zh) | 形成具有低电阻的钨多金属栅极的方法 | |
CN1329967C (zh) | 镍-自对准硅化物工艺和利用该工艺制造半导体器件的方法 | |
US8507350B2 (en) | Fabricating method of semiconductor elements | |
US6670263B2 (en) | Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size | |
KR20050005524A (ko) | 감소된 인터페이스 거칠기를 가지는 니켈 실리사이드 | |
CN101443901B (zh) | 带有多晶硅晶粒的硅化物源极/漏极电极 | |
JPH1187711A (ja) | トランジスタ製造方法 | |
US11923367B2 (en) | Low resistance fill metal layer material as stressor in metal gates | |
US6436770B1 (en) | Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation | |
US7803703B2 (en) | Metal-germanium physical vapor deposition for semiconductor device defect reduction | |
CN100388463C (zh) | 制造精密含硅电阻器的方法 | |
CN1937181A (zh) | 具有镍硅化物的半导体元件与制作镍硅化物的方法 | |
US20010053601A1 (en) | Method of manufacturing MIS semiconductor device that can control gate depletion and has low resistance gate electrode to which germanium is added | |
CN102983104B (zh) | Cmos晶体管的制作方法 | |
CN100396609C (zh) | 微小线宽金属硅化物的制作方法 | |
US6284635B1 (en) | Method for forming titanium polycide gate | |
WO2022217782A1 (zh) | 半导体器件的制造方法及其半导体器件 | |
KR101051987B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US20070120199A1 (en) | Low resistivity compound refractory metal silicides with high temperature stability | |
US5897373A (en) | Method of manufacturing semiconductor components having a titanium nitride layer | |
US20220336469A1 (en) | System and methods for dram contact formation | |
US11901182B2 (en) | Silicide film nucleation | |
US20230326764A1 (en) | Silicidation Process for Semiconductor Devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |