CN100396609C - 微小线宽金属硅化物的制作方法 - Google Patents
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
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Abstract
本发明公开了一种新的微小线宽金属硅化物的制作方法。首先，于基底表面形成一间隔层；接着，图案化该间隔层，以于间隔层中形成一开口，同时去除开口两侧以外未被图案化处理的间隔层，保留开口两侧图案化后的间隔层；接着，于整个基底表面全面性形成一多晶硅层，不仅填满开口内部，且覆盖于开口两侧图案化后的间隔层表面；接着，图案化该多晶硅层，仅留下位于开口内以及开口与其两侧图案化后的间隔层上方的多晶硅层；接着，共形于整个基底形成一金属层；最后，实施热处理程序，使图案化后的多晶硅层高于图案化后的间隔层的部分与金属层发生反应，形成金属硅化物。
Description
技术领域
本发明涉及一种金属硅化物，且特别是涉及一种微小线宽金属硅化物及其制作方法。
背景技术
在半导体技术中，金属氧化物半导体(metal-oxide-semiconductor；MOS)晶体管(transistor)是由栅极(gate)、源极(source)与漏极(drain)等三个电极所构成，其中MOS便是构成栅极结构的主体。早期的MOS是由金属层(metal layer)、二氧化硅(SiO2)与含硅基底(silicon-basedsubstrate)等三层材质所组成的。但是，由于大多数金属对于二氧化硅的附着能力(adhesion)很差，所以对于二氧化硅具有较佳附着能力的多晶硅(polysilicon)便被提出以取代金属层。然而，使用多晶硅却有电阻值太高的问题存在。即使多晶硅经过掺杂，其电阻值还是太高，并不适合用来取代MOS的金属层。于是，熟悉本领域的技术人员便提出一解决方法，也就是于多晶硅的表面再多加一层厚度与多晶硅层相当的金属硅化物(metalsalicide)，利用导电性较佳的金属硅化物与多晶硅共同组成导电层。
随着半导体组件的集积度不断增加，各组件的线宽必需随之缩小，目前栅极层的线宽已经由0.13、0.10微米降至0.07微米甚至0.05微米以下。
然而，栅极层的线宽小于0.1微米以下(0.07微米、0.05微米)的金属硅化物却有聚附(agglomeration)的问题发生，因而导致其阻值的增加，甚至导致断线。
发明内容
有鉴于此，本发明主要目的在于解决上述问题，提供一种微小线宽金属硅化物及其制作方法，其可适用于线宽小于0.1微米的栅极层的制程，可避免金属硅化物聚附的现象发生。
本发明解决问题的主要技术特征在于使多晶硅延伸至开口两侧的间隔层上方，如此一来，虽然两间隔层之间的多晶硅线宽很微小，但是高于间隔层的多晶硅部分向间隔层的表面延伸覆盖后，便具有足够的线宽，以致在形成金属硅化物后仍不会有聚附的现象发生。
为达到上述目的，本发明提出了一种微小线宽金属硅化物的制作方法，该方法的步骤主要包括：
提供一基底；在基底表面形成一间隔层；图案化所述间隔层，以于间隔层中形成一开口，同时去除上述开口两侧以外未被图案化处理的间隔层，保留开口两侧图案化后的间隔层；于整个基底表面全面性形成一硅层(多晶硅层)，不仅填满上述开口内部且覆盖于上述开口两侧图案化后的间隔层表面；图案化上述硅层，仅留下位于上述开口内以及上述开口与其两侧图案化后的间隔层上方的硅层；共形于整个基底形成一金属层；以及实施一热处理程序，使上述图案化后的硅层高于上述图案化后的间隔层的部分与上述金属层发生反应，形成一金属硅化物。
在本发明的制作方法中，通过去除开口两侧以外未被图案化处理的间隔层，而使得由横截面观看的间隔层于开口两侧形成两柱状图案化后的间隔层，其中所述开口宽度根据制程优选小于0.1微米，而开口与其两侧图案化后的间隔层宽度的总和应不小于0.1微米。并且，上述图案化后的硅层高于图案化后的间隔层的部分的宽度也应不小于0.1微米。
根据本发明的具体实施方案，图案化后的硅层高于图案化后的间隔层的部分的厚度约为200-500
以便高于图案化后的间隔层的图案化多晶硅于后续热处理程序时可与金属层反应，完全转变成金属硅化物。另外，间隔层的厚度约为400-600
本发明中，所述间隔层的材质可包括氮化物，例如Si3N4。所述金属层可包括钛(Ti)、钴(Co)或镍(Ni)。
在具体实施时，本发明的方法中还可进一步包括：形成一衬垫氧化层于所述多晶硅层与基底之间。并且，在形成金属硅化物之后还可进一步包括：去除未参与反应的金属层。
本发明的方法中所述热处理优选为快速加热制程(rapid thermalprocess；RTP)。
在提供上述方法的同时，本发明还提供了一种微小线宽金属硅化物，其包括：
一基底；二柱状间隔层，设置于基底表面；一多晶硅层，设置于上述柱状间隔层表面且填满两柱状间隔层的间隔区域；以及一金属硅化物层，设置于多晶硅层表面。
综上所述，本发明提供的微小线宽金属硅化物及其制作方法，由于使多晶硅延伸至开口两侧的间隔层上方，而使两间隔层之间的多晶硅线宽虽然很微小，但是高于间隔层的多晶硅部分向间隔层的表面延伸覆盖后，便具有足够的线宽，以致在形成金属硅化物后仍不会有聚附的现象发生。本发明的微小线宽金属硅化物及其制作方法可适用于栅极层的线宽小于0.1微米以下的制程，并可避免金属硅化物聚附的现象发生。
附图说明
图1至图11B为显示根据本发明的一优选实施例的制程剖面示意图。
图中主要符号说明：
100基底 102间隔层 104图案化第一光刻胶 I开口
102a图案化后的间隔层(柱状间隔层) 106栅极氧化层 108多晶硅层
110图案化第二光刻胶 d金属硅化物宽度 108a图案化后的多晶硅层
112金属层 114金属硅化物 101衬垫氧化层
具体实施方式
为使本发明的上述目的、特征和优点能更明显易懂，现列举具体优选实施例，并配合附图，详细说明如下：
以下请参见图1至图11所示的制程剖面图，说明根据本发明的一优选实施例。
首先，请参见图1，先提供一基底100，例如：适用于半导体的硅基底，再于上述基底100表面形成一间隔层102，预备作为后续制作的栅极层的间隔层。间隔层的厚度例如可大于500
其材质可包括氮化物，例如Si3N4。另外，基底100与间隔层102之间可形成一衬垫氧化层101，形成方法例如利用适当化学气相沉积法(CVD)等。
接着，请参见图2，例如利用适当的旋涂法(spin coating)上光刻胶与适当的光刻、显像过程定义光刻胶图案，以于间隔层102表面形成具有预定图案的第一光刻胶104。
接着，请参见图3，以图案化第一光刻胶104为掩膜，蚀刻未被图案化第一光刻胶104遮蔽的间隔层102，使间隔层102图案化，以形成一开口I于间隔层102中，同时去除开口I两侧以外未被图案化处理的间隔层102，使得由横截面观看到的间隔层102于开I两侧形成两柱状间隔层(图案化后的间隔层)102a，该柱状间隔层的厚度可约为400-600
后续将在开口I位置制作栅极层，因此开口I的宽度需与制程中栅极层的线宽一致，例如：0.07微米或0.05微米。必须注意的是，间隔层的宽度必须经过设计、控制，使得开口I宽度与其两侧图案化后的间隔层102a宽度的总和必须不小于0.1微米。例如：针对栅极线宽0.07微米的制程，开口I宽度则为0.07微米，而图案化后的间隔层102a的宽度至少为0.03微米。然后，再去除图案化第一光刻胶104。
接着，请参见图4，可例如利用适当沉积程序，共形于整个基底表面形成一栅极氧化层106，其材质例如为高介电常数的氧化物，厚度约为15-200
其可利用热氧化法在650-1000℃之间，反应5-3600秒而得。
接着，请参见图5，先例如利用化学气相沉积(chemical vapordeposition；CVD)，于整个基底表面全面性形成一多晶硅层108，不仅填满开口I内部且覆盖于开口两侧图案化后的间隔层(柱状间隔层)102a表面，其厚度约为3000-8000
再实行一化学机械研磨(chemicalmechanical polishing；CMP)程序，使多晶硅层108的表面平坦化，直到多晶硅层108高于图案化后的间隔层102a部分的厚度约为200-500
为止，以便高于图案化后的间隔层102a的多晶硅108可在后续制程阶段完全转变成金属硅化物。
接着，请参见图6，例如利用适当的旋涂法上光刻胶与适当的光刻、显像过程定义光刻胶图案，仅在两图案化后的间隔层102a的范围内上方的多晶硅层108表面形成一图案化第二光刻胶110。
接着，请参见图7A与图7B，以图案化第二光刻胶110为掩膜，蚀刻未被图案化的第二光刻胶110遮蔽的多晶硅层108，以图案化多晶硅层108，仅留下位于开口I内以及开口I与其两侧图案化后的间隔层102a上方的图案化后的多晶硅层108a。图案化后的多晶硅层108a可以覆盖满整个图案化后的间隔层102a表面，如图7A所示；也可以仅覆盖部分图案化后的间隔层102a表面，如图7B所示。重要的是，图案化后的多晶硅层108a高于图案化后的间隔层102a的部分的宽度d，也就是后续与金属层反应形成金属硅化物的部分，必须不小于0.1微米，此为本发明的特征。后续继续以图7B为例说明以下制程。
接着，请参见图8，去除图案化第二光刻胶110后，实施一离子注入程序500，使未被图案化后的间隔层102a与图案化后的多晶硅层108a覆盖的基底内形成离子掺杂的源极S/漏极D(source/drain)。
接着，请参见图9，例如利用溅镀法(sputtering)，于整个基底共形形成一金属层112。上述金属层包括钛(Ti)、钴(Co)或镍(Ni)。
接着，请参见图10，实施一热处理程序，例如：快速加热制程(rapidthermal process；RTP)，使图案化后的多晶硅层108a高于图案化后的间隔层102a的部分与金属层112发生反应，形成一金属硅化物114。如前所述，需适当选择多晶硅的厚度，才能使高于图案化后的间隔层102a的图案化后的多晶硅108a完全转变成金属硅化物114。并且，由于图案化后的多晶硅层108a高于图案化后的间隔层102a的部分的宽度d不小于0.1微米，所以，形成金属硅化物114后不会有聚附的问题产生。
最后，请参见图11A与图11B，利用适当蚀刻程序，去除未参与反应的金属层112，便完成应用于线宽小于0.1微米的栅极层的金属硅化物制作。本发明的微小线宽金属硅化物包括：一基底100；二柱状间隔层102a，设置于上述基底100表面；一多晶硅层108a，设置于上述柱状间隔层102a表面且填满上述两柱状间隔层102a的间隔区域；以及一金属硅化物层114，设置于上述多晶硅层108a表面。图11A显示由图7A所得的结果，即金属硅化物114覆盖满整个间隔层102a表面。图11B显示由图7B所得的结果，即仅覆盖部分间隔层102a表面。
本发明虽以优选实施例揭露如上，然其并非用以限定本发明的范围，任何熟悉本领域的技术人员，在不脱离本发明的精神和范围内，当可做各种的更动与润饰，本发明的保护范围应以权利要求书为准。
Claims (10)
1.一种微小线宽金属硅化物的制作方法，包括：
提供一基底；
于上述基底表面形成一间隔层；
图案化上述间隔层，以于间隔层中形成一开口，同时去除上述开口两侧以外未被图案化处理的间隔层，保留开口两侧图案化后的间隔层；
于整个基底表面全面性形成一硅层，不仅填满上述开口内部且覆盖于上述开口两侧图案化后的间隔层表面；
图案化上述硅层，仅留下位于上述开口内以及上述开口与其两侧图案化后的间隔层上方的硅层；
共形于整个基底形成一金属层；以及
实施一热处理程序，使上述图案化后的硅层高于上述图案化后的间隔层的部分与上述金属层发生反应，形成一金属硅化物，其中该金属硅化物的微小线宽小于0.1微米。
2.如权利要求1所述的微小线宽金属硅化物的制作方法，其中所述开口的宽度小于0.1微米。
3.如权利要求1所述的微小线宽金属硅化物的制作方法，其中所述图案化后的硅层高于图案化后的间隔层的部分的宽度不小于0.1微米。
4.如权利要求1所述的微小线宽金属硅化物的制作方法，其中所述图案化后的硅层高于图案化后的间隔层的部分的厚度为200-500
5.如权利要求1所述的微小线宽金属硅化物的制作方法，其中所述间隔层的厚度为400-600
6.如权利要求1所述的微小线宽金属硅化物的制作方法，其中所述间隔层包括氮化硅。
7.如权利要求1所述的微小线宽金属硅化物的制作方法，其中所述金属层是钛、钴或镍。
8.如权利要求1所述的微小线宽金属硅化物的制作方法，其中进一步包括：于所述硅层与基底之间形成一衬垫氧化层。
9.如权利要求1所述的微小线宽金属硅化物的制作方法，其中形成金属硅化物之后进一步包括：去除未参与反应的金属层。
10.如权利要求1所述的微小线宽金属硅化物的制作方法，其中所述热处理为快速加热制程。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/347,007 | 2003-01-17 | ||
| US10/347,007 US20040142517A1 (en) | 2003-01-17 | 2003-01-17 | Hatted polysilicon gate structure for improving salicide performance and method of forming the same |
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| Publication Number | Publication Date |
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| CN1517300A CN1517300A (zh) | 2004-08-04 |
| CN100396609C true CN100396609C (zh) | 2008-06-25 |
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| CNB2004100005919A Expired - Fee Related CN100396609C (zh) | 2003-01-17 | 2004-01-15 | 微小线宽金属硅化物的制作方法 |
Country Status (4)
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| US (2) | US20040142517A1 (zh) |
| CN (1) | CN100396609C (zh) |
| SG (1) | SG116522A1 (zh) |
| TW (1) | TWI228779B (zh) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100499158B1 (ko) * | 2003-02-28 | 2005-07-01 | 삼성전자주식회사 | 상부면적이 확장된 확장형 게이트 및 이를 구비하는반도체 소자의 제조방법 |
| KR100629266B1 (ko) | 2004-08-09 | 2006-09-29 | 삼성전자주식회사 | 샐리사이드 공정 및 이를 사용한 반도체 소자의 제조방법 |
| US7115921B2 (en) * | 2004-08-31 | 2006-10-03 | International Business Machines Corporation | Nano-scaled gate structure with self-interconnect capabilities |
| US7456058B1 (en) * | 2005-09-21 | 2008-11-25 | Advanced Micro Devices, Inc. | Stressed MOS device and methods for its fabrication |
| KR100696197B1 (ko) * | 2005-09-27 | 2007-03-20 | 한국전자통신연구원 | 실리콘 기판을 이용한 다중 게이트 모스 트랜지스터 및 그제조 방법 |
| US8901665B2 (en) * | 2011-12-22 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure for semiconductor device |
| CN104943082A (zh) * | 2014-03-27 | 2015-09-30 | 杨登任 | 可替换安装多个模仁的成型模具组 |
| FR3076394A1 (fr) * | 2018-01-04 | 2019-07-05 | Stmicroelectronics (Rousset) Sas | Espaceurs de transistors mos et leur procede de fabrication |
| CN111584432A (zh) * | 2020-05-28 | 2020-08-25 | 福建省晋华集成电路有限公司 | 动态随机存取存储器及其制作方法 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1213163A (zh) * | 1997-09-29 | 1999-04-07 | Lg半导体株式会社 | 半导体器件的制造方法 |
| US5918143A (en) * | 1997-02-12 | 1999-06-29 | Universite De Sherbrooke | Fabrication of sub-micron silicide structures on silicon using resistless electron beam lithography |
| US5970370A (en) * | 1998-12-08 | 1999-10-19 | Advanced Micro Devices | Manufacturing capping layer for the fabrication of cobalt salicide structures |
| JP2000196081A (ja) * | 1998-12-22 | 2000-07-14 | Hyundai Electronics Ind Co Ltd | チタンポリサイドゲ―ト電極形成方法 |
| US6262458B1 (en) * | 1997-02-19 | 2001-07-17 | Micron Technology, Inc. | Low resistivity titanium silicide structures |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0448640A (ja) * | 1990-06-14 | 1992-02-18 | Oki Electric Ind Co Ltd | Ｍｏｓトランジスタの製造方法 |
| WO1996030946A1 (fr) | 1995-03-29 | 1996-10-03 | Hitachi, Ltd. | Dispositif semi-conducteur et son procede de fabrication |
| JP2848299B2 (ja) * | 1995-12-21 | 1999-01-20 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| US6197645B1 (en) * | 1997-04-21 | 2001-03-06 | Advanced Micro Devices, Inc. | Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls |
| US5937299A (en) * | 1997-04-21 | 1999-08-10 | Advanced Micro Devices, Inc. | Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls |
| US6159781A (en) * | 1998-10-01 | 2000-12-12 | Chartered Semiconductor Manufacturing, Ltd. | Way to fabricate the self-aligned T-shape gate to reduce gate resistivity |
| US6630712B2 (en) * | 1999-08-11 | 2003-10-07 | Advanced Micro Devices, Inc. | Transistor with dynamic source/drain extensions |
| US6214680B1 (en) * | 1999-12-13 | 2001-04-10 | Chartered Semiconductor Manufacturing, Ltd. | Method to fabricate a sub-quarter-micron MOSFET with lightly doped source/drain regions |
| US6433371B1 (en) * | 2000-01-29 | 2002-08-13 | Advanced Micro Devices, Inc. | Controlled gate length and gate profile semiconductor device |
| US6326290B1 (en) | 2000-03-21 | 2001-12-04 | Taiwan Semiconductor Manufacturing Company | Low resistance self aligned extended gate structure utilizing A T or Y shaped gate structure for high performance deep submicron FET |
| US6204133B1 (en) * | 2000-06-02 | 2001-03-20 | Advanced Micro Devices, Inc. | Self-aligned extension junction for reduced gate channel |
| US6579783B2 (en) | 2000-07-07 | 2003-06-17 | Applied Materials, Inc. | Method for high temperature metal deposition for reducing lateral silicidation |
| US6350688B1 (en) | 2000-08-01 | 2002-02-26 | Taiwan Semiconductor Manufacturing Company | Via RC improvement for copper damascene and beyond technology |
| US6890854B2 (en) | 2000-11-29 | 2005-05-10 | Chartered Semiconductor Manufacturing, Inc. | Method and apparatus for performing nickel salicidation |
-
2003
- 2003-01-17 US US10/347,007 patent/US20040142517A1/en not_active Abandoned
-
2004
- 2004-01-05 SG SG200400028A patent/SG116522A1/en unknown
- 2004-01-15 CN CNB2004100005919A patent/CN100396609C/zh not_active Expired - Fee Related
- 2004-01-16 TW TW093101146A patent/TWI228779B/zh not_active IP Right Cessation
- 2004-07-19 US US10/894,542 patent/US6884669B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5918143A (en) * | 1997-02-12 | 1999-06-29 | Universite De Sherbrooke | Fabrication of sub-micron silicide structures on silicon using resistless electron beam lithography |
| US6262458B1 (en) * | 1997-02-19 | 2001-07-17 | Micron Technology, Inc. | Low resistivity titanium silicide structures |
| CN1213163A (zh) * | 1997-09-29 | 1999-04-07 | Lg半导体株式会社 | 半导体器件的制造方法 |
| US5970370A (en) * | 1998-12-08 | 1999-10-19 | Advanced Micro Devices | Manufacturing capping layer for the fabrication of cobalt salicide structures |
| JP2000196081A (ja) * | 1998-12-22 | 2000-07-14 | Hyundai Electronics Ind Co Ltd | チタンポリサイドゲ―ト電極形成方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20040259342A1 (en) | 2004-12-23 |
| CN1517300A (zh) | 2004-08-04 |
| US6884669B2 (en) | 2005-04-26 |
| TWI228779B (en) | 2005-03-01 |
| SG116522A1 (en) | 2005-11-28 |
| TW200423259A (en) | 2004-11-01 |
| US20040142517A1 (en) | 2004-07-22 |
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