WO2022217782A1 - 半导体器件的制造方法及其半导体器件 - Google Patents

半导体器件的制造方法及其半导体器件 Download PDF

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Publication number
WO2022217782A1
WO2022217782A1 PCT/CN2021/109068 CN2021109068W WO2022217782A1 WO 2022217782 A1 WO2022217782 A1 WO 2022217782A1 CN 2021109068 W CN2021109068 W CN 2021109068W WO 2022217782 A1 WO2022217782 A1 WO 2022217782A1
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layer
conductive layer
conductive
bit line
barrier layer
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PCT/CN2021/109068
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English (en)
French (fr)
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何丹丹
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长鑫存储技术有限公司
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Priority to US17/605,011 priority Critical patent/US20230180463A1/en
Publication of WO2022217782A1 publication Critical patent/WO2022217782A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to, but is not limited to, a method for manufacturing a semiconductor device and a semiconductor device thereof.
  • the ohmic contact process is a manufacturing process that is often used in the manufacture of semiconductor devices, wherein the ohmic contact refers to a region on a semiconductor device with a linear and symmetrical current-voltage characteristic curve.
  • the purpose of the ohmic contact process is to reduce the contact resistance between metals and non-metals in semiconductor devices (such as integrated circuits), thereby effectively improving the electrical conductivity of the semiconductor devices.
  • the most commonly used contact materials are TiSix (Ti is titanium, Si is silicon, and x is a constant), or CoSix (Co is cobalt), etc., where TiSix or CoSix is composed of Ti or Co formed on a silicon substrate.
  • TiSix or CoSix is composed of Ti or Co formed on a silicon substrate.
  • the traditional process for preparing ohmic contacts is prone to the problem that Ti or Co are not completely converted into compounds, but are precipitated between metals and non-metals. In this way, when the semiconductor device is energized, free Ti or Co will cause a short circuit in the metal layer of the semiconductor device, so that the electrical conductivity of the semiconductor device is reduced, thereby affecting the yield of the semiconductor device.
  • Embodiments of the present application provide a method for manufacturing a semiconductor device, including:
  • the surface area of the upper surface of the first conductive layer is greater than the surface area of the upper surface of the first conductive material layer;
  • Remove part of the dielectric layer, part of the fourth conductive layer, part of the third conductive layer, part of the first barrier layer, part of the second conductive layer, part of the ohmic contact layer and part of the first A conductive layer, the rest of the fourth conductive layer, the third conductive layer, the first barrier layer, the second conductive layer, the ohmic contact layer, the first conductive layer and the medium layer constitutes the initial bit line structure;
  • NH 3 /N 2 plasma treatment is performed on the initial bit line structure to form a second barrier layer on the sidewall of the first conductive layer, and a third barrier layer is formed on the sidewall of the ohmic contact layer, so
  • the second barrier layer, the third barrier layer and the initial bit line structure constitute a bit line structure, wherein the second barrier layer and the third barrier layer are used to prevent metal in the ohmic contact layer Precipitation;
  • bit line sidewall protective layer is formed, and the bit line sidewall protective layer covers the surface of the bit line structure.
  • the present application provides a semiconductor device including
  • a first conductive layer disposed on the substrate, and the upper surface of the first conductive layer is in an uneven shape
  • the second conductive layer is disposed on the first conductive layer, and an ohmic contact layer is formed at the intersection of the first conductive layer and the second conductive layer;
  • a first barrier layer disposed on the second conductive layer
  • a third conductive layer disposed on the first barrier layer
  • a fourth conductive layer disposed on the third conductive layer
  • a dielectric layer disposed on the fourth conductive layer
  • a second barrier layer disposed on the sidewall of the first conductive layer
  • a third barrier layer is provided on the sidewall of the ohmic contact layer; wherein the first conductive layer, the second conductive layer, the first barrier layer, the third conductive layer, the fourth conductive layer
  • the conductive layer, the second barrier layer, the third barrier layer and the dielectric layer constitute a bit line structure, and the second barrier layer and the third barrier layer are used to prevent the metal in the ohmic contact layer Precipitation;
  • bit line sidewall protection layer covers the surface of the bit line structure.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a semiconductor device according to Embodiment 1 of the present application.
  • FIG. 2 is a partial schematic diagram of the semiconductor device provided in Embodiment 1 of the present application.
  • FIG. 3 is a partial schematic diagram of the semiconductor device provided in Embodiment 1 of the present application.
  • FIG. 4 is a partial schematic diagram of the semiconductor device provided in Embodiment 1 of the present application.
  • FIG. 5 is a partial schematic diagram of the semiconductor device provided in Embodiment 1 of the present application.
  • FIG. 6 is a schematic diagram of an initial bit line structure provided in Embodiment 1 of the present application.
  • FIG. 7 is a schematic diagram of a bit line structure provided in Embodiment 1 of the present application.
  • FIG. 8 is a schematic diagram of the semiconductor device provided in Embodiment 1 and Embodiment 2 of the present application.
  • the ohmic contact process is a commonly used manufacturing process.
  • the purpose of the ohmic contact process is to reduce the contact resistance between metals and non-metals in semiconductor devices (such as integrated circuits), thereby effectively improving the conductivity of semiconductor devices. performance.
  • the most commonly used contact materials are TiSix (Ti is titanium, Si is silicon, and x is a constant), or CoSix (Co is cobalt), etc., where TiSix or CoSix is composed of Ti or Co formed on a silicon substrate.
  • the traditional process for preparing ohmic contacts is prone to the problem that Ti or Co are not completely converted into compounds, but are precipitated between metals and non-metals.
  • free Ti or Co will cause a short circuit in the metal layer of the semiconductor device, so that the electrical conductivity of the semiconductor device is reduced.
  • the metal precipitation problem existing in the traditional ohmic contact process technology has seriously affected the yield of semiconductor devices.
  • the present application provides a method for manufacturing a semiconductor device and a semiconductor device therefor.
  • the method for manufacturing a semiconductor device is to first provide a substrate, and then stack the substrate to form a first conductive layer, an ohmic contact layer, and a second conductive layer. , the first barrier layer, the third conductive layer, the fourth conductive layer and the dielectric layer, and then remove part of the first conductive layer, part of the ohmic contact layer, part of the second conductive layer, part of the first barrier layer, part of the An initial bit line structure is formed after the third conductive layer, part of the fourth conductive layer and part of the dielectric layer.
  • the resulting bit line structure has a second barrier layer and a third barrier layer.
  • the second barrier layer is formed on the sidewall of the first conductive layer
  • the third barrier layer is formed on the sidewall of the ohmic contact layer.
  • the manufacturing method of a semiconductor device provided by the present application is applied to a semiconductor manufacturing apparatus, and the semiconductor manufacturing apparatus may be an integrated apparatus that can perform the manufacturing method of a semiconductor device provided as follows.
  • the semiconductor manufacturing equipment may also be separate multiple equipments that respectively perform one or more steps in the manufacturing method of a semiconductor device provided below.
  • Embodiment 1 of the present application provides a method for manufacturing a semiconductor device, including:
  • the substrate 111 is a silicon substrate.
  • the material of the substrate 111 can also be selected according to actual needs, which is not limited in this application.
  • FIG. 2 is a schematic diagram after the first conductive material layer 112 is formed on the substrate.
  • the first conductive material layer 112 may be polysilicon doped with phosphorus ions.
  • the phosphorus ions can also be replaced by other non-metal ions, such as boron ions.
  • the first conductive material layer 112 can be formed by selective ion implantation, for example, phosphorus ions are implanted on the substrate 111 to form the first conductive material layer 112 doped with phosphorus ions.
  • Plasma also known as plasma, is the fourth largest state of matter in addition to solid, liquid and gaseous states. Gases become plasma when exposed to high temperatures or strong electromagnetic fields, where atoms in the gas have more or fewer electrons than normal, forming anions or cations, negatively or positively charged particles.
  • the first conductive material layer 112 is subjected to plasma treatment, that is, the first conductive material layer 112 is treated with plasma to form the first conductive layer 113.
  • the upper surface of the first conductive material layer 112 may be treated with argon plasma (Ar) to form uneven shapes on the upper surface of the first conductive material layer 112 .
  • the uneven shape is a corrugated shape as shown in FIG. 3 , and the uneven shape can increase the contact area between the first conductive layer 113 and the second conductive layer 115 , thereby reducing the final ohmic contact layer 114 formed The resistance.
  • treating the upper surface of the first conductive material layer 112 with argon plasma can effectively remove oxides on the upper surface of the first conductive material layer 112, reducing the first conductive material layer 112.
  • the disconnection between the conductive layer 113 and the second conductive layer 115 improves the conductivity of the semiconductor device.
  • the parameters of the argon plasma can be selected according to actual needs, which are not limited in this application.
  • the treatment time may be 5 seconds to 20 seconds
  • the energy of the argon plasma treatment may be 300 watts to 1000 watts
  • the argon plasma The temperature of the treatment may be room temperature.
  • the gas flow rate for the argon plasma treatment can range from 20 milliliters per minute (sccm) to 200 milliliters per minute (sccm).
  • the material of the first conductive layer 113 is polysilicon doped with phosphorus ions
  • the material of the second conductive layer 115 may be cobalt (Co) or titanium (Ti).
  • the first barrier layer 116 may be a Co-containing nitride, such as cobalt nitride (CoN).
  • the first barrier layer 116 may be a Ti-containing nitride, such as titanium nitride (TiN).
  • the material of the third conductive layer 117 may be a silicide containing tungsten, such as tungsten silicide (WSi), and the material of the fourth conductive layer 118 may be metal tungsten.
  • FIG. 4 is a schematic diagram after forming the second conductive layer, the first barrier layer, the third conductive layer and the fourth conductive layer in sequence.
  • a dielectric layer is formed on the fourth conductive layer, and at the same time, an ohmic contact layer is formed at the junction of the first conductive layer and the second conductive layer.
  • the dielectric layer 119 can also be understood as an insulating layer, the dielectric layer 119 is formed on the fourth conductive layer 118 , and the dielectric layer 119 is used to insulate the fourth conductive layer 118 from the outside.
  • the material of the dielectric layer 119 may be silicon nitride.
  • the dielectric layer 119 may be formed on the fourth conductive layer 118 by using a chemical vapor deposition process at a temperature of 600° C. ⁇ 650° C.
  • the thickness of the dielectric layer 119 is 80 nm ⁇ 120 nm, and the chemical vapor deposition process can reduce the time for forming the dielectric layer 119 and reduce the production cost.
  • the formation temperature of the dielectric layer 119 is relatively high, ranging from 600° C. to 650° C.
  • the first conductive layer 113 is connected to the second conductive layer 115 at the same time.
  • a reaction occurs there, and the ohmic contact layer 114 is formed.
  • the ohmic contact layer 114 refers to a region with a linear and symmetrical current-voltage characteristic curve. The ohmic contact layer 114 can reduce the contact resistance between the first conductive layer 113 and the second conductive layer 115, thereby effectively improving the conductivity of the semiconductor device.
  • the ohmic contact layer 114 is a contact layer formed by the reaction between Ti and silicon in the first conductive layer 113 , and the ohmic contact layer 114 includes silicidation Titanium (TiSi 2 ).
  • the ohmic contact layer 114 is a contact layer formed by the reaction of Co and silicon in the first conductive layer 113 , and the ohmic contact layer 114 includes cobalt silicide (CoSi 2 ).
  • the ohmic contact layer 114 When the ohmic contact layer 114 is formed, a part of the metal (Ti or Co) may be unreacted. If the unreacted metal is not isolated, it will be easily precipitated in the subsequent semiconductor device preparation, thereby causing a short circuit of the semiconductor device.
  • the fourth conductive layer, the third conductive layer, the first barrier layer, the second conductive layer, the ohmic contact layer and part of the first conductive layer constitute an initial bit line structure.
  • FIG. 6 shows the initial bit line structure 110.
  • the initial bit line structure 110 removes part of the dielectric layer 119, part of the fourth conductive layer 118, and part of the third conductive layer layer 117 , part of the first barrier layer 116 , part of the second conductive layer 115 , part of the ohmic contact layer 114 and part of the first conductive layer 113 .
  • the initial bit line structure 110 has a plurality of structures with the same composition on the substrate 111. At this time, the ohmic contact layers 114 in the plurality of structures may have metal precipitation. The contact layer 114 is processed.
  • S107, NH 3 /N 2 plasma treatment is performed on the initial bit line structure to form a second barrier layer 120 on the sidewall of the first conductive layer, and a third barrier layer 130 is formed on the sidewall of the ohmic contact layer,
  • the second barrier layer 120 , the third barrier layer 130 and the initial bit line structure constitute a bit line structure, wherein the second barrier layer 120 and the third barrier layer 130 are used to prevent metal in the ohmic contact layer 114 Precipitate.
  • FIG. 7 is a schematic diagram of the bit line structure 100 having the second barrier layer 120 and the third barrier layer 130 .
  • the ohmic contact layer 114 may be Contains unreacted Ti.
  • silicon nitride can be formed on the sidewall of the first conductive layer 113 as the second barrier layer 120 , and on the sidewall of the ohmic contact layer 114 TiN is formed as the third barrier layer 130 . Both the second barrier layer 120 and the third barrier layer 130 can block the precipitation of unreacted Ti in the ohmic contact layer 114 .
  • the ohmic contact layer 114 may be Contains unreacted Co.
  • silicon nitride can be formed on the sidewall of the first conductive layer 113 as the second barrier layer 120 , and on the sidewall of the ohmic contact layer 114 CoN is formed as the third barrier layer 130 . Both the second barrier layer 120 and the third barrier layer 130 can block the precipitation of unreacted Co in the ohmic contact layer 114 .
  • the NH 3 /N 2 plasma can also be replaced with other plasmas capable of nitriding treatment, which can be selected according to actual needs, which is not limited in this application.
  • the gas flow rate of the NH 3 plasma may be 300 milliliters per minute (sccm) to 2000 milliliters per minute (sccm).
  • bit line sidewall protection layer covering the surface of the bit line structure.
  • bit line sidewall protection layer 200 covers the surface of the bit line structure 100 .
  • the material of the bit line sidewall protection layer 200 may be silicon nitride (Si 3 N 4 ).
  • the bit line sidewall protection layer 200 may be formed by using an atomic layer deposition process at a temperature of 600° C. ⁇ 650° C.
  • the thickness of the bit line sidewall protection layer 200 is 10nm-20nm
  • the bitline sidewall protection layer 20 is formed by using the atomic layer deposition process, which can well control the thickness of the bitline sidewall protection layer 200 at various positions to ensure the semiconductor device performance.
  • other methods can also be selected to form the bit line sidewall protection layer 200 according to actual needs, which is not limited in this application.
  • bit line sidewall protection layer 200 The function of the bit line sidewall protection layer 200 is similar to that of the second barrier layer 120 and the third barrier layer 130 , and the bitline sidewall protection layer 200 can effectively prevent the metal precipitated in the ohmic contact layer 114 from escaping from the bit line
  • the structure 100 can be protected to prevent the bit line structure 100 from being short-circuited during use, thereby effectively improving the conductivity and yield of the semiconductor device.
  • the manufacturing method of the semiconductor device provided in this embodiment provides a second barrier layer 120 , a third barrier layer 130 and a bit line sidewall protection layer 200 , and the second barrier layer 120 is formed on the first portion of the initial bit line structure 100 .
  • the sidewalls of the conductive layer 113 , the third barrier layer 130 are formed on the sidewalls of the ohmic contact layer 114 of the initial bit line structure 100 , and the bit line sidewall protection layer 200 covers the surface of the bit line structure 100 .
  • the manufacturing method of the semiconductor device provided in this embodiment can effectively improve the yield of the semiconductor device.
  • the ohmic contact layer 114 is formed at the junction of the first conductive layer 113 and the second conductive layer 115 .
  • the upper surface of the first conductive layer 113 is in an uneven shape, which can increase the contact area between the first conductive layer 113 and the second conductive layer 115, thereby reducing the final ohmic contact layer formed. 114 resistor.
  • step S107 in the first embodiment includes:
  • NH 3 /N 2 plasma treatment is performed on the initial bit line structure 110 to form a second barrier layer 120 on the sidewall of the first conductive layer 113 and a third barrier layer 130 on the sidewall of the ohmic contact layer 114 , a fourth barrier layer 140 is formed on the sidewall of the second conductive layer 115 , a fifth barrier layer 150 is formed on the sidewall of the third conductive layer 117 , and a sixth barrier layer 160 is formed on the sidewall of the fourth conductive layer 118 .
  • the second barrier layer 120 , the third barrier layer 130 , the fourth barrier layer 140 , the fifth barrier layer 150 , the sixth barrier layer 160 and the initial bit line structure 110 constitute the bit line structure 100 .
  • the material of the second barrier layer 120 may be silicon nitride, and the material of the third barrier layer 130 may be TiN or CoN.
  • the fourth barrier layer 140 is made of the same material as the first barrier layer 116 .
  • the material of the fourth barrier layer 140 is TiN.
  • the material of the fourth barrier layer 140 is CoN.
  • the fifth barrier layer 150 is formed on the sidewall of the third conductive layer 117 .
  • the fifth barrier layer 150 includes tungsten silicide doped with nitrogen ions.
  • the fourth conductive layer 118 is metal tungsten
  • the sixth barrier layer 160 is tungsten nitride. The fifth barrier layer 150 and the sixth barrier layer 160 can effectively prevent metal tungsten from being precipitated, thereby improving the electrical conductivity of the semiconductor device.
  • the NH 3 /N 2 plasma can also be replaced with other plasmas capable of nitriding treatment, which can be selected according to actual needs, which is not limited in this application.
  • a second embodiment of the present application provides a semiconductor device 10 .
  • the semiconductor device 10 includes a substrate 111 , a bit line structure 100 and a bit line sidewall protection layer 200 , and the bit line sidewall protection layer 200 covers the bit line.
  • the bit line sidewall protection layer 200 is a protection layer formed by an atomic layer deposition process at a temperature of 600° C. ⁇ 650° C.
  • the material of the bit line sidewall protection layer 200 may be silicon nitride (Si 3 N 4 ).
  • the atomic layer deposition process can well control the thickness of the bit line sidewall protection layer 200 at various positions, so as to ensure the performance of the semiconductor device.
  • the semiconductor device 10 includes a substrate 111, a first conductive layer 113, an ohmic contact layer 114, a second conductive layer 115, a first barrier layer 116, a third conductive layer 117, a fourth conductive layer 118, and a dielectric layer 119, and further includes The second barrier layer 120 and the third barrier layer 130 .
  • the bit line structure 100 is formed with the dielectric layer 119 .
  • an ohmic contact layer 114 is formed at the intersection of the first conductive layer 113 and the second conductive layer 115 .
  • the dielectric layer 119 is disposed on the fourth conductive layer 118
  • the fourth conductive layer 118 is disposed on the third conductive layer 117 .
  • the third conductive layer 117 is disposed on the first barrier layer 116
  • the first barrier layer 116 is disposed on the second conductive layer 115 .
  • the second conductive layer 115 is disposed on the first conductive layer 113
  • the ohmic contact layer 114 is formed at the intersection of the second conductive layer 115 and the first conductive layer 113 .
  • the second barrier layer 120 is disposed on the sidewall of the first conductive layer 113
  • the third barrier layer 130 is disposed on the sidewall of the ohmic contact layer 114
  • the second barrier layer 120 and the third barrier layer 130 are used for Metal precipitation in the ohmic contact layer 114 is prevented.
  • the second barrier layer 120 may be silicon nitride
  • the third barrier layer 130 may be titanium nitride or cobalt nitride.
  • the first conductive layer 113 is disposed on the substrate 111 , and the upper surface of the first conductive layer 113 is uneven.
  • the uneven shape is beneficial to increase the contact area between the first conductive layer 113 and the second conductive layer 115 , and is beneficial to reduce the resistance of the ohmic contact layer 114 .
  • the first conductive layer 113 is obtained after the first conductive material layer 112 is plasma-treated, and the first conductive material layer 112 is disposed on the substrate 111 .
  • the substrate 111 is, for example, a silicon substrate, and the first conductive material layer 112 is, for example, polysilicon doped with phosphorus ions.
  • the upper surface of the first conductive material layer 112 may be treated with argon plasma, so that the upper surface of the first conductive material 112 is formed into an uneven shape, so as to form the first conductive material.
  • Conductive layer 113 may be treated with argon plasma, so that the upper surface of the first conductive material 112 is formed into an uneven shape, so as to form the first conductive material.
  • the material of the second conductive layer 115 may be cobalt (Co) or titanium (Ti).
  • the first barrier layer 116 can be a nitride containing Co, such as cobalt nitride (CoN), and the material of the ohmic contact layer 114 is cobalt silicide (CoSi 2 ).
  • the first barrier layer 116 may be a Ti-containing nitride, such as titanium nitride (TiN), and the material of the ohmic contact layer 114 is TiSi 2 .
  • the material of the third conductive layer 117 may be a silicide containing tungsten, such as tungsten silicide (WSi), and the material of the fourth conductive layer 118 may be metal tungsten.
  • the dielectric layer 119 may be silicon nitride (Si 3 N 4 ).
  • the dielectric layer 119 and the ohmic contact layer 114 are formed simultaneously.
  • the dielectric layer 119 may be a silicon nitride layer formed on the fourth conductive layer 118 by a chemical vapor deposition process at a temperature of 600° C. ⁇ 650° C.
  • the bit line structure 100 further includes a fourth barrier layer 140 , a fifth barrier layer 150 and a sixth barrier layer 160 .
  • the fourth barrier layer 140 is formed on the sidewall of the second conductive layer 115 , the second conductive layer 115 may be titanium or cobalt, and the fourth barrier layer 140 may be titanium nitride or cobalt nitride.
  • the fifth barrier layer 150 is formed on the sidewall of the third conductive layer 117 . When the third conductive layer 117 is tungsten, the fifth barrier layer 150 is tungsten nitride.
  • the sixth barrier layer 160 is formed on the sidewall of the fourth conductive layer 118 . When the fourth conductive layer 118 is tungsten silicide, the sixth barrier layer 160 includes tungsten silicide doped with nitrogen ions.
  • the semiconductor device 10 provided in this embodiment provides the second barrier layer 120 , the third barrier layer 130 and the bit line sidewall protection layer 200 , and the second barrier layer 120 is formed on the second barrier layer of the initial bit line structure 110 .
  • a surface of the conductive layer 113 , the third barrier layer 130 is formed on the surface of the ohmic contact layer 114 of the initial bit line structure 110 , and the bit line sidewall protection layer 200 covers the surface of the bit line structure 100 .
  • the second barrier layer 120 , the third barrier layer 130 and the bit line sidewall protection layer 200 can prevent the metal in the ohmic contact layer 114 from being deposited.
  • the fourth barrier layer 140 , the fifth barrier layer 150 and the sixth barrier layer 160 can effectively prevent metal tungsten from precipitation. Therefore, the method for manufacturing the semiconductor device provided in this embodiment can effectively improve and improve the conductivity of the semiconductor device and improve the yield of the semiconductor device.

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Abstract

本申请提供一种半导体器件的制造方法及其半导体器件。该方法包括提供衬底；于衬底上形成第一导电材料层；对第一导电材料层进行等离子体处理，以形成第一导电层；于第一导电层上依次形成第二导电层、第一阻挡层、第三导电层和第四导电层；于第四导电层上形成介质层，同时，第一导电层与第二导电层交接处形成欧姆接触层；构成初始位线结构；对初始位线结构进行NH 3/N 2等离子体处理，以在第一导电层的侧壁形成第二阻挡层，在欧姆接触层的侧壁形成第三阻挡层，第二阻挡层和第三阻挡层用于防止欧姆接触层中的金属析出；形成位线侧壁保护层以覆盖位线结构的表面。本申请可以解决半导体器件的欧姆接触容易析出金属的问题，提高了半导体器件的导电性能。

Description

半导体器件的制造方法及其半导体器件
本申请要求于2021年4月15日提交中国专利局、申请号为202110406661.4、申请名称为“半导体器件的制造方法及其半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及但不限于一种半导体器件的制造方法及其半导体器件。
背景技术
欧姆接触工艺是制作半导体器件时经常使用到的一种制作工艺，其中，欧姆接触指的是半导体设备上具有线性并且对称的电流-电压特性曲线的区域。欧姆接触工艺的目的是降低半导体器件(例如集成电路)中金属与非金属之间的接触电阻，进而有效地提高半导体器件的导电性能。
在典型的欧姆接触工艺中，最常用的接触材料有TiSix(Ti为钛元素，Si为硅元素，x表示常数)、或CoSix(Co为钴元素)等，其中TiSix或CoSix是由Ti或Co在硅衬底上形成。但是传统的制备欧姆接触的制程工艺容易出现Ti或Co并没有完全转换为化合物，而是从金属和非金属之间析出的问题。如此，在半导体器件通电时，游离的Ti或Co就会导致半导体器件的金属层短路，使得半导体器件导电性能降低，进而影响半导体器件的良率。
因此，如何解决半导体器件在制备欧姆接触时容易发生金属析出并减小欧姆接触的电阻，进而保证半导体器件的性能和良率，依然是值得思考的。
发明内容
本申请实施例提供一种半导体器件的制造方法，包括：
提供衬底；
于所述衬底上形成第一导电材料层；
对所述第一导电材料层进行等离子体处理，以形成第一导电层，所述第一导电层上表面的表面积大于所述第一导电材料层上表面的表面积；
于所述第一导电层上依次形成第二导电层、第一阻挡层、第三导电层和第四导电层；
于所述第四导电层上形成介质层，同时，所述第一导电层与所述第二导电层交接处形成欧姆接触层；
去除部分所述介质层、部分所述第四导电层、部分所述第三导电层、部分所述第一阻挡层、部分所述第二导电层、部分所述欧姆接触层和部分所述第一导电层，剩余的所述第四导电层、所述第三导电层、所述第一阻挡层、所述第二导电层、所述欧姆接触层、所述第一导电层和所述介质层构成初始位线结构；
对所述初始位线结构进行NH 3/N 2等离子体处理，以在所述第一导电层的侧壁形成第二阻挡层，在所述欧姆接触层的侧壁形成第三阻挡层，所述第二阻挡层、所述第三阻挡层 和所述初始位线结构构成位线结构，其中，所述第二阻挡层和所述第三阻挡层用于防止所述欧姆接触层中的金属析出；
形成位线侧壁保护层，所述位线侧壁保护层覆盖所述位线结构的表面。
另一方面，本申请提供一种半导体器件，包括
衬底；
第一导电层，设置在所述衬底上，所述第一导电层的上表面为凹凸不平的形状；
第二导电层，设置在所述第一导电层上，所述第一导电层与所述第二导电层交接处形成有欧姆接触层；
第一阻挡层，设置在所述第二导电层上；
第三导电层，设置在所述第一阻挡层上；
第四导电层，设置在所述第三导电层上；
介质层，设置在所述第四导电层上；
第二阻挡层，设置在所述第一导电层的侧壁；
第三阻挡层，设置在所述欧姆接触层的侧壁；其中，所述第一导电层、所述第二导电层、所述第一阻挡层、所述第三导电层、所述第四导电层、所述第二阻挡层、所述第三阻挡层和所述介质层构成位线结构，所述第二阻挡层和所述第三阻挡层用于防止所述欧姆接触层中的金属析出；
位线侧壁保护层，所述位线侧壁保护层覆盖所述位线结构的表面。
附图说明
图1为本申请实施例一提供的半导体器件的制造方法的流程示意图。
图2为本申请实施例一中提供的半导体器件的部分示意图。
图3为本申请实施例一中提供的半导体器件的部分示意图。
图4为本申请实施例一中提供的半导体器件的部分示意图。
图5为本申请实施例一中提供的半导体器件的部分示意图。
图6为本申请实施例一中提供的初始位线结构的示意图。
图7为本申请实施例一中提供的位线结构的示意图。
图8为本申请实施例一和实施例二中提供的半导体器件的示意图。
附图标记说明
半导体器件      10
位线结构        100
初始位线结构    110
衬底            111
第一导电材料层  112
第一导电层      113
欧姆接触层      114
第二导电层      115
第一阻挡层      116
第三导电层      117
第四导电层      118
介质层          119
第二阻挡层      120
第三阻挡层      130
第四阻挡层      140
第五阻挡层      150
第六阻挡层      160
位线侧壁保护层  200
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
在半导体的制造中，欧姆接触工艺是常用的一种制造工艺，欧姆接触工艺的目的是降低半导体器件(例如集成电路)中金属与非金属之间的接触电阻，进而有效地提高半导体器件的导电性能。在典型的欧姆接触工艺中，最常用的接触材料有TiSix(Ti为钛元素，Si为硅元素，x表示常数)、或CoSix(Co为钴元素)等，其中TiSix或CoSix是由Ti或Co在硅衬底上形成。
但是传统的制备欧姆接触的制程工艺容易出现Ti或Co并没有完全转换为化合物，而是从金属和非金属之间析出的问题。如此，在半导体器件通电时，游离的Ti或Co就会导致半导体器件的金属层短路，使得半导体器件导电性能降低。随着大规模集成电路特征尺寸的不断缩减及其对器件性能要求的不断提高，传统的欧姆接触的制程工艺存在的金属析出问题已经严重影响到了半导体器件的良率。
基于此，本申请提供一种半导体器件的制造方法及其半导体器件，该半导体器件的制造方法为先提供衬底，再从衬底开始叠加形成第一导电层、欧姆接触层、第二导电层、第一阻挡层、第三导电层、第四导电层和介质层，再去除部分该第一导电层、部分该欧姆接触层、部分该第二导电层、部分该第一阻挡层、部分该第三导电层、部分该第四导电层和部分该介质层后形成初始位线结构。对该初始位线结构进行NH 3/N 2等离子处理后，得到的位线结构具有第二阻挡层和第三阻挡层。其中，该第二阻挡层形成于该第一导电层的侧壁，该第三阻挡层形成于该欧姆接触层的侧壁。当该欧姆接触层中存在未转换成化合物的金属时，该第二阻挡层和该第三阻挡层可以有效阻止未反应完全(未转换成化合物)的金属析出，从而解决传统欧姆接触工艺容易造成半导体器件性能降低、良率下降的问题。
本申请提供的半导体器件的制造方法应用于半导体制造设备，该半导体制造设备可以是集成的一个设备，可以执行如下提供的半导体器件的制造方法。该半导体制造设 备也可以是分离的多个设备，该多个设备分别执行如下提供的半导体器件的制造方法中的一个或多个步骤。
请参见图1，本申请实施例一提供一种半导体器件的制造方法，包括：
S101，提供衬底。
可选的，该衬底111为硅衬底。该衬底111的材料也可以根据实际需要选择，本申请不做限定。
S102，于该衬底上形成第一导电材料层。
图2所示为该衬底上形成该第一导电材料层112后的示意图，如图2所示，该第一导电材料层112可以是掺杂有磷离子的多晶硅。该磷离子也可以替换为其他非金属离子，例如硼离子。该第一导电材料层112可以选择离子注入的方法形成，例如在该衬底111上注入磷离子形成掺杂有磷离子的第一导电材料层112。
S103，对该第一导电材料层进行等离子体处理，以形成第一导电层，该第一导电层上表面的表面积大于该第一导电材料层上表面的表面积。
等离子体又称电浆，是在固态、液态和气态以外的第四大物质状态。气体在高温或强电磁场下会变成等离子体，此时气体中的原子会拥有比正常更多或更少的电子，从而形成阴离子或阳离子，即带负电荷或带正电荷的粒子。
由于等离子体含有许多载流子，因此等离子体能够导电，对该第一导电材料层112进行等离子体处理，即用等离子体对该第一导电材料层112进行处理，以形成该第一导电层113。
可选的，如图3所示，可以用氩等离子体(Ar)对该第一导电材料层112的上表面进行处理，以使该第一导电材料层112的上表面形成凹凸不平的形状。该凹凸不平的形状如图3所示的波纹形状，该凹凸不平的形状可以增大该第一导电层113与该第二导电层115的接触面积，进而减小最终形成的该欧姆接触层114的电阻。
除了减少该欧姆接触层114的电阻外，利用氩等离子体对该第一导电材料层112的上表面进行处理可以有效去除该第一导电材料层112的上表面的氧化物，减少了该第一导电层113与第二导电层115之间的断路现象，提高了该半导体器件的导电性能。
该氩等离子的参数可以根据实际需要选择，本申请不做限定。可选的，在利用氩等离子体对该第一导电材料层112的上表面进行处理时，处理时间可以在5秒至20秒，氩等离子体处理的能量可以在300瓦至1000瓦，氩等离子处理的温度可以为室温。氩等离子体处理的气体流量可以在20毫升每分(sccm)至200毫升每分(sccm)。
S104，于该第一导电层上依次形成第二导电层、第一阻挡层、第三导电层和第四导电层。
当该第一导电层113的材料为掺杂有磷离子的多晶硅时，可选的，该第二导电层115的材料可以为钴(Co)或钛(Ti)。
当该第二导电层115的材料为Co时，该第一阻挡层116可以为含Co的氮化物，例如氮化钴(CoN)。
当该第二导电层115的材料为Ti时，该第一阻挡层116可以为含Ti的氮化物，例如氮化钛(TiN)。
可选的，该第三导电层117的材料可以为含钨的硅化物，例如硅化钨(WSi)，该第四导电层118的材料可以为金属钨。
图4所示为依次形成第二导电层、第一阻挡层、第三导电层和第四导电层后的示意图。
S105，于该第四导电层上形成介质层，同时，该第一导电层与该第二导电层交接处形成欧姆接触层。
如图5所示，该介质层119也可以理解为绝缘层，该介质层119形成于该第四导电层118上，该介质层119用于将该第四导电层118与外界绝缘。可选的，该介质层119的材料可以为氮化硅。
可选的，可以在600℃～650℃条件下，采用化学气相沉积工艺于该第四导电层118上形成介质层119。该介质层119的厚度为80nm～120nm，采用化学气相沉积工艺可以减小形成介质层119的时间，减小生产成本。
由于介质层119的生成温度较高，为600℃～650℃，所以，当在该第四导电层118上形成该介质层119的同时，该第一导电层113与该第二导电层115交接处发生反应，形成了欧姆接触层114。该欧姆接触层114指的是具有线性并且对称的电流-电压特性曲线的区域，该欧姆接触层114可以降低该第一导电层113和该第二导电层115之间的接触电阻，进而有效提高该半导体器件的导电性能。
如图5所示，当该第二导电层115的材料为Ti时，该欧姆接触层114是由Ti和该第一导电层113中的硅反应形成的接触层，该欧姆接触层114包括硅化钛(TiSi 2)。当该第二导电层115的材料为Co时，该欧姆接触层114是由Co和该第一导电层113中的硅反应形成的接触层，该欧姆接触层114包括硅化钴(CoSi 2)。
该欧姆接触层114在形成时可能会有一部分的金属(Ti或Co)未反应，未反应的金属如果不加以隔绝，则在后续半导体器件制备中容易析出，进而导致半导体器件的短路。
S106，去除部分该介质层、部分该第四导电层、部分该第三导电层、部分该第一阻挡层、部分该第二导电层、部分该欧姆接触层和部分该第一导电层，剩余的该第四导电层、该第三导电层、该第一阻挡层、该第二导电层、该欧姆接触层和部分第一导电层构成初始位线结构。
如图6所示为该初始位线结构110，相比于图5所示的结构，该初始位线结构110去除了部分该介质层119、部分该第四导电层118、部分该第三导电层117、部分该第一阻挡层116、部分该第二导电层115、部分该欧姆接触层114和部分该第一导电层113。该初始位线结构110是在该衬底111上具有多个构成都相同的结构，此时多个结构中的欧姆接触层114都可能会析出金属，因此，需要对该多个结构中的欧姆接触层114进行处理。
S107，对该初始位线结构进行NH 3/N 2等离子体处理，以在该第一导电层的侧壁形成第二阻挡层120，在该欧姆接触层的侧壁形成第三阻挡层130，该第二阻挡层120、该第三阻挡层130和该初始位线结构构成位线结构，其中，该第二阻挡层120和该第三阻挡层130用于防止该欧姆接触层114中的金属析出。
如图7所示为具有该第二阻挡层120和该第三阻挡层130的位线结构100的示意图。
当该第一导电层113的材料为掺杂有磷离子的多晶硅，该第二导电层115的材料为Ti时，该欧姆接触层114的材料为TiSi 2，此时该欧姆接触层114中可能含有未反应的Ti。对该初始位线结构110进行NH 3/N 2等离子体处理后，在该第一导电层113的侧壁可以形成氮化硅作为该第二阻挡层120，在该欧姆接触层114的侧壁形成TiN作为该第三阻挡层130。该第二阻挡层120和该第三阻挡层130均可以阻挡该欧姆接触层114中未反应的Ti析出。
当该第一导电层113的材料为掺杂有磷离子的多晶硅，该第二导电层115的材料为Co时，该欧姆接触层114的材料为CoSi 2，此时该欧姆接触层114中可能含有未反应的Co。对该初始位线结构110进行NH 3/N 2等离子体处理后，在该第一导电层113的侧壁可以形成氮化硅作为该第二阻挡层120，在该欧姆接触层114的侧壁形成CoN作为该第三阻挡层130。该第二阻挡层120和该第三阻挡层130均可以阻挡该欧姆接触层114中未反应的Co析出。
可选的，NH 3/N 2等离子体也可以替换为其他可以进行氮化处理的等离子体，具体可以根据实际需要选择，本申请不做限定。
可选的，在利用NH 3/N 2等离子体进行处理时，NH 3等离子体的气体流量可以在300毫升每分(sccm)至2000毫升每分(sccm)。
S108，形成位线侧壁保护层，该位线侧壁保护层覆盖该位线结构的表面。
图8所示为该位线侧壁保护层覆盖该位线结构的表面的示意图(该第二阻挡层和该第三阻挡层在该位线侧壁保护层的内侧，该位线侧壁保护层在最外侧)，如图8所示，该位线侧壁保护层200覆盖该位线结构100的表面。
该位线侧壁保护层200的材料可以为氮化硅(Si 3N 4)。
可选的，可以在600℃～650℃条件下，采用原子层沉积工艺形成该位线侧壁保护层200。该位线侧壁保护层200的厚度为10nm～20nm,利用原子层沉积工艺形成该位线侧壁保护层20，可以很好的控制位线侧壁保护层200在各个位置的厚度，保证半导体器件的性能。当然，也可以根据实际需要选择其他的方式形成该位线侧壁保护层200，本申请不做限制。
该位线侧壁保护层200的作用和该第二阻挡层120、第三阻挡层130相似，该位线侧壁保护层200可以有效防止该欧姆接触层114中析出的金属游离出该位线结构100，从而保护该位线结构100在使用时不会被短路，有效得提高了该半导体器件的导电性能和良率。
本实施例提供的该半导体器件的制造方法提供了第二阻挡层120、第三阻挡层130和位线侧壁保护层200，该第二阻挡层120形成于该初始位线结构100的第一导电层113的侧壁，该第三阻挡层130形成于该初始位线结构100欧姆接触层114的侧壁，该位线侧壁保护层200覆盖该位线结构100的表面。当该欧姆接触层114中有金属析出时，该第二阻挡层120、该第三阻挡层130和该位线侧壁保护层200都可以阻挡该欧姆接触层114中的金属被析出。因此，本实施例提供的该半导体器件的制造方法可以有效提高该半导体器件的良率。
除此之外，本实施例提供的该半导体器件的制造方法在形成该介质层110的同时，该第一导电层113和该第二导电层115的交接处形成有该欧姆接触层114。其中，该第一导电层113的上表面为凹凸不平的形状，如此设置，可以增大该第一导电层113和该第二导电层115的接触面积，进而减小最终形成的该欧姆接触层114的电阻。
可选的，实施例一中步骤S107包括：
对该初始位线结构110进行NH 3/N 2等离子体处理，以在该第一导电层113的侧壁形成第二阻挡层120，在该欧姆接触层114的侧壁形成第三阻挡层130，在该第二导电层115的侧壁形成第四阻挡层140，在该第三导电层117的侧壁形成第五阻挡层150，在第四导电层118的侧壁形成第六阻挡层160。此时，该第二阻挡层120、该第三阻挡层130、该第四阻挡层140、该第五阻挡层150、该第六阻挡层160和该初始位线结构110构成该位线结构100。
如实施例一中关于步骤S207的相关描述，该第二阻挡层120的材料可以为氮化硅，该第三阻挡层130的材料可以为TiN或CoN。
该第四阻挡层140和该第一阻挡层116的材料相同。当该第二导电层115为Ti时，该第四阻挡层140的材料为TiN。当该第二导电层115为Co时，该第四阻挡层140的材料为CoN。
该第五阻挡层150形成于该第三导电层117的侧壁，该第三导电层117为硅化钨时，该第五阻挡层150包含掺杂有氮离子的硅化钨。该第四导电层118为金属钨时，该第六阻挡层160为氮化钨。该第五阻挡层150和该第六阻挡层160可以有效防止金属钨被析出，从而提高该半导体器件的导电性能。
可选的，NH 3/N 2等离子体也可以替换为其他可以进行氮化处理的等离子体，具体可以根据实际需要选择，本申请不做限定。
请参见图8，本申请实施例二提供一种半导体器件10，该半导体器件10包括衬底111、位线结构100和位线侧壁保护层200，该位线侧壁保护层200覆盖该位线结构的表面。可选的，该位线侧壁保护层200是在600℃～650℃条件下，采用原子层沉积工艺形成的保护层。该位线侧壁保护层200的材料可以为氮化硅(Si 3N 4)。相比于其他工艺，采用原子层沉积工艺可以很好的控制位线侧壁保护层200在各个位置的厚度，保证半导体器件的性能。
该半导体器件10包括衬底111、第一导电层113、欧姆接触层114、第二导电层115、第一阻挡层116、第三导电层117、第四导电层118和介质层119，还包括第二阻挡层120和第三阻挡层130。其中，该第一导电层113、该第二导电层115、该第一阻挡层120、该第三导电层117、该第四导电层118、该第二阻挡层120、该第三阻挡层130和该介质层119构成该位线结构100。除此之外，该第一导电层113与该第二导电层115交接处形成有欧姆接触层114。
具体的，该介质层119设置在该第四导电层118上，该第四导电层118设置在该第三导电层117上。该第三导电层117设置在该第一阻挡层116上，该第一阻挡层116设置在该第二导电层115上。该第二导电层115设置在该第一导电层113上，且该第二导电层115和该第一导电层113的交接处形成有该欧姆接触层114。
该第二阻挡层120设置在该第一导电层113的侧壁，该第三阻挡层130设置在该欧姆接触层114的侧壁，该第二阻挡层120和该第三阻挡层130用于防止该欧姆接触层114中的金属析出。如实施例一中的相关描述，该第二阻挡层120可以是氮化硅，该第三阻挡层130可以是氮化钛或氮化钴。当该欧姆接触层114中有未反应的金属时，该第二阻挡层120和该第三阻挡层130可以有效阻挡该欧姆接触层114中未反应完全的金属析出。
该第一导电层113设置在该衬底111上，该第一导电层113的上表面为凹凸不平的形状。该凹凸不平的形状有利于增加该第一导电层113和该第二导电层115之间的接触面积，有利于减小该欧姆接触层114的电阻。在该半导体器件10的制作过程中，该第一导电层113是第一导电材料层112被等离子体处理后得到的，该第一导电材料层112设置在该衬底111上。该衬底111例如硅衬底，该第一导电材料层112例如掺杂有磷离子的多晶硅。在形成该第一导电层113时，可以用氩等离子体对该第一导电材料层112的上表面进行处理，使得该第一导电材料112的上表面形成凹凸不平的形状，以形成该第一导电层113。
当该第一导电层113的材料为掺杂有磷离子的多晶硅时，可选的，该第二导电层115的材料可以为钴(Co)或钛(Ti)。当该第二导电层115的材料为Co时，该第一阻挡层116可以为含Co的氮化物，例如氮化钴(CoN)，该欧姆接触层114的材料为硅化钴(CoSi 2)。当该第二导电层115的材料为Ti时，该第一阻挡层116可以为含Ti的氮化物，例如氮化钛(TiN)，该欧姆接触层114的材料为TiSi 2。
可选的，该第三导电层117的材料可以为含钨的硅化物，例如硅化钨(WSi)，该第四导电层118的材料可以为金属钨。
该介质层119可以为氮化硅(Si 3N 4)，该介质层119和该欧姆接触层114同时形成。可选的，该介质层119可以是在600℃～650℃条件下，采用化学气相沉积工艺于该第四导电层118上形成的氮化硅层。
进一步的，如图8所示，该位线结构100还包括第四阻挡层140、第五阻挡层150和第六阻挡层160。该第四阻挡层140形成于该第二导电层115的侧壁，该第二导电层115可以是钛或钴，则该第四阻挡层140可以是氮化钛或氮化钴。该第五阻挡层150形成于该第三导电层117的侧壁，该第三导电层117为钨时，该第五阻挡层150为氮化钨。该第六阻挡层160形成于该第四导电层118的侧壁，当该第四导电层118为硅化钨时，该第六阻挡层160包括掺杂有氮离子的硅化钨。
本实施例提供的该半导体器件10提供了该第二阻挡层120、该第三阻挡层130和该位线侧壁保护层200，该第二阻挡层120形成于该初始位线结构110的第一导电层113的表面，该第三阻挡层130形成于该初始位线结构110的欧姆接触层114的表面，该位线侧壁保护层200覆盖该位线结构100的表面。当该欧姆接触层114中有金属析出时，该第二阻挡层120、该第三阻挡层130和该位线侧壁保护层200都可以阻挡该欧姆接触层114中的金属被析出。除此之外，该第四阻挡层140、该第五阻挡层150和该第六阻挡层160可以有效防止金属钨析出。因此，本实施例提供的该半导体器件的制造方法可以有效改善、提高该半导体器件的导电性，提高该半导体器件的良率。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
以上仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (15)

  1. 一种半导体器件的制造方法，包括：
    提供衬底；
    于所述衬底上形成第一导电材料层；
    对所述第一导电材料层进行等离子体处理，以形成第一导电层，所述第一导电层上表面的表面积大于所述第一导电材料层上表面的表面积；
    于所述第一导电层上依次形成第二导电层、第一阻挡层、第三导电层和第四导电层；
    于所述第四导电层上形成介质层，同时，所述第一导电层与所述第二导电层交接处形成欧姆接触层；
    去除部分所述介质层、部分所述第四导电层、部分所述第三导电层、部分所述第一阻挡层、部分所述第二导电层、部分所述欧姆接触层和部分所述第一导电层，剩余的所述第四导电层、所述第三导电层、所述第一阻挡层、所述第二导电层、所述欧姆接触层、所述第一导电层和所述介质层构成初始位线结构；
    对所述初始位线结构进行NH 3/N 2等离子体处理，以在所述第一导电层的侧壁形成第二阻挡层，在所述欧姆接触层的侧壁形成第三阻挡层，所述第二阻挡层、所述第三阻挡层和所述初始位线结构构成位线结构，其中，所述第二阻挡层和所述第三阻挡层用于防止所述欧姆接触层中的金属析出；
    形成位线侧壁保护层，所述位线侧壁保护层覆盖所述位线结构的表面。
  2. 根据权利要求1所述的半导体器件的制造方法，其中，所述对所述初始位线结构进行NH3/N2等离子体处理，以形成位线结构包括：
    对所述初始位线结构进行NH 3/N 2等离子体处理，以在所述第一导电层的侧壁形成第二阻挡层，在所述欧姆接触层的侧壁形成第三阻挡层，在所述第二导电层的侧壁形成第四阻挡层，在所述第三导电层的侧壁形成第五阻挡层，在第四导电层的侧壁形成第六阻挡层；
    其中，所述第二阻挡层、所述第三阻挡层、所述第四阻挡层、所述第五阻挡层、所述第六阻挡层和所述初始位线结构构成所述位线结构。
  3. 根据权利要求1所述的半导体器件的制造方法，其中，所述对所述第一导电材料层进行等离子体处理，以形成第一导电层包括：
    用氩等离子体对所述第一导电材料层的上表面进行处理，以使所述第一导电材料层的上表面形成凹凸不平的形状，以形成所述第一导电层。
  4. 根据权利要求1所述的半导体器件的制造方法，其中，所述于所述第四导电上形成介质层包括：
    在600℃～650℃条件下，采用化学气相沉积工艺于所述第四导电层上形成介质层。
  5. 根据权利要求1所述的半导体器件的制造方法，其中，所述形成位线侧壁保护层包括：
    在600℃～650℃条件下，采用原子层沉积工艺形成所述位线侧壁保护层。
  6. 根据权利要求1所述的半导体器件的制造方法，其中，形成所述第一导电材料层的材料为掺杂有磷离子的多晶硅。
  7. 根据权利要求6所述的半导体器件的制造方法，其中，形成所述第二导电层的材料为钴或钛，形成所述介质层的材料为氮化硅。
  8. 根据权利要求7所述的半导体器件的制造方法，其中，形成所述欧姆接触层的材料为硅化钴或硅化钛。
  9. 一种半导体器件，包括：
    衬底；
    第一导电层，设置在所述衬底上，所述第一导电层的上表面为凹凸不平的形状；
    第二导电层，设置在所述第一导电层上，所述第一导电层与所述第二导电层交接处形成有欧姆接触层；
    第一阻挡层，设置在所述第二导电层上；
    第三导电层，设置在所述第一阻挡层上；
    第四导电层，设置在所述第三导电层上；
    介质层，设置在所述第四导电层上；
    第二阻挡层，设置在所述第一导电层的侧壁；
    第三阻挡层，设置在所述欧姆接触层的侧壁；其中，所述第一导电层、所述第二导电层、所述第一阻挡层、所述第三导电层、所述第四导电层、所述第二阻挡层、所述第三阻挡层和所述介质层构成位线结构，所述第二阻挡层和所述第三阻挡层用于防止所述欧姆接触层中的金属析出；
    位线侧壁保护层，所述位线侧壁保护层覆盖所述位线结构的表面。
  10. 根据权利要求9所述的半导体器件，其中，所述位线结构还包括：
    第四阻挡层，形成于所述第二导电层的侧壁；
    第五阻挡层，形成于所述第三导电层的侧壁；
    第六阻挡层，形成于所述第四导电层的侧壁。
  11. 根据权利要求9所述的半导体器件，其中，所述介质层是在600℃～650℃条件下，采用化学气相沉积工艺于所述第四导电层上形成的介质层。
  12. 根据权利要求9所述的半导体器件，其中，所述位线侧壁保护层是在600℃～650℃条件下，采用原子层沉积工艺形成的位线侧壁保护层。
  13. 根据权利要求9所述的半导体器件，其中，所述第一导电层的材料为掺杂有磷离子的多晶硅。
  14. 根据权利要求13所述的半导体器件，其中，所述第二导电材料为钴或钛，所述介质层的材料为氮化硅。
  15. 根据权利要求14所述的半导体器件，其中，所述欧姆接触层的材料为硅化钴或硅化钛。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103578A (zh) * 2013-04-08 2014-10-15 爱思开海力士有限公司 具有气隙的半导体器件及其制造方法
CN104103577A (zh) * 2013-04-12 2014-10-15 爱思开海力士有限公司 具有气隙的半导体器件及其制造方法
US20150014759A1 (en) * 2013-07-12 2015-01-15 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
CN112652570A (zh) * 2019-10-11 2021-04-13 长鑫存储技术有限公司 接触结构、半导体器件结构及其制备方法
CN113130636A (zh) * 2021-04-15 2021-07-16 长鑫存储技术有限公司 半导体器件的制造方法及其半导体器件

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5930106A (en) * 1996-07-11 1999-07-27 Micron Technology, Inc. DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films
TW377461B (en) * 1998-06-19 1999-12-21 Promos Technologies Inc Method of manufacturing gates
KR100295062B1 (ko) * 1999-08-17 2001-07-12 윤종용 게이트 산화막의 손상을 회복시키는 반도체장치의 게이트 제조방법
US6689673B1 (en) * 2000-05-17 2004-02-10 United Microelectronics Corp. Method for forming a gate with metal silicide
JP2002093743A (ja) * 2000-09-11 2002-03-29 Oki Electric Ind Co Ltd 半導体装置の製造方法
KR20090032893A (ko) * 2007-09-28 2009-04-01 주식회사 하이닉스반도체 반도체 소자 형성 방법
KR101661306B1 (ko) * 2010-02-23 2016-09-30 삼성전자 주식회사 반도체 소자 및 그 제조방법
US8461687B2 (en) * 2010-04-06 2013-06-11 Samsung Electronics Co., Ltd. Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same
JP2012156451A (ja) * 2011-01-28 2012-08-16 Elpida Memory Inc 半導体装置及びその製造方法
KR101932229B1 (ko) * 2012-08-28 2019-03-21 에스케이하이닉스 주식회사 매립비트라인을 구비한 반도체 장치 및 그 제조방법
KR20160050431A (ko) * 2014-10-29 2016-05-11 삼성전자주식회사 Ｍｉｓ 접합을 가지는 메모리 소자와 그 제조방법
US9576908B1 (en) * 2015-09-10 2017-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure, fabricating method thereof, and semiconductor device using the same
US20230290639A1 (en) * 2020-07-29 2023-09-14 Lam Research Corporation Low resistance gate oxide metallization liner
JP2023507038A (ja) * 2020-08-14 2023-02-20 チャンシン メモリー テクノロジーズ インコーポレイテッド 半導体構造及びその製造方法
TWI806330B (zh) * 2022-01-04 2023-06-21 華邦電子股份有限公司 半導體記憶結構
KR20230123345A (ko) * 2022-02-16 2023-08-23 삼성전자주식회사 반도체 메모리 소자
CN115148705A (zh) * 2022-06-29 2022-10-04 长鑫存储技术有限公司 半导体结构及其制备方法
CN117373999A (zh) * 2022-06-30 2024-01-09 长鑫存储技术有限公司 半导体结构的制备方法
US20240023307A1 (en) * 2022-07-13 2024-01-18 Nanya Technology Corporation Semiconductor device with etched landing pad surface

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103578A (zh) * 2013-04-08 2014-10-15 爱思开海力士有限公司 具有气隙的半导体器件及其制造方法
CN104103577A (zh) * 2013-04-12 2014-10-15 爱思开海力士有限公司 具有气隙的半导体器件及其制造方法
US20150014759A1 (en) * 2013-07-12 2015-01-15 SK Hynix Inc. Semiconductor device with air gap and method for fabricating the same
CN112652570A (zh) * 2019-10-11 2021-04-13 长鑫存储技术有限公司 接触结构、半导体器件结构及其制备方法
CN113130636A (zh) * 2021-04-15 2021-07-16 长鑫存储技术有限公司 半导体器件的制造方法及其半导体器件

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