WO2000022659A1 - Method of forming cobalt-disilicide contacts using a cobalt-carbon alloy thin film - Google Patents

Method of forming cobalt-disilicide contacts using a cobalt-carbon alloy thin film Download PDF

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Publication number
WO2000022659A1
WO2000022659A1 PCT/KR1999/000617 KR9900617W WO0022659A1 WO 2000022659 A1 WO2000022659 A1 WO 2000022659A1 KR 9900617 W KR9900617 W KR 9900617W WO 0022659 A1 WO0022659 A1 WO 0022659A1
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cobalt
layer
carbon
thin film
alloy thin
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PCT/KR1999/000617
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French (fr)
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Byung-Tae Ahn
Hwa-Sung Rhee
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Genitech Co., Ltd.
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Publication of WO2000022659A1 publication Critical patent/WO2000022659A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B33/00—Silicon; Compounds thereof
    • C01B33/06—Metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Definitions

  • the present invention relates generally to the contact formation of highly integrated logic and memory devices such as 1 Giga-bit DRAMs. More particularly, the present invention relates to a method for forming single crystal cobalt silicide contacts applicable to both polycide structure and salicide (self-aligned silicide) processes.
  • FIGS. 6 A to 6E The salicide technology reported by Dass is illustrated in FIGS. 6 A to 6E.
  • an MOS transistor with source/drain regions and a polysilicon gate electrode 3 is first formed on a silicon substrate 1, and then a titanium layer 6 having a thickness of 20 A is deposited on the silicon substrate 1 kept at room temperature by sputtering or vacuum evaporation.
  • FIG. 6A shows the structure of the MOS transistor having spacers comprised of silicon oxide or silicon nitride and FIG. 6B shows the titanium layer 6 used as an interlayer.
  • a cobalt layer 4 having a thickness of 150 A is deposited onto the titanium layer 6 using sputtering or vacuum evaporation.
  • a TiN protection layer 5 is then formed over the cobalt layer 4 at a temperature in the range of 200-400°C using sputtering or reactive evaporation to protect the underlying layer from any oxidation or agglomeration during subsequent heat treatments. The resultant is shown in FIG. 6C.
  • the substrate 1 is annealed at a temperature of 700°C or more to form a single crystal CoSi 2 layer 7 as shown in FIG. 6D.
  • the TiN layer 5 as well as the unreacted cobalt in cobalt layer 4 and the titanium layer 6 are removed by subsequent etching processes.
  • the substrate is then subjected to a second high temperature annealing (over 800°C) to form a final silicide layer with low contact resistance and low resistivity as shown in FIG. 6E.
  • the sheet resistance of a silicide thin layer formed by the above prior art salicide methods is about 5-10 ⁇ /Q
  • the prior art methods have disadvantages of complicated processes and high-cost manufacturing equipment because both the interlayer and the protection layer are consecutively deposited in a same reactor using sputtering or vacuum evaporation at a temperature in the range of room temperature to 400°C.
  • the prior art methods require a protection layer for preventing the oxidation and agglomeration of the underlying metal layer and can not guarantee uniform thin films because of poor step coverage in a highly integrated device. If a commonly-used titanium layer 6 is employed for an interlayer, pinholes occur at the edges of the oxide structures (field oxide and space oxide) during the annealing process, causing problems including leakage current, instability in electrical properties, and lack of reproducibility.
  • (110) or (221) CoSi 2 layers including the lattice matching (100) CoSi 2 layer are generally formed on a (100) silicon substrate. Because the lattice matching (100) layer has a higher interface energy than those of other layers, it is very difficult to form a single crystal CoSi 2 layer having a uniform interface structure. In order to obtain a uniform interface structure, it is desirable to form a single crystal (100) layer having a close lattice match to a (100) silicon substrate. For this purpose, the silicon substrate surface should be kept clean and the diffusion of cobalt atoms into the silicon substrate should be prevented.
  • a method of forming a CoSi 2 layer by depositing a cobalt layer on a silicon substrate uses a cobalt-carbon alloy thin film without using an interlayer such as a titanium layer.
  • the cobalt-carbon alloy thin film is formed using chemical vapor deposition, vacuum evaporation, and sputtering.
  • the cobalt-carbon alloy thin film prevents the diffusion of cobalt atoms into the silicon substrate to facilitate the formation of a single crystal CoSi 2 layer.
  • the deposited cobalt-carbon alloy thin film is converted into a (100) single crystal or (100) epitaxial CoSi 2 layer by reaction of the alloy thin film with the silicon substrate during heat treatments.
  • the above described method of the present invention provides process simplicity and lower contact resistance by forming only a cobalt-carbon alloy thin film in a reaction chamber and then performing a heat treatment.
  • FIG. 1 shows x-ray diffraction patterns to indicate the amorphous state of a cobalt-carbon alloy thin film formed on a silicon substrate at a temperature of 350 "C using cyclopentadienylcobaltdicarbonyl [C 5 H 5 Co(CO) 2 ], a cobalt metal-organic source;
  • FIG. 2 is an AES (Auger Electron Spectroscopy) graph characterizing the composition distribution of the cobalt-carbon alloy thin film of FIG. 1;
  • FIG. 3 is an XRD (X-ray diffraction) graph of a silicon surface on which a cobalt layer and a titanium protection layer are consecutively formed and then heat- treated at 800 °C ;
  • FIG. 4 is an XRD graph of source/drain regions of a silicon substrate surface on which a cobalt layer is formed without using a titanium protection layer and then heat-treated at a temperature in the range of 600 ° C ⁇ 800 °C ;
  • FIG. 5 is an AES graph characterizing the composition distribution of the silicon substrate surface on which a cobalt layer is formed without using a titanium protection layer and then heat-treated at a temperature of 800 °C ;
  • FIGS. 6 A through 6E illustrate, in cross section, process steps in the formation of a single crystal cobalt disilicide at the source/drain regions and polysilicon gate of an MOS transistor by reaction of silicon and metal using sputtering or vacuum evaporation according to a prior art method;
  • FIGS. 7A through 7D illustrate, in cross section, process steps in the formation of a CoSi 2 using a cobalt-carbon alloy thin film according to the present invention.
  • the direct CoSi 2 contact formation to the source/drain regions and polysilicon gate structure can be simplified compared with the prior art process shown in FIG. 6A to FIG. 6E.
  • FIGS. 7A through 7D illustrate, in cross section, process steps in the formation of a CoSi 2 using a cobalt-carbon alloy thin film according to the present invention.
  • the MOS transistor is fabricated using a cobalt-carbon alloy thin film 8
  • the process according to the present invention does not require the deposition of the interlayer which is necessary for the prior art method.
  • an MOS transistor, with source/drain regions (not shown) and a polysilicon gate electrode 3 is first formed on a silicon substrate 1.
  • a cobalt-carbon alloy thin film 8 is deposited by chemical vapor deposition using a cobalt metal-organic source such as cyclopentadienylcobaltdicarbonyl [C 5 H 5 Co(CO) 2 ] or bis(cyclopentadienyl)cobalt [Co(C 5 H 5 ) 2 ].
  • a cobalt metal-organic source such as cyclopentadienylcobaltdicarbonyl [C 5 H 5 Co(CO) 2 ] or bis(cyclopentadienyl)cobalt [Co(C 5 H 5 ) 2 ].
  • the cobalt metal-organic source stored in a reservoir of -10 ° C ⁇ 50 ° C is supplied directly in a gas phase or using a carrier gas such as hydrogen, nitrogen or argon to the silicon substrate 1 kept at a temperature in the range of 300 ° C ⁇ 400 ° C .
  • the deposited cobalt-carbon alloy thin film 8 is then subjected to a heat treatment (700°C or more) to form a (100) epitaxial CoSi 2 layer 7 on the (100) silicon substrate 1 and a polycrystalline CoSi 2 layer 7 on the polysilicon gate electrode 3, respectively, by reaction of cobalt in the cobalt-carbon alloy thin film 8 with silicon, while the cobalt over the silicon oxide 2 does not react with the oxide as shown in FIG. 7C.
  • the cobalt-carbon alloy thin film by a vacuum evaporator, it can be deposited on a substrate at room temperature by co-evaporating carbon and cobalt.
  • the carbon and cobalt respectively contained in tungsten and molybdenum boats or effusion cells are evaporated at a temperature in the range of 1000 °C — 1500 ° C and below a pressure of 10 "7 Torr.
  • the cobalt-carbon alloy thin film In the case of depositing the cobalt-carbon alloy thin film by sputtering, it can be deposited on the silicon substrate at room temperature by sputtering an alloy target having a cobalt to carbon ratio of 1 : 1 or 2: 1.
  • argon gas is supplied to the sputtering chamber at a flow rate in the range of 1 — lOsccm to maintain the chamber pressure in the range of 1 ⁇ lOmTorr, and the silicon substrate is maintained in the temperature range of room temperature to 350 ° C .
  • An amorphous cobalt-carbon alloy thin film can be deposited at room temperature in a similar manner to the above by co-sputtering separate cobalt and carbon targets instead of sputtering the cobalt-carbon alloy target.
  • the deposited cobalt-carbon alloy thin film is then subjected to the same heat treatment as for that formed by the above chemical vapor deposition. Therefore, a (100) epitaxial CoSi 2 layer is formed on the (100) silicon substrate while a polycrystalline CoSi 2 layer is formed on the polysilicon gate electrode, by reaction of cobalt in the cobalt-carbon alloy thin film with silicon. The cobalt over the silicon oxide does not react with the oxide.
  • a silicon substrate having an MOS transistor comprised of source/drain regions and a polysilicon gate electrode is maintained at a temperature of 350 °C in a reactor.
  • a cobalt-carbon alloy thin film is deposited by chemical vapor deposition using a cobalt metal-organic source, bis(cyclopentadienyl)cobalt [Co(C 5 H 5 ) 2 ].
  • the cobalt metal-organic source stored in a reservoir of 35 ° C is supplied to the reactor using a hydrogen carrier gas of 50sccm flow rate.
  • the deposition pressure is in the range of 10 ⁇ 500mTorr and the film deposited in this pressure range typically has 50:50 atomic fraction ratio of cobalt to carbon.
  • the resultant is then subjected to rapid thermal annealing at a temperature of 800 °C for 5 minutes to form a CoSi 2 layer.
  • the cobalt metal-organic source has a vapor pressure sufficiently high to be transferred to the reactor in a gas phase without using a carrier gas such as hydrogen even though the reservoir is maintained at room temperature.
  • a carrier gas such as hydrogen
  • a cobalt-carbon alloy thin film can be formed on the silicon substrate at a deposition rate of 500 A /min.
  • Example 2 The same as in Example 1 except the cobalt metal-organic source is cyclopentadienylcobaltdicarbonyl [C 5 H 5 Co(CO) 2 ].
  • the flow rate of transferred [C 5 H 5 Co(CO) 2 ] is in the range of 5 ⁇ 15sccm, and the deposition is in the range of 400 ⁇ 500mTorr.
  • the deposited cobalt-carbon alloy thin film is subjected to rapid thermal annealing at a temperature of 800 ° C for 5 minutes to form a CoSi 2 layer.
  • the deposited cobalt-carbon alloy thin film is comprised of 50% cobalt and 50% carbon, and the XRD analysis of the thin film is shown in FIG. 1.
  • the broad and smooth diffraction curve implies that the deposited cobalt- carbon alloy thin film is amorphous.
  • FIG. 2 is an AES (Auger Electron Spectroscopy) graph characterizing the composition distribution of the cobalt-carbon alloy thin film of FIG. 1. From the FIG. 2, it is found that the cobalt to carbon ratio in the cobalt-carbon alloy thin film deposited at a temperature of 350 ° C is about 1 :1. [Example 3]
  • a titanium layer is deposited as a protection layer.
  • the resultant is then subjected to rapid thermal annealing at a temperature of 800 ° C and in a nitrogen ambient for 5 minutes to form a CoSi 2 layer.
  • the XRD pattern of the CoSi 2 layer is shown in FIG. 3.
  • the resultant is then subjected to rapid thermal annealing at temperatures of 600 ° C, 700 °C, and 800 °C without previously forming a protection layer, and then investigated by XRD analysis.
  • the XRD analysis is shown in FIG. 4. Referring to FIG. 4, it is found that single crystal CoSi 2 layers are formed at a temperature of 700 ° C or more.
  • the (200) diffraction peak of an epitaxial CoSi 2 layer appears together with the (200) diffraction peak of the silicon substrate. This indicates that a (100) epitaxial CoSi 2 layer is formed on the (100) silicon substrate after the thermal annealing. Referring to FIG. 4, it is found that an epitaxial CoSi 2 layer is formed at a temperature of 700 °C or more.
  • the cobalt on the silicon oxide (SiO 2 ) does not react with the silicon oxide, and the remaining unreacted cobalt is removed by a wet etchant such as NH 4 OH+H 2 O 2 , HNO 3 +HO 2 , or H 2 SO 4 +H 2 O 2 .
  • the cobalt silicide formed by the above method has a resistivity in the range of 16 ⁇ 20 ⁇ ⁇ • cm and has a sheet resistance in the range of 5 ⁇ 10 ⁇ / ⁇ similar to that of cobalt silicide formed by sputtering.
  • a cobalt-carbon alloy thin film is deposited using a cobalt metal-organic source, cyclopentadienylcobaltdicarbonyl [C 5 H 5 Co(CO) 2 ] on a silicon substrate, and then subjected to rapid thermal annealing at a temperature of 800 ° C and in nitrogen ambient for 5 minutes to form a CoSi 2 layer.
  • the depth profile of the components of resultant CoSi 2 layer is investigated by AES analysis and shown in FIG. 5.
  • the y-axis represents atomic fraction of the respective CoSi 2 layer components.
  • the cobalt in the cobalt-carbon alloy thin film diffuses into the silicon substrate and the carbon prevents the excessive diffusion of cobalt to facilitate the formation of an epitaxial CoSi 2 layer.
  • the carbon suppresses the diffusion of oxygen, the oxidation of cobalt frequently seen in the annealing process is also suppressed and the amount of oxygen in the cobalt-carbon alloy thin film becomes small. That is, the cobalt-carbon alloy thin film of the present invention plays an important role in the suppression of both cobalt diffusion into the silicon substrate and oxidation of cobalt.
  • the CoSi 2 contact formation process is simplified because it does not requires deposition steps of interlayers and a TiN protection layer, and their subsequent heat treatments.
  • an epitaxial CoSi 2 layer with low resistivity and high reproducibility can be formed by the deposition of a cobalt-carbon alloy thin film and its subsequent heat treatment.
  • the chemical vapor deposited CoSi 2 layer has enhanced step coverage and uniform interface characteristics suitable for the interconnection process of an ultra fine contact structure.

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Abstract

A method of forming cobalt-disilicide contacts on source/drain regions and a polysilicon gate electrode of an MOS transistor using a cobalt-carbon alloy thin film. The method of the present invention comprises the steps of (a) forming an MOS transistor on a silicon substrate, with source/drain regions and a polysilicon gate electrode of the MOS transistor; (b) depositing a carbon-containing cobalt layer overlying the resultant of the (a) step; and (c) annealing the carbon-containing cobalt layer to form an epitaxial CoSi2 layer over the source/drain regions and a CoSi2 single crystal layer over the polysilicon gate electrode, respectively. According to the present invention, the CoSi2 contact formation process is simplified because it does not require deposition steps of interlayers and a TiN protection layer, and their subsequent heat treatments. In addition, an epitaxial CoSi2 layer with low resistivity and high reproducibility can be formed by the deposition of a cobalt-carbon alloy thin film and its subsequent heat treatment. The chemical vapor deposited CoSi2 layer has enhanced step coverage and uniform interface characteristics suitable for the interconnection process of an ultra fine contact structure.

Description

METHOD OF FORMING COBALT-DISILICIDE CONTACTS USING A COBALT-CARBON ALLOY THIN FILM
TECHNICAL FIELD
The present invention relates generally to the contact formation of highly integrated logic and memory devices such as 1 Giga-bit DRAMs. More particularly, the present invention relates to a method for forming single crystal cobalt silicide contacts applicable to both polycide structure and salicide (self-aligned silicide) processes.
BACKGROUND ART
It is well known that there are many technical difficulties in forming contacts of logic devices with higher-speed performance, and memory devices whose integration density is higher than that of 1 Giga-bit DRAMs. Examples of prior art salicide processes for reducing resistance of both source/drain and gate electrode in a highly integrated semiconductor device are disclosed in Korean Patent Applications No. 93-21059, No. 93-616, and No. 93- 28017. Other prior arts include a salicide technology of forming single crystal cobalt disilicide contacts over source/drain regions by employing an interlayer between a cobalt layer and a silicon substrate (Reference : M. L. A. Dass, Applied Physics Letter, 1991, Vol. 58, pi 308).
The salicide technology reported by Dass is illustrated in FIGS. 6 A to 6E. Referring to FIGS. 6A to 6E, an MOS transistor, with source/drain regions and a polysilicon gate electrode 3, is first formed on a silicon substrate 1, and then a titanium layer 6 having a thickness of 20 A is deposited on the silicon substrate 1 kept at room temperature by sputtering or vacuum evaporation.
FIG. 6A shows the structure of the MOS transistor having spacers comprised of silicon oxide or silicon nitride and FIG. 6B shows the titanium layer 6 used as an interlayer. Next, a cobalt layer 4 having a thickness of 150 A is deposited onto the titanium layer 6 using sputtering or vacuum evaporation. A TiN protection layer 5 is then formed over the cobalt layer 4 at a temperature in the range of 200-400°C using sputtering or reactive evaporation to protect the underlying layer from any oxidation or agglomeration during subsequent heat treatments. The resultant is shown in FIG. 6C.
Thereafter, the substrate 1 is annealed at a temperature of 700°C or more to form a single crystal CoSi2 layer 7 as shown in FIG. 6D.
The TiN layer 5 as well as the unreacted cobalt in cobalt layer 4 and the titanium layer 6 are removed by subsequent etching processes. The substrate is then subjected to a second high temperature annealing (over 800°C) to form a final silicide layer with low contact resistance and low resistivity as shown in FIG. 6E.
A later article by R. T. Tung, published on Applied Physics Letter, 1996, Vol. 68, p3461, reports that a so-called "Shiraki oxide layer" having a composition of SiOx, which is a chemical oxide layer formed on a silicon substrate during chemical cleaning using H2SO4 and HC1, can be used instead of the titanium layer 6. T. Ogino et al. proposed a method using germanium (Ge) in an article published on Applied Surface Science, 1997, Vol. 117/118, p280.
However, it is reported that their methods require multi-step depositions and have great difficulties in forming a single crystal CoSi2 layer having a thickness of about 500 A. Dormans et al. reported that a cobalt layer could be deposited using chemical vapor deposition at a temperature in the range of 300-600°C, but they could not propose new salicide process (Reference : J. Crystal Growth, 1991, Vol. 114, p364).
The sheet resistance of a silicide thin layer formed by the above prior art salicide methods is about 5-10Ω/Q However, the prior art methods have disadvantages of complicated processes and high-cost manufacturing equipment because both the interlayer and the protection layer are consecutively deposited in a same reactor using sputtering or vacuum evaporation at a temperature in the range of room temperature to 400°C.
Moreover, the prior art methods require a protection layer for preventing the oxidation and agglomeration of the underlying metal layer and can not guarantee uniform thin films because of poor step coverage in a highly integrated device. If a commonly-used titanium layer 6 is employed for an interlayer, pinholes occur at the edges of the oxide structures (field oxide and space oxide) during the annealing process, causing problems including leakage current, instability in electrical properties, and lack of reproducibility.
One of the most serious drawbacks in using the prior art methods is that cobalt atoms from the cobalt layer 4 diffuse into the silicon substrate 1 along the grain boundary of the polycrystalline CoSi2 layer 7 and result in a nonuniform interface between the CoSi2 layer 7 and the silicon substrate 1. In a worst case, silicide is formed even at the source/drain junctions, deteriorating the electrical properties of the semiconductor device. As the overall dimensions of semiconductor devices continue to shrink, a single crystal CoSi2 layer having a uniform interface structure should be formed, which is requisite for a process of forming ultra shallow source/drain junctions.
It is known that (110) or (221) CoSi2 layers including the lattice matching (100) CoSi2 layer are generally formed on a (100) silicon substrate. Because the lattice matching (100) layer has a higher interface energy than those of other layers, it is very difficult to form a single crystal CoSi2 layer having a uniform interface structure. In order to obtain a uniform interface structure, it is desirable to form a single crystal (100) layer having a close lattice match to a (100) silicon substrate. For this purpose, the silicon substrate surface should be kept clean and the diffusion of cobalt atoms into the silicon substrate should be prevented. In the case where the diffusion rate of cobalt atoms is high, crystalline phases of Co2Si, CoSi, and CoSi2 having different compositions are consecutively formed during heat treatment, resulting in a polycrystalline structure. In addition, layers having low interface energy other than the lattice matching (100) layer having higher interface energy are likely to be formed, which makes the formation of a CoSi2 layer of uniform interface structure difficult. Thus, prior art methods have formed an interlayer between the cobalt layer and the silicon substrate to prevent the diffusion of cobalt atoms. However, the method of using the interlayer has many problems as described above.
R. A. Donaton et al. reported that a minor amount of carbon prevented the diffusion of cobalt (Reference : Applied Physics Letter, 70, 1997, pi 266). Thus, there is a possibility of carbon application in silicide contact formation.
Accordingly, it is an object of the present invention to provide a method of forming cobalt silicide contacts in which multi-step deposition processes for the formation of metal layers and interlayers are not performed to simplify the overall process.
It is another object of the present invention to provide a method of forming low-resistance cobalt silicide contacts.
DISCLOSURE OF INVENTION
In accordance with the present invention, a method of forming a CoSi2 layer by depositing a cobalt layer on a silicon substrate uses a cobalt-carbon alloy thin film without using an interlayer such as a titanium layer. The cobalt-carbon alloy thin film is formed using chemical vapor deposition, vacuum evaporation, and sputtering. The cobalt-carbon alloy thin film prevents the diffusion of cobalt atoms into the silicon substrate to facilitate the formation of a single crystal CoSi2 layer. The deposited cobalt-carbon alloy thin film is converted into a (100) single crystal or (100) epitaxial CoSi2 layer by reaction of the alloy thin film with the silicon substrate during heat treatments.
The above described method of the present invention provides process simplicity and lower contact resistance by forming only a cobalt-carbon alloy thin film in a reaction chamber and then performing a heat treatment.
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 shows x-ray diffraction patterns to indicate the amorphous state of a cobalt-carbon alloy thin film formed on a silicon substrate at a temperature of 350 "C using cyclopentadienylcobaltdicarbonyl [C5H5Co(CO)2], a cobalt metal-organic source;
FIG. 2 is an AES (Auger Electron Spectroscopy) graph characterizing the composition distribution of the cobalt-carbon alloy thin film of FIG. 1;
FIG. 3 is an XRD (X-ray diffraction) graph of a silicon surface on which a cobalt layer and a titanium protection layer are consecutively formed and then heat- treated at 800 °C ;
FIG. 4 is an XRD graph of source/drain regions of a silicon substrate surface on which a cobalt layer is formed without using a titanium protection layer and then heat-treated at a temperature in the range of 600 °C ~ 800 °C ;
FIG. 5 is an AES graph characterizing the composition distribution of the silicon substrate surface on which a cobalt layer is formed without using a titanium protection layer and then heat-treated at a temperature of 800 °C ; FIGS. 6 A through 6E, illustrate, in cross section, process steps in the formation of a single crystal cobalt disilicide at the source/drain regions and polysilicon gate of an MOS transistor by reaction of silicon and metal using sputtering or vacuum evaporation according to a prior art method; and
FIGS. 7A through 7D, illustrate, in cross section, process steps in the formation of a CoSi2 using a cobalt-carbon alloy thin film according to the present invention.
Where considered appropriate, for brevity sake, reference numerals have been repeated among the figures to indicate corresponding elements.
BEST MODE FOR CARRYING OUT THE INVENTION
According to the method of the present invention, the direct CoSi2 contact formation to the source/drain regions and polysilicon gate structure can be simplified compared with the prior art process shown in FIG. 6A to FIG. 6E.
FIGS. 7A through 7D, illustrate, in cross section, process steps in the formation of a CoSi2 using a cobalt-carbon alloy thin film according to the present invention. As shown in FIGS. 7A through 7D, if the MOS transistor is fabricated using a cobalt-carbon alloy thin film 8, the process according to the present invention does not require the deposition of the interlayer which is necessary for the prior art method. Referring to FIG. 7A, an MOS transistor, with source/drain regions (not shown) and a polysilicon gate electrode 3, is first formed on a silicon substrate 1. Then, a cobalt-carbon alloy thin film 8 is deposited by chemical vapor deposition using a cobalt metal-organic source such as cyclopentadienylcobaltdicarbonyl [C5H5Co(CO)2] or bis(cyclopentadienyl)cobalt [Co(C5H5)2]. During the deposition step, the cobalt metal-organic source stored in a reservoir of -10°C ~50°C is supplied directly in a gas phase or using a carrier gas such as hydrogen, nitrogen or argon to the silicon substrate 1 kept at a temperature in the range of 300 °C ~400°C . The deposited cobalt-carbon alloy thin film 8 is then subjected to a heat treatment (700°C or more) to form a (100) epitaxial CoSi2 layer 7 on the (100) silicon substrate 1 and a polycrystalline CoSi2 layer 7 on the polysilicon gate electrode 3, respectively, by reaction of cobalt in the cobalt-carbon alloy thin film 8 with silicon, while the cobalt over the silicon oxide 2 does not react with the oxide as shown in FIG. 7C.
In the case of depositing the cobalt-carbon alloy thin film by a vacuum evaporator, it can be deposited on a substrate at room temperature by co-evaporating carbon and cobalt. In this case, the carbon and cobalt respectively contained in tungsten and molybdenum boats or effusion cells are evaporated at a temperature in the range of 1000 °C — 1500 °C and below a pressure of 10"7 Torr.
In the case of depositing the cobalt-carbon alloy thin film by sputtering, it can be deposited on the silicon substrate at room temperature by sputtering an alloy target having a cobalt to carbon ratio of 1 : 1 or 2: 1. In the step of sputtering, argon gas is supplied to the sputtering chamber at a flow rate in the range of 1 — lOsccm to maintain the chamber pressure in the range of 1 ~ lOmTorr, and the silicon substrate is maintained in the temperature range of room temperature to 350 °C . An amorphous cobalt-carbon alloy thin film can be deposited at room temperature in a similar manner to the above by co-sputtering separate cobalt and carbon targets instead of sputtering the cobalt-carbon alloy target.
The deposited cobalt-carbon alloy thin film is then subjected to the same heat treatment as for that formed by the above chemical vapor deposition. Therefore, a (100) epitaxial CoSi2 layer is formed on the (100) silicon substrate while a polycrystalline CoSi2 layer is formed on the polysilicon gate electrode, by reaction of cobalt in the cobalt-carbon alloy thin film with silicon. The cobalt over the silicon oxide does not react with the oxide.
Referring to FIG. 7D, the remaining unreacted cobalt-carbon alloy thin film 8 over the spacer and the field oxide is removed by etching for the final salicide process. Hereinafter, exemplary methods of the present invention will now be described in detail. [Example 1]
A silicon substrate having an MOS transistor comprised of source/drain regions and a polysilicon gate electrode is maintained at a temperature of 350 °C in a reactor. Then, a cobalt-carbon alloy thin film is deposited by chemical vapor deposition using a cobalt metal-organic source, bis(cyclopentadienyl)cobalt [Co(C5H5)2]. During the deposition step, the cobalt metal-organic source stored in a reservoir of 35 °C is supplied to the reactor using a hydrogen carrier gas of 50sccm flow rate. In this case, the deposition pressure is in the range of 10 ~500mTorr and the film deposited in this pressure range typically has 50:50 atomic fraction ratio of cobalt to carbon. The resultant is then subjected to rapid thermal annealing at a temperature of 800 °C for 5 minutes to form a CoSi2 layer.
In general, the cobalt metal-organic source has a vapor pressure sufficiently high to be transferred to the reactor in a gas phase without using a carrier gas such as hydrogen even though the reservoir is maintained at room temperature. Thus, if hydrogen is used as a carrier gas, a cobalt-carbon alloy thin film can be formed on the silicon substrate at a deposition rate of 500 A /min.
[Example 2]
The same as in Example 1 except the cobalt metal-organic source is cyclopentadienylcobaltdicarbonyl [C5H5Co(CO)2]. The flow rate of transferred [C5H5Co(CO)2] is in the range of 5 ~ 15sccm, and the deposition is in the range of 400 ~ 500mTorr. The deposited cobalt-carbon alloy thin film is subjected to rapid thermal annealing at a temperature of 800 °C for 5 minutes to form a CoSi2 layer. The deposited cobalt-carbon alloy thin film is comprised of 50% cobalt and 50% carbon, and the XRD analysis of the thin film is shown in FIG. 1.
The broad and smooth diffraction curve implies that the deposited cobalt- carbon alloy thin film is amorphous.
FIG. 2 is an AES (Auger Electron Spectroscopy) graph characterizing the composition distribution of the cobalt-carbon alloy thin film of FIG. 1. From the FIG. 2, it is found that the cobalt to carbon ratio in the cobalt-carbon alloy thin film deposited at a temperature of 350 °C is about 1 :1. [Example 3]
After the deposition of a cobalt layer on a silicon substrate, a titanium layer is deposited as a protection layer. The resultant is then subjected to rapid thermal annealing at a temperature of 800 °C and in a nitrogen ambient for 5 minutes to form a CoSi2 layer. The XRD pattern of the CoSi2 layer is shown in FIG. 3.
After the deposition of a cobalt layer on a silicon substrate, the resultant is then subjected to rapid thermal annealing at temperatures of 600 °C, 700 °C, and 800 °C without previously forming a protection layer, and then investigated by XRD analysis. The XRD analysis is shown in FIG. 4. Referring to FIG. 4, it is found that single crystal CoSi2 layers are formed at a temperature of 700 °C or more.
Referring back to FIG. 3, the (200) diffraction peak of an epitaxial CoSi2 layer appears together with the (200) diffraction peak of the silicon substrate. This indicates that a (100) epitaxial CoSi2 layer is formed on the (100) silicon substrate after the thermal annealing. Referring to FIG. 4, it is found that an epitaxial CoSi2 layer is formed at a temperature of 700 °C or more.
The cobalt on the silicon oxide (SiO2 ) does not react with the silicon oxide, and the remaining unreacted cobalt is removed by a wet etchant such as NH4OH+H2O2, HNO3+HO2, or H2SO4+H2O2. The cobalt silicide formed by the above method has a resistivity in the range of 16 ~ 20 μ Ω • cm and has a sheet resistance in the range of 5 ~ 10 Ω /□ similar to that of cobalt silicide formed by sputtering.
It is found from the TEM (Transmission Electron Microscopy) analysis that a lattice matching epitaxial cobalt disilicide layer having a thickness of about 450 A is formed on a silicon substrate in the case of using a protection layer.
[Example 4]
Without using a protection layer, a cobalt-carbon alloy thin film is deposited using a cobalt metal-organic source, cyclopentadienylcobaltdicarbonyl [C5H5Co(CO)2] on a silicon substrate, and then subjected to rapid thermal annealing at a temperature of 800 °C and in nitrogen ambient for 5 minutes to form a CoSi2 layer. The depth profile of the components of resultant CoSi2 layer is investigated by AES analysis and shown in FIG. 5. In the FIG. 5, the y-axis represents atomic fraction of the respective CoSi2 layer components. Referring to FIG. 5, it is found that the cobalt in the cobalt-carbon alloy thin film diffuses into the silicon substrate and the carbon prevents the excessive diffusion of cobalt to facilitate the formation of an epitaxial CoSi2 layer. Moreover, because the carbon suppresses the diffusion of oxygen, the oxidation of cobalt frequently seen in the annealing process is also suppressed and the amount of oxygen in the cobalt-carbon alloy thin film becomes small. That is, the cobalt-carbon alloy thin film of the present invention plays an important role in the suppression of both cobalt diffusion into the silicon substrate and oxidation of cobalt.
According to the present invention, the CoSi2 contact formation process is simplified because it does not requires deposition steps of interlayers and a TiN protection layer, and their subsequent heat treatments. In addition, an epitaxial CoSi2 layer with low resistivity and high reproducibility can be formed by the deposition of a cobalt-carbon alloy thin film and its subsequent heat treatment. The chemical vapor deposited CoSi2 layer has enhanced step coverage and uniform interface characteristics suitable for the interconnection process of an ultra fine contact structure.

Claims

WHAT IS CLAIMED IS :
1. A method of forming cobalt-disilicide contacts using a cobalt-carbon alloy thin film, the method comprising the steps of: (a) forming an MOS transistor on a silicon substrate, with source/drain regions and a polysilicon gate electrode of said MOS transistor;
(b) depositing a carbon-containing cobalt layer overlying the resultant of the (a) step; and
(c) annealing said carbon-containing cobalt layer to form an epitaxial CoSi2 layer over said source/drain regions and a CoSi2 single crystal layer over said polysilicon gate electrode, respectively.
2. The method of claim 1, wherein said step of annealing is performed using rapid thermal annealing.
3. The method of claim 1, wherein said carbon-containing cobalt layer is deposited using a cobalt metal-organic source selected from the group consisting of (C5H5)2Co and C5H5Co(CO)2.
4. The method of claim 1, wherein said carbon-containing cobalt layer is deposited using a method selected from the group consisting of chemical vapor deposition, sputtering and evaporation.
5. The method of claim 1, wherein the stoichiometric ratio of cobalt to carbon of the deposited carbon-containing cobalt layer is in the range of 1 : 1 ~ 2: 1.
6. The method of claim 3, wherein the stoichiometric ratio of cobalt to carbon of the deposited carbon-containing cobalt layer is in the range of 1 : 1 ~ 2: 1.
7. The method of claim 2, wherein said step of rapid thermal annealing is performed at a temperature in the range of 700 ~ 800°C to form a CoSi2 layer with a resistivity of 15 ~ 20 μ Ω • cm.
8. A method of forming cobalt-disilicide contacts using a cobalt-carbon alloy thin film, the method comprising the steps of:
(a) forming an MOS transistor on a silicon substrate, with source/drain regions and a polysilicon gate electrode of said MOS transistor;
(b) depositing a carbon layer overlying the resultant of the (a) step;
(c) depositing a cobalt layer overlying said carbon layer; and
(d) annealing the resultant of the (c) step to form a CoSi2 single crystal layer.
9. The method of claim 8, wherein said step of annealing is performed using rapid thermal annealing.
PCT/KR1999/000617 1998-10-13 1999-10-13 Method of forming cobalt-disilicide contacts using a cobalt-carbon alloy thin film WO2000022659A1 (en)

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