JPS6138264B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a high melting point metal, namely molybdenum (Mo),
This invention relates to improvements in methods for forming silicide layers of tungsten (W), tantalum (Ta), titanium (Ti), niobium (Nb), etc.

In semiconductor integrated circuit devices (ICs) with a high degree of integration such as LSI and VLSI, a large number of microscopic elements are formed at an extremely high density, so wiring must be formed with an extremely narrow width. The length also gets longer. Therefore, in a structure in which a polycrystalline silicon layer is used as wiring as in a conventional semiconductor IC, the wiring resistance increases because the polycrystalline silicon layer has a high sheet resistance of about 30 to 60 [Ω/□], and the semiconductor There is a problem that the operating speed of the IC decreases.

Therefore, recently, polycrystalline silicon is 1/10~
Mo, W, which can obtain a sheet resistance as low as 1/20
High-melting point metals such as Ta, Ti, and Nb, as well as silicides of these high-melting point metals, have begun to be used as wiring materials. Among them, molybdenum silicide (MoSi ₂ ), which has excellent oxidation resistance and chemical resistance, and tungsten
High melting point metal silicides such as silicide (WSi ₂ ), tantalum silicide (TaSi ₂ ), titanium silicide (TiSi ₂ ), and niobium silicide (NbSi ₂ ) have come into widespread use.

Methods for forming these high melting point metal silicide layers include (1) sputtering using a target made of high melting point metal silicide, (2) simultaneous sputtering using a high melting point metal target and a silicon target, or There are two methods: (3) forming a high melting point metal layer on a polycrystalline silicon layer and then performing alloying. The method (1) has the disadvantage that the purity of the silicide layer cannot be improved because a high-purity target cannot be obtained, and the method (2) has the disadvantage of not increasing the purity of the silicide layer. The drawback was that it was difficult to obtain a low-resistance silicide layer because it was difficult to control the amount of evaporation.

Conventionally, therefore, the method described in (3) is generally used in which a high melting point metal layer is deposited on the polycrystalline silicon layer and then an alloying layer is formed on both layers to form a silicide layer. However, during the heat treatment during alloying, the reaction between polycrystalline silicon and the high melting point metal is difficult to occur uniformly because the high melting point metal is extremely active against the atmosphere. There was a problem that it was still insufficient to form a layer.

In view of the above problems, the present invention provides a method for forming a high melting point metal silicide layer by alloying polycrystalline silicon and a high melting point metal, in which alloying is performed uniformly and stably, and the alloying is performed over the entire surface of the substrate to be processed. The present invention provides a method for obtaining a high-quality silicide layer with low resistance.

That is, the present invention provides a method for forming a high melting point metal silicide layer, in which a non-doped or phosphorus-doped first polycrystalline silicon layer is formed on a substrate to be processed, and a high melting point metal silicide layer is formed on the first polycrystalline silicon layer. forming a melting point metal layer, forming a second polycrystalline silicon layer on the high melting point metal layer, and performing heat treatment to alloy the high melting point metal layer with the first and second polycrystalline silicon layers; It is characterized by having the following.

The present invention will be described below with reference to FIGS. 1 to 5 regarding one embodiment.
The process will be explained in detail using the process cross-sectional diagrams shown in the figures.

When forming a gate line made of molybdenum silicide (MoSi ₂ ) in, for example, an MIS IC by the method of the present invention, as shown in FIG.
A field oxide film 2 and a channel cut are formed on a semiconductor substrate to be processed in which a field oxide film 2 is formed using a LOCOS method or the like, and a channel cut region 3 is formed under the field oxide film 2 by a method such as ion implantation. A layer of 200 to 500 Å is applied to one surface of the semiconductor substrate separated by region 3 by a method such as thermal oxidation.
A gate oxide film 4 of about 100 mL is formed. Next, as shown in FIG. 2, the substrate to be processed is sputtered using a conventional direct current or high frequency sputtering method using a silicon target in argon (Ar) having a pressure of about 10 ^-3 Torr. , for example 3000
A first polycrystalline Si layer 5 having a thickness of about [Å] is deposited, and then a molybdenum target of about 1,000 to 1,500 Å is deposited on the first polycrystalline Si layer 5 by the same sputtering method as described above using a molybdenum target. A molybdenum (Mo) layer 6 with a thickness of about [Å] is deposited, and then a second polycrystalline Si layer with a thickness of, for example, about 500 [Å] is deposited on the Mo layer 6 by sputtering again using a silicon target. Layer 7 is deposited. Next, using the photoresist pattern as a mask, a reactive sputtering process is performed using carbon tetrafluoride (CF ₄ ), carbon difluoride dichloride (CF ₂ Cl ₂ ), carbon tetrachloride (CCl ₄ ), etc. as an etching gas. The second polycrystalline Si layer 7, the Mo layer 6 and the first polycrystalline layer are etched by etching.
By selectively etching the Si layer 5, a laminated gate wiring 8 having a structure in which a first polycrystalline Si layer 5, a Mo layer 6, and a second polycrystalline Si layer 7 are sequentially laminated as shown in FIG. 3 is formed. Then, the substrate to be processed is heated to 900 to 1000 [°C] for a desired time in nitrogen (N ₂ ) or vacuum to form the first and second polycrystalline Si layers 5 and 7. The Mo layer 6 is alloyed to form a MoSi ₂ gate wiring 9 as shown in FIG. In addition, at the stage where the alloying reaction is carried out, the surface of the Mo layer 6, which is highly active at high temperatures, is covered with the second polycrystalline Si layer 7, so that a trace amount of oxygen contained in the processing atmosphere is absorbed. (O ₂ ) and the Mo layer 6
Therefore, the along reaction between the Mo layer 6 and the first and second polycrystalline Si layers 5 and 7 is uniformly carried out over the entire substrate surface. Furthermore, in order to prevent oxidative decomposition of the MoSi ₂ layer when heat treatment is applied in an oxidizing atmosphere, it is preferable that Si be present in an amount larger than that required to form the MoSi ₂ composition. In this embodiment, the first polycrystalline Si layer 5 is formed to be about 500 Å thick, so that when the alloying reaction is completed and the MoSi ₂ gate wiring 9 is completed as shown in FIG. Then, a thin first polycrystalline film with a thickness of just under 500 Å is placed at the bottom end of the wiring.
The Si layer 11 remains.

Next, as shown in FIG. 5, source/drain regions 10a and 10b having the second conductivity type are formed by a method such as ion implantation using the MoSi ₂ gate wiring as a mask according to the usual MSI IC manufacturing method. Although not shown, an insulating film, upper layer wiring, etc. are formed on the substrate to provide a MIS IC.

In the above embodiment, the first polycrystalline Si layer was formed of a non-doped Si layer;
If the Si layer is formed as a phosphorus-doped N ⁺ type polycrystalline Si layer by sputtering in Ar containing phosphine (PH ₃ ), alloying will be more uniform, and the MoSi ₂ wiring will be more uniform. Since electrical conductivity is imparted to the underlying polycrystalline Si layer, the stray capacitance of wiring is reduced, which is further advantageous in improving the performance of semiconductor ICs.

Note that as in the above embodiment, the first polycrystalline Si layer,
When the Mo layer and the second polycrystalline Si layer are all formed by sputtering, continuous formation is possible using the same sputtering device.

In the above embodiment, the first and second polycrystals
Although the Si layer and the refractory metal, ie, Mo layer, were formed by sputtering, it is a well-known fact that these layers can be formed not only by vapor deposition but also by chemical vapor deposition.

An example of conditions for forming a polycrystalline Si layer and a Mo layer by chemical vapor deposition is as follows.

[Phosphorus-doped n ⁺ type polycrystalline Si layer]

Reactive gas and flow rate Monosilane (SiH ₄ ) 40 [SCCM] Phosphine (PH ₃ ) 5 to 6 [SCCM] Pressure 0.2 to 0.3 [Torr] Growth temperature 625 [℃] [Mo layer] Reaction gas and flow rate 6 Tungsten fluoride (MoF ₆ ) 100 [SCCM] Hydrogen 2 [SLM] Pressure 0.3 to 0.5 [Torr] Growth temperature 300 to 350 [℃] [Non-doped polycrystalline Si layer] Reactant gas and flow rate Monosilane (SiH ₄ ) 40 [SCCM] ] Pressure: 0.2 to 0.3 [Torr] Growth temperature: 625 [°C] In carrying out the present invention, the thicknesses and thickness ratios of these vapor-phase grown layers may be the same as in the above embodiments, and alloy The conditions may be exactly the same.

In the above examples, the method of the present invention was applied to MoSi ₂
Although an example of layer formation has been described, the high melting point metal silicide layer forming method of the present invention can be applied to the above-mentioned MoSi such as tungsten silicide (WSi ₂ ), tantalum silicide (TaSi ₂ ), titanium silicide (TiSi ₂ ), niobium silicide (NbSi ₂ ), etc. Of course, the present invention can also be applied to shapes of high melting point metal silicide layers other than ₂ .

In addition, in the above examples, the method of the present invention is
Although the case where it is applied to the formation of high melting point metal silicide wiring in MISIC has been described, the method of the present invention is applicable not only to the above-mentioned gate wiring but also to various high melting point metal silicide wiring arranged on an insulating film in MISIC and bipolar IC. It can also be applied to formation.

As described above, according to the present invention, a high melting point metal silicide wiring having low resistance can be formed uniformly over the entire surface of a substrate to be processed with good workability and in a stable state. Therefore, the present invention is extremely effective in improving the performance and manufacturing yield of highly integrated semiconductor ICs such as LSI and VLSI.

[Brief explanation of the drawing]

1 to 5 are process cross-sectional views in one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a channel cut region, 4 is a gate oxide film, 5 is a first polycrystalline silicon layer, 6 is a molybdenum layer, and 7 is a thin second layer. polycrystalline silicon layer, 8
9 indicates a stacked gate wiring, 9 a molybdenum silicide gate wiring, and 11 a thin first polycrystalline silicon layer.

Claims (1)

[Claims] 1. A first polycrystalline silicon layer is formed on a substrate to be processed, a high melting point metal layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the high melting point metal layer. A method for forming a high melting point metal silicide layer, comprising the steps of: forming a polycrystalline silicon layer, and performing heat treatment to alloy the high melting point metal layer with first and second polycrystalline silicon layers. 2. The method of forming a refractory metal silicide layer according to claim 1, wherein the first polycrystalline silicon layer is a phosphorus-doped polycrystalline silicon layer.