CN113764341B - 一种半导体结构及其制作方法和半导体存储器 - Google Patents
一种半导体结构及其制作方法和半导体存储器 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 104
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 238000005468 ion implantation Methods 0.000 claims abstract description 39
- 150000002500 ions Chemical class 0.000 claims description 68
- 238000000034 method Methods 0.000 claims description 43
- 239000010410 layer Substances 0.000 claims description 40
- 238000002513 implantation Methods 0.000 claims description 25
- 238000002955 isolation Methods 0.000 claims description 23
- 239000011241 protective layer Substances 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000006731 degradation reaction Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 230000009467 reduction Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052582 BN Inorganic materials 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
本发明公开了一种半导体结构及其制作方法和半导体存储器。该半导体结构的制作方法包括:提供衬底并对所述衬底进行离子注入,形成有源区;在所述衬底表面形成栅极沟槽;测量所述栅极沟槽的深度;如果所述栅极沟槽的深度满足预设条件时,则根据所述栅极沟槽的深度对所述衬底进行离子注入补偿,在所述栅极沟槽一侧的所述有源区内形成离子补偿区域。该半导体结构的制作方法能够避免由栅极沟槽的深度变异造成的半导体结构性能劣化,改善半导体存储器的性能。
Description
技术领域
本发明实施例涉及半导体技术领域,尤其涉及一种半导体结构及其制作方法和半导体存储器。
背景技术
埋入式字线是指将字线埋设在半导体衬底的内部,可以显著地减少在字线与位线之间的寄生电容,大幅地改善半导体器件的电压读出操作的可靠性,为增加半导体器件的集成密度提供了一种新的选择。
现有技术中,在埋入式晶体管的栅极沟槽制作之前,其离子注入已经完成,即注入离子的参数已经确定,在随后的制程中栅极沟槽的深度存在变异可能,使得阈值电压发生变异,会造成埋入式晶体管的性能的劣化,进而会造成半导体存储器良率或可靠性的劣化。
发明内容
本发明提供一种半导体结构及其制作方法和半导体存储器,以避免由栅极沟槽的深度变异造成的半导体结构性能劣化,改善半导体存储器的性能。
第一方面,本发明实施例提供一种半导体结构的制作方法,包括:
提供衬底并对所述衬底进行离子注入,形成有源区;
在所述衬底表面形成栅极沟槽;
测量所述栅极沟槽的深度;
如果所述栅极沟槽的深度满足预设条件时,在所述栅极沟槽一侧的所述有源区内形成离子补偿区域。
可选的,根据在所述栅极沟槽一侧的所述有源区内形成离子补偿区域,包括:
在所述栅极沟槽一侧的所述有源区内形成位线接触孔;
通过所述位线接触孔对所述衬底进行离子注入补偿,形成所述离子补偿区域。
可选的,所述根据所述栅极沟槽的深度对所述衬底进行离子注入补偿,包括:
根据所述栅极沟槽的深度确定补偿离子的注入深度;
根据所述补偿离子的注入深度确定所述补偿离子的注入能量;
根据所述补偿离子的注入能量,对所述衬底进行离子注入补偿,形成所述离子补偿区域。
可选的,所述预设条件为所述栅极沟槽的深度小于目标深度,且所述栅极沟槽的深度与所述目标深度的差值绝对值大于阈值标准差;
所述阈值标准差根据以所述目标深度为工艺参数制作而成的多个所述栅极沟槽的深度的统计结果确定。
可选的,所述在所述衬底表面形成栅极沟槽,包括:
在所述衬底表面形成浅沟道隔离结构,将所述有源区分隔成若干块;
在所述衬底表面形成所述栅极沟槽,所述栅极沟槽的深度小于所述浅沟道隔离结构的深度。
可选的,所述测量栅极沟槽的深度之后,还包括:
在所述栅极沟槽表面依次形成栅氧化层和扩散阻挡层;
在所述栅极沟槽内填充字线;
在所述字线和所述衬底的表面形成保护层;
所述在所述栅极沟槽一侧的所述有源区内形成位线接触孔包括:
刻蚀所述保护层形成所述位线接触孔;所述位线接触孔贯穿所述保护层,且露出所述衬底;所述位线接触孔位于同一块所述有源区内相邻两个所述栅极沟槽之间。
第二方面,本发明实施例提供了一种半导体结构,采用第一方面提供的任一半导体的制作方法制作得到,包括:衬底、栅极沟槽和离子补偿区域;
有源区位于所述衬底中形成有;
所述离子补偿区域位于深度满足预设条件的所述栅极沟槽一侧的所述有源区内。
可选的,所述半导体结构还包括位线接触孔,所述位线接触孔在所述衬底上的垂直投影与所述离子补偿区域在所述衬底上的垂直投影至少部分交叠。
可选的,所述半导体结构还包括浅沟道隔离结构,所述浅沟道隔离结构位于所述衬底表面且将所述有源区分隔成若干块,且所述栅极沟槽的深度小于所述浅沟道隔离结构的深度;
所述半导体结构还包括:
位于所述栅极沟槽表面的栅氧化层和扩散阻挡层;
位于所述栅极沟槽内的字线;
位于所述字线和所述衬底表面的保护层,所述位线接触孔贯穿所述保护层且露出所述衬底,且所述位线接触孔位于同一块所述有源区内相邻两个所述栅极沟槽之间。
第三方面,本发明实施例提供了一种半导体存储器,包括第二方面提供的任一半导体结构。
本发明实施例提供的技术方案,通过测量栅极沟槽的深度,并且判断栅极沟槽的深度是否满足预设条件,如果栅极沟槽的深度满足预设条件,则说明栅极沟槽与沟道调节掺杂区的距离比较远,沟道调节掺杂区对阈值电压调节影响比较小,对栅极沟槽两侧的源漏区导通的阻挡作用较弱,即栅极沟槽两侧的源漏区较容易导通,即该半导体结构的阈值电压较小;通过根据栅极沟槽的深度对衬底进行受主离子注入补偿,在所述栅极沟槽一侧的所述有源区内形成离子补偿区域,离子补偿区域距离栅极沟槽较近,能在一定程度上有效阻挡栅极沟槽两侧的源漏区的导通,因此提高了半导体结构的阈值电压,补偿了由于栅极沟槽的深度过浅导致的阈值电压的降低,避免由栅极沟槽的深度变异造成的半导体结构性能劣化,改善半导体存储器的性能。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案,下面对描述实施例中所需要用到的附图做一简单介绍。显然,所介绍的附图只是本发明所要描述的一部分实施例的附图,而不是全部的附图,对于本领域普通技术人员,在不付出创造性劳动的前提下,还可以根据这些附图得到其他的附图。
图1为本发明实施例提供的一种半导体结构的制作方法的流程示意图;
图2-图5为本发明实施例提供的半导体结构的制作方法各个步骤的制备工艺示意图;
图6为本发明实施例提供的一种栅极沟槽深度与阈值电压的关系示意图;
图7为本发明实施例提供的一种阈值电压与良率的关系示意图
图8为本发明实施例提供的又一种半导体结构的制作方法的流程示意图;
图9和图10为本发明实施例提供的一种离子补偿区域的制作方法各个步骤的制备工艺示意图;
图11为本发明实施例提供的一种离子注入补偿的方法的流程示意图。
图12为本发明实施例提供的一种栅极沟槽深度与离子注入深度的关系示意图;
图13为本发明实施例提供的一种离子注入深度与离子注入能量的关系示意图;
图14为本发明实施例提供的又一种半导体结构的制作方法的流程示意图;
图15为本发明实施例提供的多个半导体结构的栅极沟槽的深度的统计结果示意图;
图16为本发明实施例提供的一种栅极沟槽的制作方法的流程示意图;
图17为本发明实施例提供的又一种半导体结构的制作方法的流程示意图;
图18为本发明实施例提供的一种字线的制作方法的制备工艺示意图;
图19为本发明实施例提供的一种半导体存储器的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是,此处所描述的具体实施例仅仅用于解释本申请,而非对本申请的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与本申请相关的部分而非全部结构。
图1为本发明实施例提供的一种半导体结构的制作方法的流程示意图,图2-图5为本发明实施例提供的半导体结构的制作方法各个步骤的制备工艺示意图。如图1所示,具体步骤包括:
S110,提供衬底并对所述衬底进行离子注入,形成有源区。
示例性的,如图2所示,以NMOS为例,向衬底110内部注入N型离子形成具有一定深度的有源区121,向有源区121注入受主杂质,形成沟道调节掺杂区122,因此沟道调节掺杂区122产生的电压对有源区121中的导电粒子的密度起到控制作用。在其他实施方式中,还可以是P型离子形成有源区121,注入施主杂质形成沟道调节掺杂区122。需要说明的是,衬底110可采用但不限于硅、锗、锗硅等常用的半导体衬底材料,注入离子的类型根据实际需求选择。
S120,在所述衬底表面形成栅极沟槽。
具体的,在衬底110表面沉积形成衬底保护层131,在衬底保护层131背离衬底110一侧的表明沉积形成硬掩膜层132,硬掩膜层132背离衬底110一侧的表明涂覆光阻材料,形成光阻层133,利用栅极沟槽的掩膜板进行曝光,在光阻层133上形成栅极沟槽的图案,如图3所示;光阻层133、硬掩膜层132及衬底保护层131共同作为掩膜,在衬底110表面刻蚀形成多个栅极沟槽140,去除光阻层133,在栅极沟槽140的两侧形成源漏区,如图4所示。衬底保护层131的材料选自氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅、碳氮氧化硅以及氮化硼所构成群组的其中一种,硬掩膜层133的材料选自氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅、碳氮氧化硅以及氮化硼所构成群组的其中一种,示例性的,衬底保护层131可选择氧化硅,硬掩膜层133可选择氮化硅。
S130,测量所述栅极沟槽的深度。
S140,如果所述栅极沟槽的深度满足预设条件时,则根据所述栅极沟槽的深度对所述衬底进行离子注入补偿,在所述栅极沟槽一侧的所述有源区内形成离子补偿区域。
具体的,如图5所示,测量得到栅极沟槽140的深度为h,如果栅极沟槽140的深度h满足预设条件,则说明栅极沟槽140的深度h较短,即栅极沟槽140距沟道调节掺杂区122较远。沟道调节掺杂区122中的受主杂质能够控制有源区121中的可移动电荷的密度,如果栅极沟槽140距沟道调节掺杂区122较远,会降低沟道调节掺杂区122对栅极沟槽140附近可移动电荷的密度的控制作用,栅极沟槽140一侧的源漏区中的电荷更容易穿过栅极沟槽140到达另一侧的源漏区,即栅极沟槽140两侧的源漏区更容易导通,导致源漏区的导通电压减小,即半导体结构的阈值电压减小。而阈值电压减小会影响到半导体结构的性能,具体分析如下。
示例性的,图6为本发明实施例提供的一种栅极沟槽深度与阈值电压的关系示意图,图7为本发明实施例提供的一种阈值电压与良率的关系示意图。结合图6和图7,栅极沟槽深度每改变1nm,则半导体结构电阈值电压改变10mv,当半导体结构阈值电压小于670mV时,半导体结构的良率会明显下降,因此要保证半导体结构的性能必须确保半导体结构阈值电压Vth大于670mV。
本发明实施例中,通过根据栅极沟槽140的深度对衬底110进行离子注入补偿,在栅极沟槽140的一侧的有源区121内形成离子补偿区域150,如图5所示,离子补偿区域150的作用与沟道调节掺杂区122的作用相同,对栅极沟槽140附近的可移动电荷的密度起到控制作用,使栅极沟槽140两侧的源漏区更难导通,因此提高了源漏区的导通电压,即阈值电压,补偿了由于栅极沟槽140的深度过浅导致的阈值电压的降低,避免由栅极沟槽140的深度变异造成的半导体结构性能劣化,改善半导体存储器的性能。
可选的,图8为本发明实施例提供的又一种半导体结构的制作方法的流程示意图。如图8所示,具体步骤包括:
S110,提供衬底并对所述衬底进行离子注入,形成有源区。
S120,在所述衬底表面形成栅极沟槽。
S130,测量所述栅极沟槽的深度。
S141,如果所述栅极沟槽的深度满足预设条件时,在所述栅极沟槽一侧的所述有源区内形成位线接触孔;
S142,通过所述位线接触孔对所述衬底进行离子注入补偿,形成所述离子补偿区域。
具体的,图9和图10为本发明实施例提供的一种离子补偿区域的制作方法各个步骤的制备工艺示意图。栅极沟槽140的深度满足预设条件时,在保护层161背离衬底110一侧形成光阻层134,利用位线接触孔的掩膜板进行曝光,在光阻层134上形成位线接触孔的图案,如图9所示。光阻层134、扩散阻挡层162、保护层161和衬底110共同作为掩膜,在衬底110表面刻蚀形成多个位线接触孔170,去除光阻层134,通过位线接触孔170对衬底110进行离子注入补偿,注入的离子在衬底110内扩散形成具有一定深度的离子补偿区域150,如图10所示。由于离子注入需在衬底110的表面上进行,才能确保注入离子在有源区121内形成离子补偿区域150,因此需要利用刻蚀等工艺露出衬底110的表面,以进行补偿离子的注入,本发明实施例通过位线接触孔170进行补偿离子注入,无需增加额外的工艺,简化了工艺过程。
可选的,图11为本发明实施例提供的一种离子注入补偿的方法的流程示意图。如图11所示,具体步骤包括:
S210,根据所述栅极沟槽的深度确定补偿离子的注入深度;
具体的,图12为本发明实施例提供的一种栅极沟槽深度与离子注入深度的关系示意图。如图12所示,通过大量的实验数据获取到栅极沟槽的深度的量测值与离子注入深度的关系,当栅极沟槽的深度的量测值为h1时,对应的离子注入深度为H1。
S220,根据所述补偿离子的注入深度确定所述补偿离子的注入能量;
具体的,图13为本发明实施例提供的一种离子注入深度与离子注入能量的关系示意图。在实际的工艺过程中,离子的注入深度取决于离子的注入能量,根据公开的数据获取到离子的注入深度与离子的注入能量的关系,如图13所示,当离子注入深度为H1时,对应的离子的注入能量为E1,因此可以根据栅极沟槽的深度h1确定出离子的注入能量为E1。
S240,根据所述补偿离子的注入能量,对所述衬底进行离子注入补偿,形成所述离子补偿区域。
示例性的,栅极沟槽的深度的量测值为h1,可确定出补偿离子的注入能量E1,将补偿离子的注入能量E1作为工艺参数对衬底进行离子注入补偿,从而在栅极沟槽一侧的有源区内形成离子补偿区域,以补偿阈值电压。
可选的,补偿离子的注入剂量D可通过大量的实验数据获取阈值电压或良率参数与离子注入剂量的关系,再根据需要补偿的阈值电压进行相应计算可得。
可选的,图14为本发明实施例提供的又一种半导体结构的制作方法的流程示意图。如图14所示,具体步骤包括:
S110,提供衬底并对所述衬底进行离子注入,形成有源区。
S120,在所述衬底表面形成栅极沟槽。
S130,测量所述栅极沟槽的深度。
S143,如果所述栅极沟槽的深度满足所述栅极沟槽的深度小于目标深度,且所述栅极沟槽的深度与所述目标深度的差值绝对值差大于阈值标准差;则根据所述栅极沟槽的深度对所述衬底进行离子注入补偿,在所述栅极沟槽一侧的所述有源区内形成离子补偿区域。
其中,所述阈值标准差根据以所述目标深度为工艺参数制作而成的多个所述半导体结构的栅极沟槽的深度的统计结果确定。
具体的,以h2为工艺参数制作半导体结构,则目标深度为h2,由于工艺设备、工艺环境等方面的影响,制作而成的半导体结构的栅极沟槽的深度h可能大于目标深度h2也能小于目标深度h2,当栅极沟槽的深度h处于目标深度h2一定的偏差范围内时,不影响半导体结构的性能。通过测量多个性能正常的半导体结构的栅极沟槽的深度h,根据栅极沟槽的深度h的统计结果计算得到阈值标准差。示例性的,选取N个以目标深度h2为工艺参数正常制作的半导体结构,测量得到这N个性能正常的半导体结构的栅极沟槽的深度h’i,(1≤i≤N),计算N个栅极沟槽深度h’i的平均值havg和标准差s,该平均值havg作为标准平均值SH,该标准差s作为阈值标准差DSth,也就是说当半导体结构的栅极沟槽的深度h与标准平均值SH的差值绝对值位于该阈值标准差DSth范围内时,则认为该半导体结构的沟槽深度未发生异常。需要说明的是,本发明实施例仅示例性说明标准平均值和阈值标准差的确定方法,本申请对比不做具体限制。
当栅极沟槽的深度h小于目标深度h2,栅极沟槽距沟道调节掺杂区122较远,存在阈值电压减小的风险,需要进一步确认栅极沟槽的深度h是否小到足够影响半导体结构的阈值电压;当半导体结构的栅极沟槽的深度h与标准平均值SH的差值绝对值大于阈值标准差DSth,则说明该半导体结构的沟槽深度发生异常,因此,需要通过补偿离子的注入来进行补偿。
示例性的,图15为本发明实施例提供的多个半导体结构的栅极沟槽的深度的统计结果示意图。如图15所示,选取多个半导体结构,测量其栅极沟槽的深度,获取到的统计结果,计算得到半导体结构的栅极沟槽的深度的平均值为137nm,阈值标准差为1.4nm,在一倍阈值标准差范围内,半导体结构的阈值电压会有3%的误差,在三倍阈值标准差范围内,半导体结构的阈值电压会有至少10%的误差。通过上述方法补偿阈值电压,最终得到半导体结构的阈值电压的误差会小于3%。
可选的,图16为本发明实施例提供的一种栅极沟槽的制作方法的流程示意图。如图16所示,具体步骤包括:
S121,在所述衬底表面形成浅沟道隔离结构,将所述有源区分隔成若干块。
S122,在所述衬底表面成所述栅极沟槽,所述栅极沟槽的深度小于所述浅沟道隔离结构的深度。
具体的,如图5所示,在衬底110的表面分别形成浅沟道隔离结构180栅极沟槽140,浅沟道隔离结构180将有源区121进行分隔,浅沟道隔离结构180的深度Z大于栅极沟槽140的深度h,以实现浅沟道隔离结构180对半导体结构的分隔,确保各个半导体结构能够独立的工作,不会受到相邻半导体结构电压电流变化的影响。
可选的,图17为本发明实施例提供的又一种半导体结构的制作方法的流程示意图。如图17所示,具体步骤包括:
所述测量栅极沟槽的深度之后,还包括:
S310,提供衬底并对所述衬底进行离子注入,形成有源区。
S320,在所述衬底表面形成栅极沟槽。
S330,测量所述栅极沟槽的深度。
S340,在所述栅极沟槽表面依次形成栅氧化层和扩散阻挡层;
S350,在所述栅极沟槽内填充字线;
S360,在所述字线的表面和所述衬底的表面形成保护层;
S370,刻蚀所述保护层形成所述位线接触孔;所述位线接触孔贯穿所述保护层,且露出所述衬底;所述位线接触孔位于同一块所述有源区内相邻两个所述栅极沟槽之间;
示例性的,图18为本发明实施例提供的一种字线的制作方法的制备工艺示意图。可采热氧化或其它沉积方法在栅极沟槽的表面形成栅氧化层163,栅氧化层163的材质一般选择氧化硅;在栅氧化层163背离衬底110一侧以及浅沟道隔离结构180的表面形成扩散阻挡层162,通过扩散阻挡层162材质包括但不限于氮化钛或氮化钽,用于减少或防止字线190与衬底110之间的扩散。在扩散阻挡层162的表面沉积形成金属层190,金属层190可选择钨或其它常用的字线材料,如图18所示。
对金属层190进行回刻,使金属层190低于衬底110上表面,即在栅极沟槽140和浅沟道隔离结构180内形成字线190,在回刻的过程中,栅极沟槽140和浅沟道隔离结构180外的扩散阻挡层162也被去除;随后在字线190的表面形成保护层161,该保护层161用于保护字线190,优选氮化硅材料,如图9所示。
在保护层161表面刻蚀形成位线接触孔170;位线接触孔170贯穿保护层161,且露出衬底110,补偿离子才能够通过位线接触孔170注入衬底110中,从而在有源区121内扩散形成离子补偿区域150,如图10所示。
S380,如果所述栅极沟槽的深度满足预设条件时,则根据所述栅极沟槽的深度对所述衬底进行离子注入补偿,在所述栅极沟槽一侧的所述有源区内形成离子补偿区域。
基于同一发明构思,本发明实施例还提供一种半导体结构,采用本发明任意实施例所提供的半导体结构的制作方法制作得到,具备该方法相应的有益效果。
本发明实施例提供了一种半导体结构,其结构如图5所示,半导体结构100包括:衬底110、栅极沟槽140和离子补偿区域150。有源区121位于衬底110中;离子补偿区域150位于深度满足预设条件的栅极沟槽140一侧的有源区121内。
本发明实施例中,通过根据栅极沟槽140的深度对衬底110进行离子注入补偿,在栅极沟槽140的一侧的有源区121内形成离子补偿区域150,离子补偿区域150对源漏区中可移动电荷的密度起到控制作用,使栅极沟槽140两侧的源漏区更难导通,因此提高了阈值电压,补偿了由于栅极沟槽140的深度过浅导致的阈值电压的降低,避免由栅极沟槽140的深度变异造成的半导体结构性能劣化,改善半导体存储器的性能。
可选的,本发明实施例提供了又一种半导体结构,其结构如图10所示,半导体结构100还包括位线接触孔170,位线接触孔170在衬底110上的垂直投影与离子补偿区域150在衬底110上的垂直投影至少部分交叠。由于离子注入需在衬底110上进行,才能确保注入离子在衬底110上形成离子补偿区域,因此需要利用刻蚀等工艺露出衬底110,以进行补偿离子的注入,本发明实施例通过位线接触孔170进行补偿离子注入,无需增加额外的工艺,简化了工艺过程。
可选的,结合图5和图10,半导体结构100还包括浅沟道隔离结构180,相邻两个浅沟道隔离结构180之间设置有栅极沟槽140,且栅极沟槽140的深度h小于浅沟道隔离结构180的深度Z;半导体结构100还包括位于栅极沟槽140和浅沟道隔离结构180表面的栅氧化层163和扩散阻挡层162;位于栅极沟槽140和浅沟道隔离结构180内的字线190;位于字线190表面的保护层161,位线接触孔170贯穿保护层161且露出衬底110。
基于同一发明构思,本发明实施例还提供一种半导体存储器,包括本发明任意实施例所提供的半导体结构,具备该半导体结构相应的功能和有益效果。
图19为本发明实施例提供的一种半导体存储器的结构示意图。如图19所示,半导体存储器200包括多个半导体结构100。
本发明实施例提供的半导体存储器200具备上述实施例中半导体结构100所具有的有益效果,此处不再赘述。
上述仅为本发明的较佳实施例及所运用的技术原理。本发明不限于这里的特定实施例,对本领域技术人员来说能够进行的各种明显变化、重新调整及替代均不会脱离本发明的保护范围。因此,虽然通过以上实施例对本发明进行了较为详细的说明,但是本发明不仅仅限于以上实施例,在不脱离本发明构思的情况下,还可以包括更多其他等效实施例,而本发明的范围由权利要求的范围决定。
Claims (10)
1.一种半导体结构的制作方法,其特征在于,包括:
提供衬底并对所述衬底进行离子注入,形成有源区;
在有源区中形成沟道调节掺杂区;
在所述衬底表面形成栅极沟槽,所述沟道调节掺杂区位于所述栅极沟槽下方;
测量所述栅极沟槽的深度;
如果所述栅极沟槽的深度满足预设条件时,则根据所述栅极沟槽的深度对所述衬底进行离子注入补偿,在所述栅极沟槽一侧的所述有源区内形成离子补偿区域。
2.根据权利要求1所述的半导体结构的制作方法,其特征在于,在所述栅极沟槽一侧的所述有源区内形成离子补偿区域,包括:
在所述栅极沟槽一侧的所述有源区内形成位线接触孔;
通过所述位线接触孔对所述衬底进行离子注入补偿,形成所述离子补偿区域。
3.根据权利要求1所述的半导体结构的制作方法,其特征在于,所述根据所述栅极沟槽的深度对所述衬底进行离子注入补偿,包括:
根据所述栅极沟槽的深度确定补偿离子的注入深度;
根据所述补偿离子的注入深度确定所述补偿离子的注入能量;
根据所述补偿离子的注入能量,对所述衬底进行离子注入补偿,形成所述离子补偿区域。
4.根据权利要求1所述的半导体结构的制作方法,其特征在于,所述预设条件为所述栅极沟槽的深度小于目标深度,且所述栅极沟槽的深度与所述目标深度的差值绝对值大于阈值标准差;
所述阈值标准差根据以所述目标深度为工艺参数制作而成的多个所述栅极沟槽的深度的统计结果确定。
5.根据权利要求2所述的半导体结构的制作方法,其特征在于,所述在所述衬底表面形成栅极沟槽,包括:
在所述衬底表面形成浅沟道隔离结构,将所述有源区分隔成若干块;
在所述衬底表面形成所述栅极沟槽,所述栅极沟槽的深度小于所述浅沟道隔离结构的深度。
6.根据权利要求5所述的半导体结构的制作方法,其特征在于,所述测量栅极沟槽的深度之后,还包括:
在所述栅极沟槽表面依次形成栅氧化层和扩散阻挡层;
在所述栅极沟槽内填充字线;
在所述字线和所述衬底的表面形成保护层;
所述在所述栅极沟槽一侧的有源区内形成位线接触孔包括:
刻蚀所述保护层形成所述位线接触孔;所述位线接触孔贯穿所述保护层,且露出所述衬底;所述位线接触孔位于同一块所述有源区内相邻两个所述栅极沟槽之间。
7.一种半导体结构,其特征在于,采用权利要求1-6任一项所述半导体结构的制作方法制作得到,包括:
衬底、栅极沟槽、沟道调节掺杂区和离子补偿区域;
有源区位于所述衬底中;
所述离子补偿区域位于深度满足预设条件的所述栅极沟槽一侧的所述有源区内,所述沟道调节掺杂区位于所述栅极沟槽下方。
8.根据权利要求7所述的半导体结构,其特征在于,所述半导体结构还包括位线接触孔,所述位线接触孔在所述衬底上的垂直投影与所述离子补偿区域在所述衬底上的垂直投影至少部分交叠。
9.根据权利要求8所述的半导体结构,其特征在于,所述半导体结构还包括浅沟道隔离结构,所述浅沟道隔离结构位于所述衬底表面且将所述有源区分隔成若干块,且所述栅极沟槽的深度小于所述浅沟道隔离结构的深度;
所述半导体结构还包括:
位于所述栅极沟槽表面的栅氧化层和扩散阻挡层;
位于所述栅极沟槽内的字线;
位于所述字线和所述衬底表面的保护层,所述位线接触孔贯穿所述保护层且露出所述衬底,且所述位线接触孔位于同一块所述有源区内相邻两个所述栅极沟槽之间。
10.一种半导体存储器,其特征在于,包括权利要求7-9中任一项所述的半导体结构。
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