CN105374688B - 嵌入式晶体管 - Google Patents
嵌入式晶体管 Download PDFInfo
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- CN105374688B CN105374688B CN201410803553.0A CN201410803553A CN105374688B CN 105374688 B CN105374688 B CN 105374688B CN 201410803553 A CN201410803553 A CN 201410803553A CN 105374688 B CN105374688 B CN 105374688B
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- groove
- side wall
- insulating layer
- semiconductor devices
- dielectric
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- 239000003989 dielectric material Substances 0.000 claims description 26
- 239000011737 fluorine Substances 0.000 claims description 15
- 229910052731 fluorine Inorganic materials 0.000 claims description 15
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Classifications
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract
本发明提供了一种用于电器件(诸如,DRAM存储单元)的嵌入式晶体管及其制造方法。沟槽形成在衬底中并且栅介质和栅电极形成在衬底的沟槽内。源极/漏极区形成在位于沟槽的相对两侧的衬底中。在实施例中,源极/漏极区的一个连接至存储节点而源极/漏极区的另一个连接至位线。在本实施例中,栅电极可连接至字线以形成DRAM存储单元。可将电介质生长改性剂注入到沟槽的侧壁内以调整栅介质的厚度。
Description
相关申请的交叉引用
本申请是2011年10月13日提交的标题为“Embedded Transistor”的美国专利申请第13/273,012号的部分继续申请案,其全部内容结合于此作为参考。
技术领域
本发明总体涉及半导体领域,更具体地,涉及晶体管及其制造方法。
背景技术
通常,互补金属氧化物半导体(CMOS)晶体管包括栅电极和栅介质,其形成在衬底(通常为硅半导体衬底)上。通过将N型或P型杂质注入到衬底中而在栅电极的相对两侧上形成轻掺杂漏极。氧化物衬垫和一个或多个注入掩模(通常称为间隔件)邻近栅电极形成,并且实施额外的注入以完成源极/漏极区。然后,通过控制施加至栅电极的电压电平可控制流经源极/漏极区的电流。
在过去的几十年,CMOS晶体管尺寸的减小已提供了速度、性能、电路密度和每单元功能成本方面的持续改进。随着传统块体MOSFET的栅极长度的减小,源极和漏极越来越与沟道相互作用并且对沟道电势产生影响。因此,具有短栅极长度的晶体管遭受与栅极不能基本控制沟道的导通和关闭状态有关的问题。
发明内容
根据本发明的一个方面,提供了一种制造半导体器件的方法,该方法包括:将电介质生长改性剂注入到沟槽的第一侧壁内;以及沿着沟槽的第一侧壁和底部形成栅极绝缘层,其中,栅极绝缘层沿着沟槽的第一侧壁以不同于沿着沟槽的底部的速率形成,使得栅极绝缘层沿着沟槽的第一侧壁具有逐减的厚度。
优选地,电介质生长改性剂包括氟。
优选地,该方法还包括:将电介质生长改性剂注入到沟槽的不同于第一侧壁的第二侧壁内。
优选地,以大于零的第一角度实施将电介质生长改性剂注入到第一侧壁内。
优选地,第一角度大于沟槽的宽度除以沟槽的高度的反正切。
优选地,以与第一角度相对的第二角度将电介质生长改性剂注入到第二侧壁内。
优选地,沟槽具有不包括电介质生长改性剂的第二侧壁。
根据本发明的另一方面,提供了一种制造半导体器件的方法,该方法包括:以第一角度将第一电介质生长改性剂注入到沟槽的第一侧壁内;将第二电介质生长改性剂注入到沟槽的不同于第一侧壁的第二侧壁内,其中,以不同于第一角度的第二角度实施第二电介质生长改性剂的注入;以及沿着沟槽的底部、第一侧壁和第二侧壁生长栅极绝缘层,其中,栅极绝缘层沿着沟槽的底部具有第一厚度,第一厚度小于栅极绝缘层沿着第一侧壁和第二侧壁具有的第二厚度。
优选地,电介质生长改性剂包括氟。
优选地,第一角度大于沟槽的宽度除以沟槽的高度的反正切。
优选地,第二角度大于沟槽的宽度除以沟槽的高度的反正切并且与第一角度相对。
优选地,该方法还包括:将栅电极沉积在沟槽内。
优选地,生长栅极绝缘层包括原位蒸汽生成工艺。
优选地,生长栅极绝缘层包括化学汽相沉积工艺。
根据本发明的又一方面,提供了一种半导体器件,包括:沟槽,位于衬底中,沟槽包括第一侧壁、第二侧壁和底部;以及栅极绝缘层,内衬于沟槽的第一侧壁、第二侧壁和底部,其中,内衬于第一侧壁的栅极绝缘层具有从沟槽的顶部到沟槽的底部逐减的厚度。
优选地,内衬于第二侧壁的栅极绝缘层具有不变的厚度。
优选地,内衬于第二侧壁的栅极绝缘层具有从沟槽的顶部到沟槽的底部逐减的厚度。
优选地,该半导体器件还包括:位于第一侧壁内的第一浓度的电介质生长增强材料。
优选地,该半导体器件还包括:位于第二侧壁内的第二浓度的电介质生长增强材料。
优选地,沟槽的底部基本不包括电介质生长增强材料。
附图说明
为了更全面地理解本公开及其优势,现将结合附图所进行的以下描述作为参考,其中:
图1至图8示出了根据实施例的在制造嵌入式晶体管中的各种中间阶段;
图9示出了根据实施例的使用嵌入式晶体管的存储单元的平面图;
图10A和图10B是图9中示出的存储单元的截面图;
图11至图12示出了根据实施例的使用双面倾斜角注入的实施例;以及
图13至图14示出了根据实施例的使用单个倾斜角注入的实施例。
具体实施方式
下面详细讨论各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅是说明制造和使用本发明的具体方式,而不限制本发明的范围。贯穿本发明的各种视图和说明性实施例,相同的参考数字用于表示相同的元件。
首先参照图1,提供衬底110,衬底110具有形成在其上的第一图案化掩模112。衬底110可包括任意半导体材料并且可包括已知结构,例如,该已知结构包括有渐变层或掩埋层。在实施例中,衬底110包括可未掺杂或掺杂(例如,p型、n型、或它们的组合)的块状硅。可使用适用于半导体器件形成的其他材料。然而,在实施例中,衬底110是块状硅。
形成第一图案化掩模112以图案化下面的材料,诸如,下面的衬底110。在实施例中,第一图案化掩模112包括已被掩蔽、曝光和显影的光刻胶材料。通常,沉积、辐射(曝光)和使光刻胶材料显影以去除光刻材料的一部分,从而限定图1中所示的图案。剩余的光刻胶材料保护下面的材料免受诸如蚀刻的后续处理步骤的影响。
图1还示出了可选的硬掩模114。硬掩模114是防止在蚀刻工艺期间去除诸如衬底110的下面的结构的保护层。在某些情况下,由于要被图案化的材料、蚀刻工艺的持续时间、所用蚀刻剂的类型等,除了第一图案化掩模112以外,需要掩模。在衬底110是硅衬底的实施例中,一种这样合适的硬掩模114包括诸如氧化硅层的氧化物层和上面的诸如氮化硅(Si3N4)层的氮化物层。通过诸如在包括氧化物、H2O、NO或它们的组合的环境中的湿或干热氧化的任何氧化工艺,或通过使用正硅酸乙酯(TEOS)和氧气作为前体的化学汽相沉积(CVD)技术可形成氧化物层。例如,通过在O2、H2O、NO、它们的组合等的环境中的原位蒸汽生成(ISSG)工艺也可形成氧化物层。在实施例中,氧化物层的厚度为约至约通过使用硅烷和氨气作为前体气体的CVD技术可形成氮化物层。使用CHF3等离子体可图案化氮化物层,并且使用CF4等离子体可图案化氧化物层。
本领域一般技术人员会意识到,其他掩模材料和/或结构可用于形成第一图案化掩模112或/和硬掩模114。例如,可使用其他材料、单层、三层或更多层等。在可选实施例中,硬掩模可包括单个氮化硅层,而没有下面的氧化物层。
图2示出了根据实施例的已图案化衬底之后的衬底110。通过实施一次或多次蚀刻步骤可图案化衬底110,从而形成沟槽2161至2165(共同称为沟槽216),其中鳍218介于邻近的沟槽216之间。通过例如HBr/O2、HBr/Cl2/O2或SF6/Cl2等离子体可蚀刻衬底110。如下文将更详细地讨论的,鳍218将形成晶体管的源极/漏极区,而交替的沟槽将形成晶体管的栅电极。其他沟槽将形成例如浅沟槽隔离(STI)的隔离结构。
在图2所示的实施例中,沟槽216可具有约至约的深度D1(因此为鳍218的高度),并且鳍218可具有约至约的宽度W1。尽管本实施例中示出的鳍218的宽度W1相同,但是其他实施例可利用不同宽度的鳍218。如上所述,后续处理在鳍218的上部中形成源极/漏极区。因此,可调整尺寸(例如,鳍218的宽度和高度)以达到晶体管的理想电气特性。此外,应该注意,同一晶圆上的鳍可具有不同的宽度和深度。
此外,也可改变沟槽的宽度W2。如上所述,沟槽将成为栅电极和隔离沟槽。这样,可调整沟槽的宽度以改变栅极长度和隔离特性。例如,在一些实施例中希望提供比用于栅电极的沟槽更宽的隔离沟槽以提供邻近的器件之间的更大隔离特性。在其他实施例中,可期望栅电极的沟槽更宽。
图2也示出了第一图案化掩模112(见图1)的去除。例如,通过O2等离子体干剥离以及浓硫酸和过氧化氢的混合物可去除第一图案化掩模112。
现参照图3,在衬底110上方形成第一介电材料320,从而基本填充沟槽216。在实施例中,第一介电材料320包括可使用SiH4和O2混合物且通过高密度等离子体CVD沉积工艺而形成的氧化硅层。
如图3所示,根据实施例,平坦化第一介电材料320直至衬底110的顶面。例如,通过使用氧化层研磨液的化学机械抛光(CMP)工艺可平坦化第一介电材料320,其中,衬底110用作停止层。
图4示出了从沟槽216中选择的沟槽(诸如,沟槽2162和2164)去除第一介电材料320。在实施例中,通过下列步骤可选择性地从沟槽2162和2164去除第一介电材料320:形成并图案化掩模层(未示出)以保护沟槽2161、2163和2165中的第一介电材料320,而使沟槽2162和2164中的介电材料暴露。使用与以上参照图1和图2所示的蚀刻衬底110讨论的技术相似的光刻技术可图案化掩模。例如,可形成光刻胶材料、根据期望的图案(例如,暴露沟槽2162和2164)曝光光刻胶材料以及使光刻胶材料显影。此外,还可使用诸如以上讨论的硬掩模。
在第一介电材料320是氧化硅且衬底110是硅的实施例中,通过使用对衬底110和第一介电材料320具有高蚀刻选择性的蚀刻剂(诸如,CF4或C2F6)的各向异性干蚀刻工艺可去除第一介电材料320。通过这种方式,在蚀刻或去除第一介电材料320的同时,衬底110相对不受影响。
图5示出了根据实施例的沿沟槽2162和2164的表面形成栅极绝缘层526以及在沟槽2162和2164内形成栅电极材料528之后的衬底110。通常,栅极绝缘层526防止源极/漏极区和栅电极之间的电子耗尽。在实施例中,栅极绝缘层526包括氧化物层,其通过诸如在包括氧化物、H2O、NO或它们的组合的环境中的湿或干热氧化的氧化工艺、通过在O2、H2O、NO、它们的组合等的周围环境中的原位蒸汽生成(ISSG)工艺,或者通过使用正硅酸乙酯(TEOS)和氧气作为前体的化学汽相沉积(CVD)技术形成氧化物层。还可使用包括高k介电材料(诸如,HfO2、HfSiO2、ZnO、ZrO2、Ta2O5、Al2O3等)的其他材料和诸如原子层沉积(ALD)、原子汽相沉积(AVD)等的其他工艺。在实施例中,栅极绝缘层526具有介于约和约之间的厚度。应该注意到,仅为了说明的目的,图5示出了栅极绝缘层526没有在第一介电材料320上方延伸。栅极绝缘层526是否延伸在第一介电材料320上方至少部分地取决于用于形成栅极绝缘层526的方法。例如,热工艺通常导致与图5所示的相似的实施例,而当使用例如CVD工艺或ISSG工艺形成栅极绝缘层526时,栅极绝缘层526可在第一介电材料320上方延伸。
可选择地,可实施注入以帮助或阻止栅极绝缘层526的形成。例如,可实施氮注入以阻止选择区域(诸如,沟槽的底部)中的氧化物生长,而可实施氟注入以提高氧化物生长。在一实施例中,可以以垂直于衬底的上表面的角度来实施氮注入。在该实施例中,沟槽的侧壁的注入将少于沟槽的底面的注入。沿着沟槽的底部的氮注入阻止氧化物生长,从而导致相比于沟槽的侧壁,沿着沟槽的底部形成的栅极绝缘层更薄。在另一个实施例中,可调整沿着侧壁注入氮的注入角度,从而导致沿着底部的栅极绝缘层厚于沿着侧壁的栅极绝缘层。使用氟注入来提高栅极绝缘层的相对生长速率可获得相似的效果,例如,沿着沟槽的底部的相对较薄或较厚的栅极绝缘层。
应该注意到,在形成栅极绝缘层之前可掺杂衬底110以制备例如沟道区。例如,在形成具有p型掺杂的源极/漏极区的p型晶体管中,在形成栅极绝缘层526之前,可将诸如磷、砷、氮、锑等的n型掺杂剂注入衬底110的沟道区(沿着沟槽2162和2164的侧壁和底部)。类似地,在形成具有n型掺杂源极/漏极区的n型晶体管中,可将诸如硼、铝、镓、铟等的p型掺杂剂注入衬底的沟道区内。可调整注入角度以确保沿着沟槽2162和2164的侧壁区以及沟槽2162和2164的底部的适当注入。可选地,在形成沟槽之前,可通过分别形成其中形成有沟槽2162和2164的n阱或p阱来掺杂衬底110。
例如,可通过在相对于沟槽2162和2164的底面的约0°至约5°的角度、相对于沟槽2162和2164的垂直侧壁的介于约-25°至约25°之间的角度、约1E12至约3E13原子/平方厘米的剂量以及约20KeV至约400KeV的能量下,注入磷离子来形成p型晶体管。可通过在相对于沟槽2162和2164的底面的约0°至约5°的角度、相对于沟槽2162和2164的垂直侧壁的介于约-25°至约25°之间的角度、约1E12至约3E13原子/平方厘米的剂量以及约5KeV至约300KeV的能量下,注入硼离子来形成n型晶体管。
栅电极材料528包括诸如金属(例如,钽、钛、钼、钨、铂、铝、铪、钌)、金属硅化物(例如,硅化钛、硅化钴、硅化镍、硅化钽)、金属氮化物(例如,氮化钛、氮化钽)、掺杂多晶硅的导电材料、其他导电材料、或它们的组合。在一个实例中,沉积非晶硅并且将其重结晶以产生多晶硅(poly-silicon)。在实施例中,通过沉积(例如,CVD、低压CVD(LPCVD)等)覆盖衬底110并且填充沟槽2162和2164的共形层而形成栅电极层。之后,可实施诸如CMP工艺的平坦化工艺以去除过量的材料,从而形成与图5所示相似的结构。
可掺杂地或未掺杂地沉积栅电极材料528。例如,在实施例中,通过沉积多晶硅层可形成栅电极材料528,并且一旦施加栅电极材料528,多晶硅可掺杂有例如磷离子(或其他P型掺杂剂)以形成PMOS器件或掺杂有硼(或其他N型掺杂剂)以形成NMOS器件。例如,还可通过原位掺杂的多晶硅的炉沉积(furnace deposition)来沉积多晶硅。可选地,例如,栅电极材料528可包括多晶硅金属合金或包括诸如钨、镍、钛和氮化钽等的金属的金属栅极。
图6示出了开槽栅电极材料528(见图5)以形成沿着沟槽2162和2164的底部的栅电极630。在栅电极材料528包括多晶硅的实施例中,可使用干蚀刻或湿蚀刻来实施开槽。在使用干蚀刻的情况下,工艺气体可包括CF4、CHF3、NF3、SF6、Br2、HBr、Cl2或它们的组合。可以可选择地使用诸如N2、O2或Ar的稀释气体。在使用湿蚀刻的情况下,化学物质可包括NH4OH:H2O2:H2O(APM)、NH2OH、KOH、HNO3:NH4F:H2O等。在实施例中,使栅电极材料528凹进约至约
现参照图7,在衬底110上方形成第二介电层732,从而填充沟槽2162和2164中的栅电极630之上的凹槽。可使用以上参照第一介电材料320讨论的相似的工艺且由相似的材料形成第二介电层732。在沉积第二介电层732之后,可使用例如CMP工艺的平坦化工艺去除过量的材料,从而形成与图7所示结构相似的结构。在实施例中,该平坦化工艺暴露鳍218。
图8示出了根据实施例的源极/漏极区834的形成。通过注入n型或p型掺杂剂可掺杂源极/漏极区834。例如,通过以约1E15至约5E15原子/平方厘米的剂量和约20KeV至约100KeV的能量注入诸如磷离子的n型离子可形成n型晶体管。通过以约1E15至约5E15原子/平方厘米的剂量和约10KeV至约50KeV的能量注入诸如硼离子的p型离子可形成p型晶体管。
此外,图8还示出了根据实施例的可选的硅化物区836。硅化物区836降低了源极/漏极区834和在后续处理步骤中形成的接触件之间的接触电阻。例如,通过经由等离子体汽相沉积(PVD)工序沉积诸如钛、镍、钨、或钴的金属层(未示出)而形成硅化物区836。退火工序使得金属层与源极/漏极区834的衬底110(例如,硅)发生反应以形成金属硅化物。金属层的位于其他区域的各部分(诸如,第一介电材料320(例如,隔离结构)和第二介电材料732)仍未发生反应。例如,通过湿蚀刻工序可实现金属层的未反应部分的选择性去除。如果需要改变硅化物区836的相位,可使用额外的退火周期,这样可导致较低的电阻。
如能够意识到的,以上段落描述了可用于各种应用中的嵌入式晶体管的实施例。例如,图9、图10A和图10B示出了将以上公开的嵌入式晶体管用作DRAM存储单元中的存取晶体管的实施例。具体地,图9示出了多个DRAM存储单元的平面图,图10A示出了沿着图9的线A-A’截取的截面图,并且图10B示出了沿着图9的线B-B’截取的截面图。虚线框950表示单个存储单元。
存储单元950包括形成在例如第一金属化层M1中的位线952,第一金属化层M1具有将位线952电连接至下面的存取晶体管的源极/漏极区834中的一个的位线接触件954。存取晶体管的源极/漏极区834中的另一个通过存储节点接触件958电连接至存储节点956。例如,存储节点956可以是金属绝缘体金属(MIM)电容器、平面电容器、U型电容器、垂直电容器、水平电容器、非电容器存储结构等。栅电极630电连接至字线(WL)。
应该意识到,诸如以上讨论的一些实施例利用单个掩模和单次蚀刻工艺来形成隔离沟槽和嵌入式栅电极。通过这种方式,本文公开的使用自对准工艺的实施例避免了在使用单独的掩模和多次蚀刻工艺来形成隔离沟槽和栅电极沟槽的其他方法中可出现的未对准问题。应该相信,这些实施例降低了字线干扰问题。
本文公开的实施例还允许布局设计师具有较大的自由。例如,与各鳍之间的节距限定了栅极长度相反,沟槽的深度限定了栅极长度,从而可能允许在没有增加节距的情况下调节栅极长度。
图11示出了沿着沟槽216的侧壁可调整栅极绝缘层526(在图11中未示出,但是在下面参照图12的本实施例中示出和讨论)的厚度的进一步实施例。在图11开始的实施例中,已形成鳍218和沟槽216并且一些沟槽已填充有第一介电材料320(如以上参照图1至图3所述)。一旦形成,使用包括第一注入工艺(图11中用标示为1101的箭头表示)和第二注入工艺(图11中用标示为1103的箭头表示)的双面倾斜角注入以将电介质生长改性剂主要注入到沟槽216的侧壁。此外,通过使用一系列成角度注入工艺,几乎没有将电介质生长改性剂注入到沟槽216的底部。在实施例中,电介质生长改性剂可以是诸如氟的电介质生长增强剂或诸如氮的电介质生长抑制剂。
在电介质生长改性剂是电介质生长增强剂的实施例中,当将电介质生长改性剂主要注入到沟槽216的侧壁内时,栅极绝缘层526将沿着侧壁较快生长并且沿着沟槽216的侧壁比沿着沟槽216的底部形成更厚的栅极绝缘层526。可选地,在电介质生长改性剂为电介质生长抑制剂的实施例中,栅极绝缘层526将沿着侧壁较慢生长并且沿着沟槽216的侧壁比沿着沟槽216的底部形成更薄的栅极绝缘层526。
在实施例中,第一注入工艺1101以第一角度θ1注入电介质生长改性剂,使得电介质生长改性剂被主要注入沟槽的侧壁并且避免了模板效应(shuttering effect)。例如,在鳍218具有宽度为W2的间隔并且沟槽216具有深度为D1的实施例中,以大于宽度W2除以深度D1的反正切的第一角度θ1(例如,θ1>tan-1(W2/D1))实施第一注入工艺1101。通过使用大于宽度W2除以深度D1的反正切的角度,电介质生长改性剂将被主要注入到沟槽216的侧壁内而不是沟槽216的底部内。
在电介质生长改性剂是氟的实施例中,第一注入工艺1101可注入氟并且在沟槽216的侧壁内形成第一电介质生长改性剂区1105。在实例中,可形成具有介于约1E13cm2和约1E15cm2(诸如,约1E14cm2)之间的电介质生长改性剂(例如,氟)的浓度的第一电介质生长改性剂区1105。
同样地,可在与第一注入工艺1101相反的方向上实施第二注入工艺1103,以将电介质生长改性剂注入沟槽216的与第一注入工艺1101相对的侧壁。在该实施例中,第二注入工艺1103可以以与第一角度θ1相对的第二角度θ2注入氟。第二角度θ2可类似地基于宽度W2和深度D1,诸如大于宽度W2除以深度D1的反正切(例如,θ2>tan-1(W2/D1)),但是为了将电介质生长改性剂注入至沟槽216的与第一注入工艺1101相对的侧壁,第二角度θ2与第一角度θ1方向相反。
可以以独立的工艺分别实施第一注入工艺1101和第二注入工艺1103,衬底110在第一注入工艺1101和第二注入工艺1103之间可改变位置。可选地,可以以单次工艺实施第一注入工艺1101和第二注入工艺1103,其中,在工艺期间转动衬底110,使得沟槽216的相对两个侧壁均暴露于注入工艺。可选择使用注入电介质生长改性剂的任意合适方法,并且所有这样的方法完全都包括在实施例的范围内。
在电介质生长改性剂为氟的实施例中,第二注入工艺1103可注入氟并且在沟槽216的侧壁内形成第二电介质生长改性剂区1107。在实例中,可形成具有介于约1E13cm2和约1E15cm2(诸如,约1E14cm2)之间的电介质生长改性剂(例如,氟)的浓度的第二电介质生长改性剂区1107。
图12示出了一旦已实施第一注入工艺1101和第二注入工艺1103以形成第一电介质生长改性剂区1105和第二电介质生长改性剂区1107,就可形成如以上参照图5所述的栅极绝缘层526。例如,栅极绝缘层526可以为氧化物层,通过诸如在包括氧化物、H2O、NO或它们的组合的环境中的湿或干热氧化的氧化工艺、在O2、H2O、NO、它们的组合等的周围环境中的原位蒸汽生成(ISSG)工艺,或者通过使用正硅酸乙酯(TEOS)和氧气作为前体的化学汽相沉积(CVD)技术可形成氧化物层,但是可选择使用任意合适的工艺和材料。
然而,由于第一电介质生长改性剂区1105和第二电介质生长改性剂区1107主要位于沟槽216的侧壁中,所以栅极绝缘层526将沿着沟槽216的侧壁(此处具有较高的氟浓度)以快于沿着沟槽216的底部(此处具有较低的氟浓度,如果还有的话)的速率生长。这样,沿着沟槽216的侧壁的栅极绝缘层526将厚于沿着底部的栅极绝缘层526,并且从沟槽216的顶部到沟槽216的底部逐渐减小。
例如,在电介质生长改性剂为氟的实施例中,沿着沟槽216的侧壁的栅极绝缘层526在沟槽216的顶部可具有介于约至约之间的第一厚度T1。沿着侧壁的栅极绝缘层526在沟槽216的底部还可具有小于约的第二厚度T2。换言之,沿着侧壁的栅极绝缘层526的厚度将从沟槽216的顶部到沟槽216的底部减小。沿着沟槽216的底部的栅极绝缘层526还将具有第三厚度T3,第三厚度T3小于第一厚度T1并且小于或等于第二厚度T2,诸如小于约
一旦已形成栅极绝缘层526,就可在栅极绝缘层526上方形成栅电极630,第二介电层732可形成在栅电极630上方,源极/漏极区834可形成在鳍218(图12中用标示为834的虚线表示)中,可形成可选择硅化物区836(未在图14中单独示出),并且可形成位线接触件954、位线952、存储节点接触件958和存储节点956。在实施例中,可形成如以上参照图5至图10B所述的栅电极630、第二介电层732、源极/漏极区834、可选择硅化物区836、位线接触件954和存储节点956。然而,可选择使用任意其他合适的方法和材料。
通过使用电介质生长改性剂,可更好地控制栅极绝缘层526的形成,以产生期望的结果。例如,通过沿着侧壁增加栅极绝缘层526的厚度,栅极绝缘层526将具有更大的等效氧化物厚度并且在物理特性上也更厚。这样,可降低栅致漏极泄漏(GIDL),并且因为在沟槽216的底部处的栅极绝缘层厚度仍然较薄,所以亚阈值泄漏(Isoff)无缺陷。此外,使用该工艺,对沟道迁移率没有不期望的副作用。
图13示出了形成的栅极绝缘层526(图13中未示出,但下面参照图14示出和讨论)沿着沟槽216的侧壁具有逐减的厚度。在本实施例中,如以上参照图11所述,实施第一注入工艺1101。例如,将电介质生长改性剂注入沟槽216的侧壁内以形成第一电介质生长改性剂区1105,并且以第一角度θ1实施注入,这其中考虑了宽度W2除以深度D1,从而将电介质生长改性剂主要注入至侧壁内而不是沿着沟槽216的底部注入。
然而,在本实施例中,将电介质生长改性剂注入一侧侧壁内(例如,使用第一注入工艺1101),而没有将电介质生长改性剂注入到相对侧壁内。例如,在本实施例中,可使用第一注入工艺1101以将电介质生长改性剂注入到沟槽216的一侧侧壁内。然而,不是在第一注入工艺1101之后进行第二注入工艺1103,而是没有实施第二注入工艺1103,因此将电介质生长改性剂注入到沟槽216的单侧侧壁内,使得另一侧壁基本不包括电介质生长改性剂,从而在沟槽216的单侧侧壁中(以及还沿着鳍218的顶部)形成第一电介质生长改性剂区1105。
图14示出了一旦已实施第一注入工艺1101(但不是第二注入工艺1103),可形成如以上参照图5所述的栅极绝缘层526。例如,栅极绝缘层526可以为氧化物层,通过诸如在包括氧化物、H2O、NO或它们的组合的环境中的湿或干热氧化的氧化工艺、在O2、H2O、NO、它们的组合等的周围环境中的原位蒸汽生成(ISSG)工艺,或者通过使用正硅酸乙酯(TEOS)和氧气作为前体的化学汽相沉积(CVD)技术形成氧化物层,但是可选择使用任意合适的工艺和材料。
然而,由于在沟槽216的一侧侧壁内存在有电介质生长改性剂,所以栅极绝缘层526将以不同的(例如,较快的)速率沿着沟槽216的已经注入有电介质生长改性剂的侧壁生长并且以不一样快的速率沿着沟槽216的相对侧壁和底部生长。这样,栅极绝缘层526的厚度将沿着侧壁从沟槽216的顶部到沟槽216的底部减小。例如,在沿着注入有电介质生长改性剂的侧壁的沟槽216的顶部处,栅极绝缘层526可具有第一厚度T1,而在沿着侧壁的邻近沟槽216的底部处,栅极绝缘层526可具有第二厚度T2。此外,在本实施例中,沿着沟槽216的底部和另一侧壁(未注入有电介质生长改性剂的侧壁)的栅极绝缘层526可具有第三厚度T3。
一旦已经形成栅极绝缘层526,就可在栅极绝缘层526上方形成栅电极630,第二介电层732可形成在栅电极630上方,源极/漏极区834可形成在鳍218(在图14中由标示为834的虚线表示)中,可形成可选的硅化物区836(图14中未单独示出),并且可形成位线接触件954、位线952、存储节点接触件958和存储节点956。在实施例中,可形成如以上参照图5至图10B所述的栅电极630、第二介电层732、源极/漏极区834、可选择硅化物区836、位线接触件954和存储节点956。然而,可选择使用任意其他合适的方法和材料。
通过沿着沟槽216的侧壁中的一个使用电介质生长改性剂,可以更好地控制栅极的形成,使得在源极/漏极区834的一个上(例如,嵌入式晶体管的源极线节点上)可形成较厚的电介质,而在源极/漏极区834的另一个(例如,位线节点)上不具有较厚的电介质。这样,可实现源极线节点上具有较厚的电介质的益处(例如,GIDL减小),而避免了在位线节点上电介质较厚时驱动电流的劣化。
根据实施例,提供了一种制造半导体器件的方法,其包括将电介质生长改性剂注入到沟槽的第一侧壁内。沿着沟槽的第一侧壁和底部形成栅极绝缘层,其中,沿着沟槽第一侧壁以不同于沿着沟槽的底部的速率形成栅极绝缘层,使得栅极绝缘层沿着沟槽的第一侧壁具有逐减的厚度。
根据另一个实施例,提供了一种制造半导体器件的方法,其包括将第一电介质生长改性剂以第一角度注入至沟槽的第一侧壁。将第二电介质生长改性剂注入到沟槽的不同于第一侧壁的第二侧壁内,其中,以不同于第一角度的第二角度实施第二电介质生长改性剂的注入。沿着沟槽的底部、第一侧壁和第二侧壁生长栅极绝缘层,其中,栅极绝缘层沿着沟槽的底部具有第一厚度,该第一厚度小于栅极绝缘层沿着第一侧壁和第二侧壁具有的第二厚度。
根据又一实施例,提供了一种包括位于衬底中的沟槽的半导体器件,该沟槽包括第一侧壁、第二侧壁和底部。栅极绝缘层内衬于沟槽的第一侧壁、第二侧壁和底部,其中,内衬于第一侧壁的栅极绝缘层具有从沟槽的顶部到沟槽的底部的逐减的厚度。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明的主旨和范围的情况下,可以做出各种不同的改变、替换和更改。而且,本申请的范围并不旨在限于本说明书中描述的工艺、机器、制造、物质组分、工具、方法和步骤的特定实施例。作为本领域普通技术人员将容易从本发明理解,根据本发明,可以利用现有的或今后开发的实施与在此所介绍的相应实施例基本相同的功能或获得基本相同的结果的工艺、机器、制造、物质组分、工具、方法或步骤。因此,所附权利要求旨在包括将这样的工艺、机器、制造、物质组分、工具、方法或步骤包括在它们的范围内。
Claims (19)
1.一种制造半导体器件的方法,所述方法包括:
提供具有第一组沟槽和第二组沟槽的衬底;
将介电材料设置在所述第一组沟槽和所述第二组沟槽中;
去除所述第二组沟槽中的所述介电材料;
将电介质生长改性剂注入到第二组沟槽中的第一沟槽的第一侧壁内;以及
沿着所述第二组沟槽中的第一沟槽的第一侧壁和底部形成栅极绝缘层,其中,所述栅极绝缘层沿着所述第一侧壁以不同于沿着所述底部的速率形成,使得所述栅极绝缘层沿着所述第一侧壁具有逐减的厚度。
2.根据权利要求1所述的制造半导体器件的方法,其中,所述电介质生长改性剂包括氟。
3.根据权利要求1所述的制造半导体器件的方法,还包括:将所述电介质生长改性剂注入到所述第二组沟槽中的第一沟槽的不同于所述第一侧壁的第二侧壁内。
4.根据权利要求3所述的制造半导体器件的方法,其中,以大于零的第一角度实施将所述电介质生长改性剂注入到所述第一侧壁内。
5.根据权利要求4所述的制造半导体器件的方法,其中,所述第一角度大于所述第一沟槽的宽度除以所述第一沟槽的高度的反正切。
6.根据权利要求4所述的制造半导体器件的方法,其中,以与所述第一角度相对的第二角度将所述电介质生长改性剂注入到所述第二侧壁内。
7.根据权利要求1所述的制造半导体器件的方法,其中,所述第二组沟槽中的第一沟槽具有不包括所述电介质生长改性剂的第二侧壁,其中,所述第二侧壁不同于所述第一侧壁。
8.一种制造半导体器件的方法,所述方法包括:
在衬底中形成第一沟槽和第二沟槽;
通过第一介电材料层填充所述第一沟槽和第二沟槽;
从所述第二沟槽中去除所述第一介电材料层,其中,在去除所述第一介电材料层之后,暴露所述第二沟槽的底部;
以第一角度将第一电介质生长改性剂注入到所述第二沟槽的第一侧壁内;
将第二电介质生长改性剂注入到所述第二沟槽的不同于第一侧壁的第二侧壁内,其中,以不同于所述第一角度的第二角度实施所述第二电介质生长改性剂的注入;以及
沿着所述第二沟槽的底部、所述第一侧壁和所述第二侧壁生长栅极绝缘层,其中,所述栅极绝缘层沿着所述第二沟槽的底部具有第一厚度,所述第一厚度小于栅极绝缘层沿着所述第一侧壁和所述第二侧壁具有的第二厚度。
9.根据权利要求8所述的制造半导体器件的方法,其中,所述电介质生长改性剂包括氟。
10.根据权利要求8所述的制造半导体器件的方法,其中,所述第一角度大于所述第二沟槽的宽度除以所述第二沟槽的高度的反正切。
11.根据权利要求10所述的制造半导体器件的方法,其中,所述第二角度大于所述第二沟槽的宽度除以所述第二沟槽的高度的反正切并且与所述第一角度相对。
12.根据权利要求8所述的制造半导体器件的方法,还包括:将栅电极沉积在所述第二沟槽内。
13.根据权利要求8所述的制造半导体器件的方法,其中,生长所述栅极绝缘层包括原位蒸汽生成工艺。
14.根据权利要求8所述的制造半导体器件的方法,其中,生长所述栅极绝缘层包括化学汽相沉积工艺。
15.一种半导体器件,包括:
第一沟槽,填充有第一介电材料层;
第二沟槽,位于衬底中,所述第二沟槽包括第一侧壁、不同于所述第一侧壁的第二侧壁和底部;以及
栅极绝缘层,内衬于所述第二沟槽的所述第一侧壁、所述第二侧壁和所述底部,其中,内衬于所述第一侧壁的所述栅极绝缘层具有从所述第二沟槽的顶部到所述第二沟槽的底部逐减的厚度,
第一浓度的电介质生长增强材料,位于所述第一侧壁内。
16.根据权利要求15所述的半导体器件,其中,内衬于所述第二侧壁的所述栅极绝缘层具有不变的厚度。
17.根据权利要求15所述的半导体器件,其中,内衬于所述第二侧壁的所述栅极绝缘层具有从所述第二沟槽的顶部到所述第二沟槽的底部逐减的厚度。
18.根据权利要求15所述的半导体器件,还包括:位于所述第二侧壁内的第二浓度的所述电介质生长增强材料。
19.根据权利要求18所述的半导体器件,其中,所述第二沟槽的底部基本不包括所述电介质生长增强材料。
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