TW201413033A - 形成可伸展性鎢膜與可壓縮性鎢膜的方法 - Google Patents

形成可伸展性鎢膜與可壓縮性鎢膜的方法 Download PDF

Info

Publication number
TW201413033A
TW201413033A TW102123248A TW102123248A TW201413033A TW 201413033 A TW201413033 A TW 201413033A TW 102123248 A TW102123248 A TW 102123248A TW 102123248 A TW102123248 A TW 102123248A TW 201413033 A TW201413033 A TW 201413033A
Authority
TW
Taiwan
Prior art keywords
tungsten
substrate
tungsten film
compressible
extensible
Prior art date
Application number
TW102123248A
Other languages
English (en)
Other versions
TWI605146B (zh
Inventor
Feng Chen
Tsung-Han Yang
Ju-Wen Gao
Roey Shaviv
Raashina Humayun
de-qi Wang
Original Assignee
Novellus Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Novellus Systems Inc filed Critical Novellus Systems Inc
Publication of TW201413033A publication Critical patent/TW201413033A/zh
Application granted granted Critical
Publication of TWI605146B publication Critical patent/TWI605146B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/18Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34Nitrides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • C23C16/45527Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
    • C23C16/45536Use of plasma, radiation or electromagnetic fields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864Thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883Post-treatment or after-treatment of the conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7845Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Electromagnetism (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

本發明描述用於沉積可伸展性或可壓縮性鎢膜的方法、設備和系統。在一實施態樣中,一種方法包含提供基板至腔室。該基板具有一場區和從該場區凹陷之特徵部。接著該基板係暴露至有機金屬鎢前驅體。未吸附到基板上的有機金屬鎢前驅體係從腔室中移除。該基板係遭受第一處理,包含熱處理或電漿處理,以形成鎢層於該基板上。處理基板後,殘餘的氣體係從該腔室中移除。該基板上之該鎢層係遭受第二處理,包含熱處理或電漿處理。

Description

形成可伸展性鎢膜與可壓縮性鎢膜的方法
本發明關於一種形成可伸展性鎢膜與可壓縮性鎢膜的方法。
使用化學氣相沉積(CVD)技術以沉積鎢膜是許多半導體製造處理中不可或缺的一部分。鎢膜可用以作為低電阻的電性連接,其形式可為水平內連線、相鄰金屬層之間的介層窗、以及矽基板上的第一金屬層和元件之間的接觸窗。在習知的鎢沈積處理中,晶圓係於真空腔室中加熱至處理溫度,且接著沉積作為種子層或成核層之非常薄的一部分鎢膜。此後,其餘的鎢膜(主體層)係沉積於該成核層上。習知地,鎢主體層係藉由在生長鎢層上之六氟化鎢(WF6)與氫氣(H2)的還原反應而形成。
本發明提供用於沉積可伸展性和可壓縮性鎢膜的方法、設備、和系統。本發明亦提供整合方法,其涉及沉積可伸展性及/或可壓縮性鎢膜,例如,以做為接觸窗及/或金屬閘極、及結合鎢膜之半導體元件。
在一些實施例中,一種方法包含提供基板於腔室。該基板具有一場區和從場區凹陷的特徵部。該基板係暴露至有機金屬鎢前驅體。未吸附到基板上的有機金屬鎢前驅體係從腔室中移除。該基板係遭受第一處理,包含熱處理或電漿處理,以形成鎢層於該基板上。處理基板後,殘餘的氣體係自腔室中移除。該基板上之鎢層係遭受第二處理,包含熱處理或電漿處理。
在一些實施例中,沉積設備包含腔室和控制器。該控制器包含程式指令,用以進行包含提供基板至腔室之處理。該基板具有一場區和從場區凹陷的特徵部。該基板係暴露至有機金屬鎢前驅體。未吸附到基板上的有機金屬鎢前驅體係從腔室中移除。該基板係遭受第一處理,包含熱處理或電漿處理,以形成鎢層於該基板上。處理基板後,殘餘的氣體係自腔室中移除。該基板上之鎢層係遭受第二處理,包含熱處理或電漿處理。
在一些實施例中,非暫時性電腦機器可讀媒體包含用於腔室之控制的程式指令。這些指令包含用以提供基板至腔室的碼。該基板具有一場區和從場區凹陷的特徵部。該基板係暴露至有機金屬鎢前驅體。未吸附到基板上的有機金屬鎢前驅體係從腔室中移除。該基板係遭受第一處理,包含熱處理或電漿處理,以形成鎢層於該基板上。處理基板後,殘餘的氣體係自腔室中移除。該基板上之鎢層係遭受第二處理,包含熱處理或電漿處理。
本揭露之這些和其它實施態樣係參照圖式進一步描述於下。
100‧‧‧PMOS元件
102‧‧‧基板
104‧‧‧導電閘極
106‧‧‧金屬
108‧‧‧閘極介電質
110‧‧‧通道區域
112‧‧‧源極
114‧‧‧汲極
116‧‧‧介電間隙壁
118‧‧‧介電膜
132‧‧‧平行應力
134‧‧‧垂直應力
136‧‧‧應變
138‧‧‧應力
140‧‧‧應力
142‧‧‧小接縫
200‧‧‧NMOS元件
202‧‧‧基板
204‧‧‧導電閘極
206‧‧‧金屬
208‧‧‧閘極介電質
210‧‧‧通道區域
212‧‧‧源極
214‧‧‧汲極
216‧‧‧介電間隙壁
218‧‧‧介電膜
232‧‧‧平行應力
234‧‧‧應力
236‧‧‧應變
242‧‧‧接縫
252‧‧‧向量
254‧‧‧向量
302‧‧‧接觸窗
304‧‧‧接觸窗
312‧‧‧平行應力
314‧‧‧垂直應力
316‧‧‧應力
320‧‧‧小接縫
402‧‧‧接觸窗
403‧‧‧小接縫
404‧‧‧接觸窗
412‧‧‧平行應力
414‧‧‧垂直應力
416‧‧‧應力
500‧‧‧半導體元件
502‧‧‧淺溝槽隔離特徵部
602‧‧‧操作
604‧‧‧操作
606‧‧‧操作
608‧‧‧操作
610‧‧‧操作
702‧‧‧操作
704‧‧‧操作
706‧‧‧操作
708‧‧‧操作
710‧‧‧操作
712‧‧‧操作
714‧‧‧操作
802‧‧‧操作
804‧‧‧操作
1800‧‧‧系統
1801‧‧‧晶圓來源模組
1803‧‧‧傳輸模組
1807‧‧‧單一或多站模組
1809‧‧‧多站反應器
1811‧‧‧站
1813‧‧‧站
1815‧‧‧站
1817‧‧‧站
1819‧‧‧大氣傳輸腔室
1821‧‧‧負載鎖室
1829‧‧‧系統控制器
1900‧‧‧沉積站
1901‧‧‧基座部
1902‧‧‧晶圓支架
1903‧‧‧噴淋頭
隨附圖式係併入本說明書中並構成本說明書之一部分,隨附圖式繪示所揭露之實施例,並與詳細說明共同用於解釋所揭露之實施例:圖1為根據一些實施例之PMOS元件的示意圖。
圖2為根據一些實施例之NMOS元件的示意圖。
圖3為根據一些實施例之PMOS元件的示意圖。
圖4為根據一些實施例之NMOS元件的示意圖。
圖5為根據一些實施例之半導體元件的示意圖。
圖6描繪一處理流程圖,顯示根據一些實施例的半導體元件之製造方法中的操作。
圖7描繪一處理流程圖,顯示根據一些實施例的鎢層之沉積方法中的操作。
圖8描繪一處理流程圖,顯示根據一些實施例的鎢之沉積方法中的操作。
圖9為適合用於根據各種實施例進行鎢沉積處理的處理系統之示意圖。
圖10為適合用於根據各種實施例進行鎢沉積處理的沉積站之示意圖。
簡介
在以下之詳細敘述中,提出許多具體實施例以提供對本揭露之實施例的深入了解。然而,如對於本技術領域中具有通常技術者顯而易見地,此等實施例可在缺少此等具體細節,或使用替代的元素或處理之情況下實施。在其它情況下,已為人所熟知之程式步驟及/或結構將不再贅述,以不非必要地妨礙本實施例之實施態樣。
在本申請中,用語「半導體晶圓」、「晶圓」、和「部分加工之積體電路」可互換使用。在本領域具有通常技術者將可理解,用語「部分加工之積體電路」可指在製造其上之積體電路的許多階段之任一者期間的矽晶圓。以下的詳細說明假定實施例係在晶圓上實施。然而,此等實施例並不局限於此。工件可為各種形狀、尺寸、和材料。不僅半導體晶圓,其他可利用此等實施例之優點的工件包含各種物品,例如印刷電路板及其相似物等。
為了增加電荷載體之活動性,矽的應變(straining)係用於90奈米(nm)及更小的技術節點中。此可藉由引入具有高拉伸應力的氮化物襯墊作為在前金屬介電質序列中的第一個步驟而達成。例如,氮化物襯墊膜係用於在金屬氧化物半導體場效應電晶體(MOSFET)中的應變矽;可伸展性膜係用於施加應變於N型金屬氧化物半導體場效應電晶體(NMOS),且可壓縮性膜係用於施加應變於P型金屬氧化物半導體場效應電晶體(PMOS)。施加應變於NMOS元件的通道區域,以增加在此區域中之矽的晶格常數,可增加在通道區域中之電子的活動性,從而提高元件性能。施加應變於PMOS元件的通道區域,以減少在此區域中之矽的晶格常數,可增加在通道區域中之電洞的活動性,從而提高元件性能。增加場效應電晶體元件中電荷載體,即電子或電洞,之活動性,使元件之操作更快, 且功率損耗更少。然而,在「後閘極(gate-last)」積體MOSFET元件和鰭式場效應電晶體(FinFET)元件中,高拉伸應力膜係位於距離矽一段距離處,並因此其對於元件性能之效應受到影響。
半導體元件之性能亦可藉由改變由金屬膜所引發之應力而改善,金屬膜係形成於半導體元件之閘極和接觸窗中。傳統上,鋁係用以作為半導體元件之後閘極整合中之閘極金屬,並且不顯著地施加應力於其下之通道區域。然而,作為在NMOS元件金屬閘極中之金屬的可壓縮性鎢膜或作為在PMOS元件金屬閘極中之金屬的可伸展性鎢膜,可用以提高元件性能,如以下所進一步描述。再者,半導體元件之接觸窗內部的鎢金屬膜之應力在傳統的半導體製造中並不重要。然而,在NMOS元件接觸窗中之可伸展性鎢膜,或在PMOS元件接觸窗中之可壓縮性鎢膜,可用以提高元件性能,亦如同以下所進一步描述者。
用以填充高深寬比特徵部之典型鎢膜可為高拉伸應力膜,以提供良好的一致性、插塞填充、以及對障壁層之附著力。對於厚度大於約2000埃的膜而言,此鎢膜中的應力水平之範圍為從約1.2×1010dyne/cm2(1.2吉帕)至約1.4×1010dyne/cm2(1.4吉帕)。用以作為內連線之典型的鎢膜可為低拉伸應力膜,此低拉伸應力膜可能不具有良好的階梯覆蓋性。對於厚度大於約2000埃的膜而言,在此低拉伸應力膜中的應力水平可能小於約1×1010dyne/cm2(1吉帕)。
本文所揭露之鎢沉積方法可產生可伸展性和可壓縮性膜,以實現在PMOS元件、NMOS元件、和其他半導體元件應用中的應變增強。可伸展性鎢膜和製造可伸展性鎢膜的方法係進一步描述於2011年2月3日提出申請之美國專利申請案第13/020,748號,其係併入於此作為參考。
元件
為了提高PMOS元件性能,應增加元件之閘極區域下方的通道區域中之電洞的活動性。此可藉由施加應變於閘極下方的矽以減少晶格常數而達成。在源極和汲極區域中的SiGe合金之晶格常數高於閘極下之矽的晶格常數,SiGe合金係常用於施加應變於閘極下的矽,以減少晶格常數。
相似地,填充閘極的拉伸應力金屬將施加一力在通道中之矽,從而降低晶格常數。因此,拉伸應力之金屬閘極,由於施加壓縮力至矽,因此有助於PMOS元件性能。
圖1為根據一些實施例之PMOS元件的示意圖。圖1所示的PMOS元件100包含基板102、被金屬106從基板102分離的導電閘極104、和閘極介電質108。基板102中的通道區域110分隔p型源極112和汲極114區域。介電間隙壁116與閘極區域相連。介電膜118完成所描繪的PMOS元件。需注意用於源極112和汲極114區域的接觸窗未顯示於圖1。在一些實施例中,基板102為矽。源極112和汲極114區域可包含SiGe合金,以在一些實施例中減少通道區域110中之基板的晶格常數。例如,砷化鎵和其它半導體材料亦可用以作為基板102、源極112,和汲極114。
在一些實施例中PMOS元件100之導電閘極104包含可伸展性鎢膜。圖1所示之向量顯示在PMOS元件100中之可伸展性鎢膜的作用。可伸展性鎢膜可展現不同的應力。在可伸展性鎢膜中的一些應力可在與基板102之平面平行的平面中(平行應力),且在可伸展性鎢膜中的一些應力可在與基板102之平面垂直的平面中(垂直應力)。可伸展性鎢膜的平行應力係由向量132所表示。可伸展性鎢膜的垂直應力係由向量134所表示。
基板102係受導電閘極104中之可伸展性鎢膜的平行應力所施加應變。鎢的平行應力132施加應變136於通道區域110上。平行應力132為可壓縮性並減少基板102的通道區域110之晶格常數,此增加了在通道區域中的電洞之活動性。應力132係加至由源極112和汲極114區域施加至通道區域上的應力138,源極和汲極區域包含例如SiGe。
在一些實施例中,可伸展性鎢膜的垂直應力在PMOS元件100中較不重要。鎢的垂直應力134係受到可壓縮性介電間隙壁之應力140所平衡,且對於基板102上的晶格常數可能沒有影響。如果存在,位於導電閘極104之可伸展性鎢膜的中心之小接縫142亦可有助於抵消垂直應力。因此,位於導電閘極104的底部之鎢的平行應力132,而非垂直應力134,對於基板102的晶格常數可具有顯著的影響。
為了提高NMOS元件性能,應增加閘極下方之通道中的電子之活動性。此可透過在一些實施例中封裝NMOS元件的可伸展性介電膜而達成。該介電膜施加應變於源極和汲極區域,此進而增加在通道中的晶格常數。可壓縮性或無應力金屬閘極將因此有助於NMOS性能。氮化鈦(TiN)或氮化鉭(TaN)可用於金屬閘極區域中,以幫助增加在通道中的晶格常數。同樣地,可壓縮性鎢金屬閘極將施加拉伸應力於通道中的矽上,從而增加通道中的晶格常數。
圖2為根據一些實施例之NMOS元件的示意圖。圖2所示之NMOS元件200包含基板202、被金屬206從基板202分離的導電閘極204、和閘極介電質208。基板202中的通道區域210分隔n型源極212和汲極214區域。介電間隙壁216與閘極區域相連。介電膜218完成所描繪的NMOS元件。需注意用於源極212和汲極214區域的接觸窗未顯示於圖2。
在一些實施例中介電膜218為可伸展性介電膜。圖2所示之向量顯示在NMOS元件200中之可伸展性介電膜的作用。可伸展性介電膜的平行應力232施加應力234於源極212和汲極214區域上。應力234從而產生應變236於通道區域210中,此增加了在通道區域中的電子之活動性。
在一些實施例中,NMOS元件200之導電閘極204包含可壓縮性鎢膜。在可壓縮性鎢膜中的一些應力可在與基板202之平面平行的平面中(平行應力),且在可壓縮性鎢膜中的一些應力可在與基板202之平面垂直的平面中(垂直應力)。可壓縮性鎢膜的平行應力係由向量252所表示。可壓縮性鎢膜的垂直應力係由向量254所表示。
基板202係受導電閘極204中之可壓縮性鎢膜的平行應力所施加應變。鎢的平行應力252施加應變236於通道區域210上。平行應力252為可拉伸性並增加基板202的通道區域210之晶格常數,此增加了在通道區域中的電子之活動性。例如,應力252係加至由可伸展性介電膜218施加至通道區域上的應力234。在一些實施例中,接縫242存在於閘極204中。
亦可分別使用可壓縮性或可伸展性金屬於到源極和汲極之接觸窗中,而實現藉由應力控制的PMOS和NMOS元件性能。鎢金屬是傳統且最廣泛使用的接觸窗金屬化金屬。調整源極和汲極接觸窗內部的鎢之應力,提供了增進元件性能之有效、成本中立、且可靠的方法。此做法與傳統的圓柱接觸窗金屬化和使用柱形接觸窗金屬化之新興技術相容。
圖3為根據一些實施例之PMOS元件的示意圖。圖3所示的PMOS元件100與圖1所示之PMOS元件100相同,另外增加用於源極區域112之接觸窗302和用於汲極區域114之接觸窗304。
在一些實施例中,接觸窗302和304包含可壓縮性鎢膜。圖3所示之向量表示可壓縮性鎢膜在PMOS元件100之接觸窗302和304中的作用。可壓縮性鎢膜可具備不同的應力。在可壓縮性鎢膜中的一些應力可在與基板102之平面平行的平面中(平行應力),且在可壓縮性鎢膜中的一些應力可在與基板102之平面垂直的平面中(垂直應力)。可壓縮性鎢膜的平行應力係由向量312所表示。可壓縮性鎢膜的垂直應力係由向量314所表示。位於接觸窗302和304的可壓縮性鎢膜的中心之小接縫320可有助於抵消垂直應力314。
基板102之源極112和汲極114區域係由位於接觸窗302和304中之可壓縮性鎢膜的平行應力所施加應變。鎢之平行應力312施加應力316於源極112和汲極114區域中。在源極112和汲極114區域中的應力316減少在通道區域110中之矽的晶格常數,此增加在通道區域中的電洞活動性。
PMOS元件的一些實施方案包含在閘極區域中的伸展性鎢膜。PMOS元件的一些實施例包含可壓縮性鎢膜,用於至源極區域和汲極區域之接觸窗。PMOS元件的一些實施例包含閘極區域中之可伸展性鎢膜,以及用於至源極區域和汲極區域的接觸窗之可壓縮性鎢膜。
圖4為根據一些實施例之NMOS元件的示意圖。圖4所示的NMOS元件200與圖1所示之NMOS元件200相同,另外增加用於源極區域212之接觸窗402和用於汲極區域214之接觸窗404。
在一些實施例中,接觸窗402和404包含可伸展性鎢膜。圖 4所示之向量顯示在NMOS元件200之接觸窗402和404中之可伸展性鎢膜的作用。可伸展性鎢膜可具備不同的應力。在可伸展性鎢膜中的一些應力可在與基板202之平面平行的平面中(平行應力),且在可伸展性鎢膜中的一些應力可在與基板202之平面垂直的平面中(垂直應力)。可伸展性鎢膜的平行應力係由向量412所表示。可伸展性鎢膜的垂直應力係由向量414所表示。位於接觸窗402和404的可伸展性鎢膜的中心之小接縫403可有助於抵消垂直應力414。
基板202之源極212和汲極214區域係由位於接觸窗402和404中之可伸展性鎢膜的平行應力所施加應變。鎢之平行應力412施加應力416於源極212和汲極214區域中。在源極212和汲極214區域中的應力416增加在通道區域210中之矽的晶格常數,此增加在通道區域中的電子活動性。
NMOS元件的一些實施例包含閘極區域中之可壓縮性鎢膜。NMOS元件的一些實施例包含可伸展性鎢膜,用於至源極區域和汲極區域之接觸窗。NMOS元件的一些實施例包含閘極區域中之可壓縮性鎢膜,以及可伸展性鎢膜,用於至源極區域和汲極區域的接觸窗。
圖5為根據一些實施例之半導體元件的示意圖。圖5所示之半導體元件500包含PMOS元件100和NMOS元件200。PMOS元件100和NMOS元件200係使用淺溝槽隔離特徵部502彼此互相隔離。PMOS元件100的實施例可包含閘極區域中的可伸展性鎢膜及/或可壓縮性鎢膜,用於至源極和汲極區域的接觸窗。NMOS元件200的實施例可包含閘極區域中之可壓縮性鎢及/或用於至源極和汲極區域的接觸窗之可伸展性鎢。
雖然上述元件包含平面電晶體,但可伸展性和可壓縮性鎢膜之使用並不限於此等元件,且亦可使用於其它元件中。例如,可伸展性和可壓縮性鎢膜可用於三維結構中,包含但不限於三閘極鰭式效應電晶體(tri-gate finFETs)和閘極全環繞場效應電晶體。
用於形成可伸展性和可壓縮性鎢膜的方法係描述如下。
方法
圖6描繪一處理流程圖,顯示根據一些實施例的半導體元件 之製造方法600中的操作。例如,半導體元件可包含PMOS元件及/或NMOS元件,如上所述。方法600之實施例可用於「先閘極」和「後閘極」整合模式。
在操作602中,提供具有閘極、源極、和汲極之半導體基板。該閘極、源極、和汲極可為如上所述之PMOS或NMOS元件用之閘極、源極、和汲極。此外,半導體基板可包含數個PMOS及/或NMOS元件用之一個以上的閘極、源極、和汲極。
在操作604中,界定閘極區域和源極和汲極接觸窗。源極和汲極接觸窗接觸該半導體基板之源極和汲極。可使用微影技術及/或犧牲膜以界定閘極區域和源極和汲極接觸窗,如具備本領域之一般技術者所知。
在操作606中,閘極區域和源極和汲極接觸窗係打開。例如,閘極區域和源極和汲極接觸窗可使用蝕刻技術,包含濕式和乾式化學蝕刻打開。
在操作608中,可壓縮性鎢膜係沉積於選定之閘極區域及/或源極和汲極接觸窗,如本文所述。可使用例如微影技術及/或犧牲膜以界定沉積可壓縮性鎢膜的區域。
在操作610中,可伸展性鎢膜係沉積於選定之閘極區域及/或源極和汲極接觸窗,如本文所述。可使用例如微影技術及/或犧牲膜以界定沉積可伸展性鎢膜的區域。
具備本領域之技術者將理解,根據本實施方式可改變特定操作的順序,且可省略一或更多操作,或可執行額外的操作。例如,在一些實施例中,中性應力鎢或另一金屬可沉積以用於可伸展性或可壓縮性鎢的增添或替代。
在一些實施例中,可使用原子層沉積(ALD)類型之處理形成鎢層。ALD是一種使用一或更多化學反應物,亦稱為「前驅體」所實施的薄膜沉積技術。ALD係基於連續的自限性表面反應。前驅體以氣體狀態依序進入反應腔室,於反應腔室中接觸工件(即,被塗佈的表面或複數表面)。例如,當第一前驅體進入反應腔室時,被吸附至表面上。然後,當第二前驅體進入到反應腔室時,第一前驅體與第二前驅體於表面產生反。 應。藉由反覆地將表面暴露於前驅體之交替連續脈衝,材料之薄膜係受沉積。ALD處理亦包含使表面暴露於單一前驅體之連續脈衝的處理,單一前驅體將材料之薄膜沉積於該表面上。ALD通常形成保形層,即,忠實地遵循底下表面之輪廓的層。
圖7描繪一處理流程圖,顯示根據一些實施例的鎢層之沉積方法700中的操作。在操作702中,基板係提供至腔室,例如處理腔室或真空腔室。在一些實施例中,該基板可具有一場區和從場區凹陷的特徵部。在一些實施例中,該特徵部可為高深寬比特徵部。根據各種實施例,基板之特徵部具有之深寬比至少為5:1、至少為10:1、至少為15:1、至少20:1、至少25:1、或至少30:1。根據各種實施例,特徵部尺寸之特點為深寬比之增添或替代的特徵部開口尺寸。例如,特徵部開口尺寸可為約10nm~100nm寬或約10nm到50nm寬。在一些實施例中,該方法可用於具有狹窄的開口的特徵部,不論其深寬比為何。在一些實施例中,特徵部包含傾斜之側壁,俾使特徵部開口尺寸係小於位於該特徵部之底部的特徵部之寬度。在一些實施例中,特徵部包含空腔及/或特徵部內之進一步的特徵部。
在一些實施例中,特徵部係形成於基板上之介電層內,特徵部之底部提供至底下金屬層的接觸。例如,特徵部可為用於PMOS或NMOS元件之源極或汲極區域的接觸窗。在一些實施例中,特徵部係形成於基板上的金屬層內。例如,特徵部可為PMOS或NMOS元件之閘極區域中的金屬,用以調整閘極和通道區域之間的功函數差異。在一些實施例中,特徵部包含在其側壁及/或底部上之襯墊/障蔽層。襯墊層的範例包含Ti/TiN、TiN、WN、TiC、和WC。作為擴散障壁層之增添或替代,特徵部可包含數層,例如粘著層、成核層、其組合物、或任何其他做為特徵部側壁及底部襯裡的合適材料。
在操作704中,基板係暴露至有機金屬鎢前驅體。在一些實施例中,有機金屬鎢前驅體為不含鹵素或非鹵素有機金屬鎢前驅體。鹵系化學品可能攻擊底下之表面,例如,如矽或矽化物,且使用不含鹵素或非鹵素有機金屬鎢前驅體可防止鎢前驅體與底層表面產生化學反應。一些不含鹵素的有機金屬鎢前驅體可包含氧和氮。在一些實施例中,有機金屬鎢 前驅體可包含環戊二烯基,叔丁基、羰基、或二甲基。在一些實施例中,有機金屬鎢前驅體可為脂族或芳基,包含烷基、烯基、炔基、苯基之任何一者。有機金屬鎢前驅體亦可具有碳及/或氮,例如,以亞硝基和氨基的形式。此等化合物的一些範例包含但不限於六羰基鎢、乙基環戊二烯基二羰基亞硝醯鎢、二氫乙基環戊二烯基三羰基鎢、二(環戊二烯基)二氫化鎢、二(叔丁基亞氨基)二(叔丁基氨基)鎢、環戊二烯鎢(II)三羰基氫化物、二(叔丁基亞氨基)二(二甲基氨基)鎢、和(甲基環戊二烯基)二羰基亞硝醯鎢。無鹵素和非鹵素有機金屬鎢前驅體係進一步描述於美國專利第8,053,365號,其係併入於此作為參考。在一些其它實施例中,在操作704中,基板可暴露於非有機金屬鎢前驅體的含鎢前驅體。此含鎢前驅體包含,例如WF6、及六氯化鎢(WCL6)。
在操作706中,未吸附到基板上的有機金屬鎢前驅體係從腔室中移除。例如,腔室可使用諸如氬氣、氫氣、氮氣或氦氣之載氣吹洗。在某些實施例中,氬氣係用以作為載氣。氣體吹洗可清除在基板表面附近的區域之殘留氣體反應物。
在操作708中,有機金屬鎢前驅體係遭受第一處理,包含熱處理或電漿處理,以在基板上形成鎢層。在一些實施例中,有機金屬鎢前驅體可使用包含氬、氫、氮、及/或氨的電漿加以處理。在一些實施例中,操作708可包含,例如,使用含氬/氫之電漿處理基板。在一些實施例中,用以產生電漿的射頻(RF)功率約為0.1watts到2000watts、約0.1watts到1200watts、或約200watts至700watts。在一些實施例中,在電漿處理期間之基板溫度可為約100℃至550℃、約100℃至350℃、或約150℃至300℃。含氫之電漿可與有機金屬鎢前驅體反應或分解有機金屬鎢前驅體,以形成鎢層。含氫電漿亦可能產生低電阻鎢層。氨或含氮的電漿可將氮加入正在形成的鎢層中。
在一些實施例中,熱處理可包含將基板暴露至約100℃至550℃、約100℃至350℃、或約150℃至300℃之溫度。在一些實施例中,熱處理可在包含氬、氫、氮、和氨之一或更多者的大氣環境中進行。
在操作710中,殘餘的氣體係從腔室中移除。例如,可在腔 室上抽真空,使腔室中的壓力降低,並移除殘餘的氣體。可替代地,可使用諸如氬氣、氫氣、氮氣、或氦氣之載氣吹洗腔室。在一些實施例中,氬氣係用以作為載氣。
在操作712中,基板上的鎢層係遭受第二處理,包含熱處理或電漿處理。在一些實施例中,操作712可類似於操作708。例如,在一些實施例中,操作708和712兩者可包含以含有氬、氫、氮、及/或氨的電漿處理基板。在一些實施例中,電漿功率及/或基板溫度在操作708和712中可為相同,而在一些其它的實施例中,電漿功率及/或基板溫度在操作708和712中可能會不同。
在一些實施例中,操作712中的熱處理可包含將基板暴露至約100℃至550℃、約100℃至350℃、或約150℃至300℃的溫度下。在一些實施例中,熱處理可在包含氬、氫、氮、和氨之一或更多者的大氣環境中進行。
在一些其它實施例中,操作712可不同於操作708。例如,在一些實施例中,操作708可包含在第一溫度下使用電漿處理基板,該電漿係以第一功率產生,並包含氫。操作712可包含在第二溫度下使用電漿處理基板,該電漿係以第二功率產生,並包含氨。作為另一個範例,在一些實施例中,操作708可包含在第一溫度下使用電漿處理基板,該電漿係以第一功率產生,並包含氨。操作712可包含在第二溫度下使用電漿處理基板,該電漿係以第二功率產生,並包含氫。亦可使用電漿氣體的其他組合。作為另一個範例,在一些實施例中,第一處理可為熱處理且第二處理可為電漿處理。在一些其它實施例中,第一處理可為電漿處理和第二處理可為熱處理。
在操作714中,殘餘的氣體係從腔室中移除。例如,可在腔室上抽真空,使腔室中的壓力降低,並移除殘餘的氣體。可替代地,可使用諸如氬氣、氫氣、氮氣、或氦氣之載氣吹洗腔室。在一些實施例中,氬氣係用以作為載氣。
在一些實施例中,在方法700中形成的鎢層可包含鎢金屬、氮、氮化鎢、碳、及/或碳化鎢。例如,當在操作708及/或712中,鎢 前驅體或鎢層係用氨或含氮電漿處理時,鎢層可包含可形成氮化鎢的氮。當有機金屬鎢前驅體包含氮及/或碳時,鎢層亦可包含氮、氮化鎢、碳、及/或碳化鎢。
在一些實施例中,鎢層可遭受進一步處理。例如,在操作712後,在操作714中,可藉由在腔室上抽真空,將殘餘的氣體從腔室移除,或可使用諸如氬氣、氫氣、氮氣、或氦氣之載氣吹洗殘餘之氣體。接著,基板上的鎢層可遭受第三處理,包含熱處理或電漿處理。在一些實施例中,第三處理可能類似於第一及/或第二處理,且在一些其它的實施例中,第三處理可不同於第一及/或第二處理。亦可進行第四、第五、第六等處理。
在一些實施例中,可不執行操作712和714。即,在操作708中形成鎢層後,鎢層可不遭受處理。
在一些實施例中,方法700可形成厚度為約0.1埃至1埃的鎢層。在本領域具有通常技術者將體認,具有為約0.1埃之厚度的鎢層表示平均膜厚度為約0.1埃,且鎢膜在基板的表面上可能不具有均勻的厚度。
在某些實施例中,可重複操作704、706、708、710、712、714、或操作704、706、708、和710,以形成具有期望厚度之鎢層。例如,可重複此等操作數次,以形成具有約1埃至約400埃之厚度的鎢層。
在一些實施例中,在操作704中將基板暴露至有機金屬鎢前驅體之前,基板可遭受處理以移除可能存在於基板表面上之暴露金屬上的氧化物。例如,處理可包含電漿處理,諸如電漿濺射處理或暴露至包含如氫或氨之反應性物種的電漿中。此處理可改善鎢層至基板的黏合。
在一些實施例中,在操作704之離子誘導的原子層沉積(iALD)類型的處理中,當使基板暴露至有機金屬前驅體時,電漿可能存在。可使用約0.1watts到100watts的射頻功率產生電漿。iALD類型的處理可提高鎢層的黏合性,或可提高鎢層的沉積率。再者,相較於使用其它方法所產生的層之密度,iALD處理所產生的材料層通常具有更高的密度。iALD處理也有進一步的優點,包含提供高度保形之層和精確地控制這些層的厚度。iALD處理係進一步描述於美國專利第6,428,859、6,416,822、7,871,678、和8,053,372號中,其係併入於此作為參考。iALD處理亦描述 於2011年9月23日提出申請之美國專利申請案第13/244,009號中,其係併入於此作為參考。
在一些實施例中,取決於在方法700中之有機金屬鎢前驅體與處理條件,可形成可壓縮性鎢層或可伸展性鎢層。例如,在一些實施例中,鎢層中的壓縮應力可為至少約0.5吉帕(GPa),或約0.5吉帕至3吉帕。在一些其他實施例中,鎢層中的拉伸應力可為至少約0.5吉帕,或約0.5吉帕至4.5吉帕。
表1顯示使用不含鹵素的有機金屬鎢前驅體沉積鎢層的處理條件。六個不同的處理(即,處理A至F)係用於沉積不同厚度的鎢層,其範圍介於從約45埃至340埃厚。亦顯示每個沉積之鎢層中的應力,負應力表示可壓縮性層且正應力表示可伸展性層。
在處理A-E中,鎢層係形成且未接受後續處理;換言之,鎢層之沉積係藉由相對於圖7進行上述之操作704至710的數個循環而執行,以達到期望之鎢厚度,且不執行操作712和714。在處理F中,鎢層係形成且隨後遭受處理,換言之,鎢層之沉積係藉由相對於圖7進行上述之操作704至714的數個循環而執行,以達到期望之鎢厚度。操作708係使用含有氬和氫之電漿進行,且操作712係使用含有氬和氨之電漿進行。
如表中所顯示,在一個既定溫度(例如,約300℃),較高的電漿功率(例如,約600watts之射頻功率或高於約500watts之射頻功率)產生可壓縮性鎢層且較低的電漿功率(例如,約200、300、或450watts之射頻功率,或低於約500watts之射頻功率)產生可伸展性鎢層。處理C-F係在約300℃下,以不同的電漿功率進行。在一既定的電漿功率(例如,約450watts之射頻功率)下,較低的處理溫度(例如,約150℃或約225℃以下)產生可壓縮性鎢層且較高的處理溫度(例如,約300℃或約225℃以上)產生可伸展性鎢層。處理A、B、E係在約450watts之電漿功率,以不同的溫度進行。
在一些實施例中,可壓縮性鎢層可由方法700形成,且接著可伸展性鎢層可由方法700,以不同的處理條件及/或鎢前驅體形成於該可壓縮性鎢層上。在一些其它實施例中,可伸展性鎢層可由方法700形成,且接著可壓縮性鎢層可由方法700,以不同的處理條件及/或鎢前驅體形成於該可伸展性鎢層上。額外的可壓縮性及/或可伸展性鎢層可進一步沉積於鎢層上。此等實施例可形成具有期望之最終壓縮或拉伸應力的鎢層,或無應力之鎢層。
在一些實施例中,操作704、706、708、710、712、和714皆可在相同的處理腔室中執行。在一些實施例中,操作704、706、708、710、712、和714皆可在相同的處理腔室中以及在/使用相同的基板支架或基座上執行。在一些其它實施例中,操作704、706、708、710、712、和714之一部份可在相同的處理腔室中以及在/使用不同的基板支架或基座上執行。在一些實施例中,操作704、706、708、710、712、和714之一部份可在不同的處理腔室中進行。例如,操作704至708可在第一處理腔室中執行,基板可接著被傳送到第二處理腔室,且接著操作710至714可在第二處理腔室中執行。
圖8描繪一處理流程圖,顯示根據一些實施例的鎢之沉積方法800中的操作。在操作702中,基板係提供至腔室中,如上所述,相對於圖7。
在操作802中,具有期望之厚度的鎢層係沉積於基板上。可使用包含操作704至操作714或操作704至操作710的方法沉積鎢層,如上所述相對於圖7。鎢層可作為成核層以進一步沉積鎢。例如,可沉積鎢層以形成足夠厚的成核層,以支援高品質的鎢沉積。根據一些實施例,可形成約30埃至50埃厚的鎢層作為成核層,且在一些其它實施例中,可形成約10埃至15埃厚的鎢層作為成核層。
形成鎢層後,在操作804中,使用化學氣相沉積(CVD)處理沉積鎢。例如,還原劑和含鎢前驅體可流入至腔室中以沉積主體鎢層。可使用惰性載體氣體以輸送反應物流之一或更多者,此等反應物流可為或可不為預先混合。不同於ALD類型之處理,此操作通常涉及使反應物連續地流動直到已沉積了期望之材料量。在一些實施例中,CVD處理可發生在數個階段中,且反應物之連續和同時流動的數個期間係由一或更多轉向之反應物流的期間所分開。
各種含鎢氣體,包含但不限於WF6,WCl6,及六羰基鎢(W(CO)6)可用以作為含鎢之CVD前驅體。在一些實施例中,含鎢之CVD前驅體為含鹵素之化合物,如WF6。在一些實施例中,還原劑為氫氣,但亦可使用其他的還原劑,包含矽烷(SiH4)、乙矽烷(Si2H6)、肼(N2H4)、 乙硼烷(B2H6)、及鍺烷(GeH4)。
如上所述,四個MOSFET元件的實施例,即包含在閘極區域中之可伸展性鎢膜的PMOS元件、包含用於至源極和汲極區域之接觸窗的可伸展性鎢膜的NMOS元件、包含用於至源極和汲極區域之接觸窗的可壓縮性鎢膜的PMOS元件、以及包含在閘極區域中之可壓縮性鎢膜的NMOS元件,可獨立於彼此地實施。在包含PMOS元件和NMOS元件之半導體元件的加工過程的一些實施例中,在單一組之處理操作中,可沉積用於PMOS元件之閘極和NMOS元件之接觸窗的可伸展性鎢膜。單一組之處理操作可能會使例如可伸展性鎢膜之沉積更符合成本效益。在包含PMOS元件和NMOS元件之半導體元件的製造過程之一些實施例中,在單一組之處理操作中,可沉積用於PMOS元件之閘極和NMOS元件之接觸窗的可壓縮性鎢膜。相似地,單一組之處理操作可能會使例如可壓縮性鎢膜之沉積更符合成本效益。
在一些實施例中,為了在單一的半導體元件中沉積可伸展性鎢膜和可壓縮性鎢膜兩者,遮罩及/或犧牲膜係用以控制其上沉積鎢之區域。相似地,在一些可伸展性鎢膜和可壓縮性鎢膜兩者皆沉積於被加工於單一半導體晶圓上之PMOS結構和NMOS結構裡的實施例中,遮罩及/或犧牲膜係用以控制其上沉積鎢之區域。採用遮罩及/或犧牲膜的微影技術係為在本領域中具有通常技術者所熟知。
此外,可將可伸展性鎢膜和可壓縮性鎢膜整合在金屬閘極沉積模組、接觸窗金屬化沉積模組、或在「後閘極」整合模式中。處理設備係進一步描述於下。因為此等模組之每一者的整合可能獨立於其它模組,因此可伸展性鎢膜和可壓縮性鎢膜可在任何類型的鎢沉積模組中進行沉積。
進一步地,具有不同應力位準之可壓縮性鎢膜可沉積於NMOS元件的閘極或PMOS元件的接觸窗中。相似地,具有不同應力位準之可伸展性鎢膜可沉積於PMOS元件的閘極或NMOS元件的接觸窗中。鎢膜之應力位準可隨著沉積參數變化,以提高元件性能。
設備
本文所揭露之方法可在來自不同供應商之各種類型的沉積設備中進行。適當設備之範例包含Novellus Concept-1 AltusTM,Concept 2 AltusTM、Concept-2 ALTUS-STM、Concept 3 AltusTM、Altus MaxTM、或各種其他市售工具任何一者。在一些情況下,此等方法可依序地在數個沉積站上執行。可參照例如併入於此作為參考之美國專利第6,143,082號。在一些實施例中,鎢係沉積於第一站,該站為位於單一沉積腔室中之二個、五個、甚至更多沉積站之其中一者。因此,含鎢前驅體和其它處理氣體可引入至位於第一站之半導體基板的表面,此係使用在基板表面建立局部大氣環境之單獨的氣體供應系統。第一站可接著用以進行處理。一或更多站可接著用於進一步的處理,或藉由CVD處理沉積鎢。二或更多站可用以在並行的處理操作中執行CVD。可替代地,晶圓可被編入索引,以在二或更多站上依序執行CVD操作。
圖9為適合用於根據各種實施例進行鎢沉積處理的處理系統之示意圖。系統1800包含傳輸模組1803。傳輸模組1803提供乾淨、加壓的環境,以使當受處理之基板在各種反應器模組之間移動時,遭受污染的風險降至最低。安裝在傳輸模組1803上的係為多站反應器1809,此多站反應器能根據各種實施例執行至含鎢前驅體之暴露、不同的處理、以及CVD處理。腔室1809可包含數個站,包含站1811、1813、1815、及1817,此等站可依序執行這些操作。例如,腔室1809可配置俾使站1811執行至含鎢前驅體之暴露以及第一處理,站1813執行第二處理,且站1815和1817執行CVD。每個沉積站包含一加熱之晶圓基座和噴淋頭、分散板或其他進氣口。沉積站1900的一個範例係描繪於圖10中,包含晶圓支架1902和噴淋頭1903。加熱器亦可設置於基座部1901。
亦安裝於傳輸模組1803上者可為一或更多單一或多站模組1807,此模組可進行電漿或化學(非電漿)預清洗。該模組亦可用於各種其他處理,例如,襯墊後氮化鎢處理。系統1800亦包含一或更多(在此情況下為兩個)晶圓來源模組1801,其儲存處理前和處理後的晶圓。在大氣傳輸腔室1819中之大氣機器人臂(未顯示)首先將晶圓從來源模組1801移除並移至負載鎖室1821。傳輸模組1803中之晶圓輸送元件(通常為機器 人臂單元)將晶圓從負載鎖室1821移動至安裝在傳輸模組1803上之複數模組及該等模組之間。
在一些實施例中,系統控制器1829係用以控制沉積期間之處理條件。該控制器通常包含一或更多記憶體元件及一或更多處理器。該處理器可包含中央處理單元或電腦、類比及/或數位輸入/輸出連接,步進馬達控制板等。
控制器可控制沉積設備所有的活動。系統控制器執行系統控制軟體,該系統控制軟體包含數組指令,用以控制特定處理之定時、氣體混合物、腔室壓力、腔室溫度、晶圓溫度、射頻功率位準、晶圓夾盤或基座之位置、以及其它參數。在一些實施例中,可採用其它儲存在與該控制器相連之記憶體元件上的電腦程式。
通常情況下,使用者介面係與控制器相連。使用者介面可包含顯示螢幕、設備及/或處理條件之圖形軟體顯示,以及使用者輸入裝置,如指向裝置、鍵盤、觸控螢幕、麥克風等等。
用以在處理程式中控制沉積和其他處理的電腦程式碼,可以任何習知的電腦可讀取程式化語言加以撰寫;例如,程式語言包含組合語言、C、C++、Pascal、Fortran、及其他。編譯後的目標碼或腳本係藉由處理器執行,以執行程式中識別之任務。
控制器參數與處理條件相關,例如,處理氣體之組成和流率、溫度、壓力、例如射頻功率位準之電漿條件、冷卻氣體壓力、以及腔室壁之溫度。這些參數係以配方的形式提供給使用者,並可利用使用者界面輸入。
用以監視處理之信號可由系統控制器之類比及/或數位輸入連接件所提供。用以控制處理之信號係輸出至沉積設備之類比及數位輸出連接件上。
系統軟體可以許多不同的方式設計或配置。例如,各種腔室組件的副程式或控制對象可被寫入,以控制進行本發明之沉積處理所需的腔室組件之操作。用於此目的之程式或程式的部份之範例包含基板定位碼、處理氣體控制碼、壓力控制碼、加熱器控制碼、以及電漿控制碼。
基板定位程式可包含用於控制腔室組件之程式碼,用以裝載基板至基座或夾盤上,以及控制基板和腔室之其它部位,如進氣口及/或目標之間距。處理氣體控制程式可包含用於控制氣體組成和流率之碼,以及可選擇地,用於在沉積之前將氣體流動至腔室以穩定腔室內之壓力。壓力控制程式可包含碼,用於藉由調節,例如,腔室之排氣系統中的節流閥,以控制腔室內之壓力。加熱器控制程式可包含用於控制流至用以加熱基板之加熱單元的電流之碼。可替代地,加熱器控制程式可控制諸如氦氣之加熱傳輸氣體至晶圓夾盤的輸送。
在沉積期間可受監控之腔室感應器的範例包含:質量流量控制器、壓力感應器,如位於基座或夾盤中之壓力計及熱電偶。適當地程式化之反饋和控制算法可與來自這些感應器的數據一起使用,以維持期望之處理條件。前面描述了本文所揭露之在單一或多腔室半導體處理工具中之實施例的實施方式。
本文所描述之設備/處理可結合微影圖案化工具或處理使用以用於,例如,半導體元件、顯示器、LEDs、光電板及其相似物之加工或製造等。雖非必然,但通常此等工具/處理將在一共同的處理設施中一起使用或實施。膜之微影圖案化通常包含以下步驟之部份或全部,每個步驟需使用一些可能的工具方可達成:(1)使用旋塗或噴塗工具以施加光阻於工件,即基板上;(2)使用熱板或爐或紫外線固化工具以固化光阻;(3)使用如晶圓步進器之工具以使光阻暴露於可見光或紫外線或X射線;(4)使光阻顯影,以選擇性地移除光阻,從而使用如濕檯之工具使之圖案化;(5)使用乾式或電漿輔助蝕刻工具以轉移光阻圖案到下層之膜或工件中;(6)使用如射頻或微波電漿光阻剝除器之工具以移除光阻。
其它實施例
仍有落於本揭露之實施例的範圍內之替換、變更、修改及置換均等物。例如,已描述用於沉積可伸展性或可壓縮性鎢膜之實施例。上述方法可用於沉積可伸展性或可壓縮性鎢膜於無圖案之表面上以及在基板之特徵部中。上述方法亦適用以形成其他金屬膜。
此等方法之實施例亦可用於製造具有背面應力層之半導體 結構,如在美國專利第7,670,931號中所進一步說明,其係併入於此作為參考。
應注意仍有許多實施本揭露實施例之方法和設備的替代性方式。因此欲使以下隨附請求項解釋為包含所有落於本揭露實施例之真正精神及範圍的此替換、變更、修改及置換均等物。
100‧‧‧PMOS元件
102‧‧‧基板
104‧‧‧導電閘極
106‧‧‧金屬
108‧‧‧閘極介電質
110‧‧‧通道區域
112‧‧‧源極
114‧‧‧汲極
116‧‧‧介電間隙壁
118‧‧‧介電膜
132‧‧‧平行應力
134‧‧‧垂直應力
136‧‧‧應變
138‧‧‧應力
140‧‧‧應力
142‧‧‧小接縫

Claims (22)

  1. 一種用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,包含:(a)提供基板於腔室,該基板具有一場區和從該場區凹陷之特徵部。(b)暴露該基板至有機金屬鎢前驅體;(c)從該腔室移除未吸附到該基板上之該有機金屬鎢前驅體;(d)使該基板遭受第一處理,包含熱處理或電漿處理,以形成鎢層於該基板上;(e)在操作(d)後,將殘餘的氣體從該腔室中移除;以及(f)使該基板上之該鎢層遭受第二處理,包含熱處理或電漿處理。
  2. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,其中該第一處理包含該電漿處理,第一電漿包含氬、氫、氮和氨之一或更多者。
  3. 如申請專利範圍第2項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,其中該第二處理包含該電漿處理,第二電漿包含氬、氫、氮和氨之一或更多者,其中在該第一電漿中之物種不同於在該第二電漿中之物種。
  4. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,其中該第一電漿處理和該第二電漿處理包含相同的處理。
  5. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,其中該基板之溫度在操作(d)及(f)中之該等電漿處理期間為約100℃至550℃。
  6. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,其中操作(b)係在以約0.1watts到100watts的射頻功率所產生之電漿存在的狀態下進行。
  7. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,其中在操作(d)及(f)中之該等電漿處理係使用在約0.1watts到2000watts之射頻功率所產生之電漿進行。
  8. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,其中在操作(d)及(f)中之該等電漿處理係使用在約200watts到700watts之射頻功率所產生之電漿進行。
  9. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,其中在操作(d)及(f)中之該等熱處理係在約100℃至550℃的溫度下進行。
  10. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,其中在操作(d)和(f)中之該等加熱處理,係在包含氬、氫、氮和氨之一或更多者之腔室大氣環境中進行。
  11. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,更包含:(g),在操作(f)後,將殘餘的氣體從該腔室中移除;以及重複操作(f)。
  12. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,更包含:(g),在操作(f)後,將殘餘的氣體從該腔室中移除;以及重複(b)至(f)的操作。
  13. 如申請專利範圍第1-12項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法之任一者,其中第一次執行操作(b)至(f)時,形成具有拉伸應力或壓縮應力之任一者的鎢層,且其中第二次執行操作(b)至(f)時,形成具有該拉伸應力或該壓縮應力之另一者的含鎢層。
  14. 如申請專利範圍第1-12項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法之任一者,其中該鎢層包含碳及/或氮。
  15. 如申請專利範圍第1-12項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法之任一者,其中該有機金屬鎢前驅體包含至少一官能基,且其中該官能基係選自於由環戊二烯基、叔丁基、羰基,以及二甲基所組成之群組。
  16. 如申請專利範圍第1-12項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法之任一者,其中該鎢層中之壓縮應力係為至少約0.5吉帕。
  17. 如申請專利範圍第1-12項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法之任一者,其中該鎢層中之拉伸應力係為至少約0.5吉帕。
  18. 如申請專利範圍第1-12項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法之任一者,更包含:在操作(b)前,將該基板暴露至電漿處理,以移除在該基板上之金屬表面上的氧化物。
  19. 如申請專利範圍第1項之用以形成可伸展性鎢膜與可壓縮性鎢膜的方法,更包含:施加光阻至該基板上;使該光阻暴露至光線;圖案化該光阻並將該圖案轉移至該基板;以及選擇性地將該光阻從該基板上移除。
  20. 一種沉積設備,包含:腔室;以及控制器,包含程式指令以進行處理,該處理包含:(a)提供基板至該腔室,該基板具有場區和從該場區凹陷的特徵部; (b)使該基板暴露於有機金屬鎢前驅體;(c)將未吸附到該基板上的該有機金屬鎢前驅體從該腔室中移除;(d)使該基板遭受第一處理,包含熱處理或電漿處理,以形成鎢層於該基板上;(e)在操作(d)後,將殘餘的氣體從該腔室中移除;以及(f)使該基板上之該鎢層遭受第二處理,包含熱處理或電漿處理。
  21. 一種系統,包含如申請專利範圍第20項之沉積設備和步進器。
  22. 一種非暫時性電腦機器可讀取媒體,包含用於腔室之控制的數個程式指令,該等指令包含碼,用於:(a)提供基板於腔室,該基板具有一場區和從該場區凹陷之特徵部;(b)暴露該基板至有機金屬鎢前驅體;(c)從該腔室移除未吸附到該基板上之該有機金屬鎢前驅體;(d)使該基板遭受第一處理,包含熱處理或電漿處理,以形成鎢層於該基板上;(e)在操作(d)後,將殘餘的氣體從該腔室中移除;以及(f)使該基板上之該鎢層遭受第二處理,包含熱處理或電漿處理。
TW102123248A 2012-06-29 2013-06-28 形成可伸展性鎢膜與可壓縮性鎢膜的方法 TWI605146B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201261666466P 2012-06-29 2012-06-29

Publications (2)

Publication Number Publication Date
TW201413033A true TW201413033A (zh) 2014-04-01
TWI605146B TWI605146B (zh) 2017-11-11

Family

ID=49878832

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102123248A TWI605146B (zh) 2012-06-29 2013-06-28 形成可伸展性鎢膜與可壓縮性鎢膜的方法

Country Status (3)

Country Link
US (1) US9034760B2 (zh)
KR (2) KR20140005777A (zh)
TW (1) TWI605146B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109728091A (zh) * 2017-10-30 2019-05-07 台湾积体电路制造股份有限公司 半导体元件

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US8623733B2 (en) 2009-04-16 2014-01-07 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
CN110004429B (zh) 2012-03-27 2021-08-31 诺发系统公司 钨特征填充
US9969622B2 (en) 2012-07-26 2018-05-15 Lam Research Corporation Ternary tungsten boride nitride films and methods for forming same
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US9911848B2 (en) * 2014-08-29 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical transistor and method of manufacturing the same
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
TWI720106B (zh) 2016-01-16 2021-03-01 美商應用材料股份有限公司 Pecvd含鎢硬遮罩膜及製造方法
US9929271B2 (en) 2016-08-03 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR20180038823A (ko) 2016-10-07 2018-04-17 삼성전자주식회사 유기 금속 전구체, 이를 이용한 막 형성 방법 및 이를 이용한 반도체 장치의 제조 방법
US10276677B2 (en) * 2016-11-28 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
JP7229929B2 (ja) 2017-02-01 2023-02-28 アプライド マテリアルズ インコーポレイテッド ハードマスク応用向けのホウ素がドープされた炭化タングステン
US10355012B2 (en) 2017-06-26 2019-07-16 Sandisk Technologies Llc Multi-tier three-dimensional memory device with stress compensation structures and method of making thereof
CN111095488A (zh) 2017-08-14 2020-05-01 朗姆研究公司 三维竖直nand字线的金属填充过程
JP2021523292A (ja) 2018-05-03 2021-09-02 ラム リサーチ コーポレーションLam Research Corporation 3d nand構造内にタングステンおよび他の金属を堆積させる方法
JP2020047706A (ja) * 2018-09-18 2020-03-26 キオクシア株式会社 半導体装置およびその製造方法
US11742212B2 (en) 2018-11-05 2023-08-29 Lam Research Corporation Directional deposition in etch chamber
US11972952B2 (en) 2018-12-14 2024-04-30 Lam Research Corporation Atomic layer deposition on 3D NAND structures
KR102211654B1 (ko) * 2019-02-13 2021-02-03 주식회사 메카로 텅스텐 전구체 화합물 및 이를 이용하여 제조된 텅스텐 함유 박막
US11205589B2 (en) * 2019-10-06 2021-12-21 Applied Materials, Inc. Methods and apparatuses for forming interconnection structures
KR20220030456A (ko) * 2020-09-01 2022-03-11 삼성전자주식회사 반도체 장치
KR20220030455A (ko) * 2020-09-01 2022-03-11 삼성전자주식회사 반도체 장치
CN113053804B (zh) * 2021-03-10 2023-02-21 中国科学院微电子研究所 一种钨复合膜层及其生长方法、单片3dic
KR20230174883A (ko) * 2022-06-22 2023-12-29 한국알박(주) Pvd 스퍼터링법을 통한 텅스텐의 비저항 및 응력 제어 방법

Family Cites Families (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI117944B (fi) 1999-10-15 2007-04-30 Asm Int Menetelmä siirtymämetallinitridiohutkalvojen kasvattamiseksi
JPS62216224A (ja) 1986-03-17 1987-09-22 Fujitsu Ltd タングステンの選択成長方法
JPS62260340A (ja) 1986-05-06 1987-11-12 Toshiba Corp 半導体装置の製造方法
US4746375A (en) 1987-05-08 1988-05-24 General Electric Company Activation of refractory metal surfaces for electroless plating
US5250329A (en) 1989-04-06 1993-10-05 Microelectronics And Computer Technology Corporation Method of depositing conductive lines on a dielectric
US5028565A (en) 1989-08-25 1991-07-02 Applied Materials, Inc. Process for CVD deposition of tungsten layer on semiconductor wafer
EP1069610A2 (en) 1990-01-08 2001-01-17 Lsi Logic Corporation Refractory metal deposition process for low contact resistivity to silicon and corresponding apparatus
KR100209856B1 (ko) 1990-08-31 1999-07-15 가나이 쓰도무 반도체장치의 제조방법
US5326723A (en) 1992-09-09 1994-07-05 Intel Corporation Method for improving stability of tungsten chemical vapor deposition
KR950012738B1 (ko) 1992-12-10 1995-10-20 현대전자산업주식회사 반도체소자의 텅스텐 콘택 플러그 제조방법
KR970009867B1 (ko) 1993-12-17 1997-06-18 현대전자산업 주식회사 반도체 소자의 텅스텐 실리사이드 형성방법
EP0704551B1 (en) 1994-09-27 2000-09-06 Applied Materials, Inc. Method of processing a substrate in a vacuum processing chamber
US6001729A (en) 1995-01-10 1999-12-14 Kawasaki Steel Corporation Method of forming wiring structure for semiconductor device
JP2737764B2 (ja) 1995-03-03 1998-04-08 日本電気株式会社 半導体装置及びその製造方法
US5863819A (en) 1995-10-25 1999-01-26 Micron Technology, Inc. Method of fabricating a DRAM access transistor with dual gate oxide technique
US6017818A (en) 1996-01-22 2000-01-25 Texas Instruments Incorporated Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
US6310300B1 (en) 1996-11-08 2001-10-30 International Business Machines Corporation Fluorine-free barrier layer between conductor and insulator for degradation prevention
US6297152B1 (en) 1996-12-12 2001-10-02 Applied Materials, Inc. CVD process for DCS-based tungsten silicide
US5804249A (en) 1997-02-07 1998-09-08 Lsi Logic Corporation Multistep tungsten CVD process with amorphization step
US6037248A (en) 1997-06-13 2000-03-14 Micron Technology, Inc. Method of fabricating integrated circuit wiring with low RC time delay
US5956609A (en) 1997-08-11 1999-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing stress and improving step-coverage of tungsten interconnects and plugs
US5795824A (en) 1997-08-28 1998-08-18 Novellus Systems, Inc. Method for nucleation of CVD tungsten films
US5926720A (en) 1997-09-08 1999-07-20 Lsi Logic Corporation Consistent alignment mark profiles on semiconductor wafers using PVD shadowing
US7829144B2 (en) 1997-11-05 2010-11-09 Tokyo Electron Limited Method of forming a metal film for electrode
US6861356B2 (en) 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
US6099904A (en) 1997-12-02 2000-08-08 Applied Materials, Inc. Low resistivity W using B2 H6 nucleation step
JPH11260759A (ja) 1998-03-12 1999-09-24 Fujitsu Ltd 半導体装置の製造方法
US6066366A (en) 1998-07-22 2000-05-23 Applied Materials, Inc. Method for depositing uniform tungsten layers by CVD
US6143082A (en) 1998-10-08 2000-11-07 Novellus Systems, Inc. Isolation of incompatible processes in a multi-station processing chamber
KR100273767B1 (ko) 1998-10-28 2001-01-15 윤종용 반도체소자의 텅스텐막 제조방법 및 그에 따라 제조되는 반도체소자
US6037263A (en) 1998-11-05 2000-03-14 Vanguard International Semiconductor Corporation Plasma enhanced CVD deposition of tungsten and tungsten compounds
US6331483B1 (en) 1998-12-18 2001-12-18 Tokyo Electron Limited Method of film-forming of tungsten
US20010014533A1 (en) 1999-01-08 2001-08-16 Shih-Wei Sun Method of fabricating salicide
US6245654B1 (en) 1999-03-31 2001-06-12 Taiwan Semiconductor Manufacturing Company, Ltd Method for preventing tungsten contact/via plug loss after a backside pressure fault
US6294468B1 (en) 1999-05-24 2001-09-25 Agere Systems Guardian Corp. Method of chemical vapor depositing tungsten films
US6720261B1 (en) 1999-06-02 2004-04-13 Agere Systems Inc. Method and system for eliminating extrusions in semiconductor vias
US6174812B1 (en) 1999-06-08 2001-01-16 United Microelectronics Corp. Copper damascene technology for ultra large scale integration circuits
US6355558B1 (en) 1999-06-10 2002-03-12 Texas Instruments Incorporated Metallization structure, and associated method, to improve crystallographic texture and cavity fill for CVD aluminum/PVD aluminum alloy films
US6265312B1 (en) 1999-08-02 2001-07-24 Stmicroelectronics, Inc. Method for depositing an integrated circuit tungsten film stack that includes a post-nucleation pump down step
US6309966B1 (en) 1999-09-03 2001-10-30 Motorola, Inc. Apparatus and method of a low pressure, two-step nucleation tungsten deposition
US6303480B1 (en) 1999-09-13 2001-10-16 Applied Materials, Inc. Silicon layer to improve plug filling by CVD
EP1221178A1 (en) 1999-10-15 2002-07-10 ASM America, Inc. Method for depositing nanolaminate thin films on sensitive surfaces
US6277744B1 (en) 2000-01-21 2001-08-21 Advanced Micro Devices, Inc. Two-level silane nucleation for blanket tungsten deposition
US6429126B1 (en) 2000-03-29 2002-08-06 Applied Materials, Inc. Reduced fluorine contamination for tungsten CVD
EP1290746B1 (en) 2000-05-18 2012-04-25 Corning Incorporated High performance solid electrolyte fuel cells
US6551929B1 (en) 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US6936538B2 (en) 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US7405158B2 (en) 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US6491978B1 (en) * 2000-07-10 2002-12-10 Applied Materials, Inc. Deposition of CVD layers for copper metallization using novel metal organic chemical vapor deposition (MOCVD) precursors
US6740591B1 (en) 2000-11-16 2004-05-25 Intel Corporation Slurry and method for chemical mechanical polishing of copper
US6908848B2 (en) 2000-12-20 2005-06-21 Samsung Electronics, Co., Ltd. Method for forming an electrical interconnection providing improved surface morphology of tungsten
US6635965B1 (en) 2001-05-22 2003-10-21 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US7262125B2 (en) 2001-05-22 2007-08-28 Novellus Systems, Inc. Method of forming low-resistivity tungsten interconnects
US7141494B2 (en) 2001-05-22 2006-11-28 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US7955972B2 (en) 2001-05-22 2011-06-07 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US7005372B2 (en) 2003-01-21 2006-02-28 Novellus Systems, Inc. Deposition of tungsten nitride
US7589017B2 (en) 2001-05-22 2009-09-15 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
US7211144B2 (en) 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
WO2003029515A2 (en) 2001-07-16 2003-04-10 Applied Materials, Inc. Formation of composite tungsten films
US20030029715A1 (en) 2001-07-25 2003-02-13 Applied Materials, Inc. An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems
JP2005504885A (ja) 2001-07-25 2005-02-17 アプライド マテリアルズ インコーポレイテッド 新規なスパッタ堆積方法を使用したバリア形成
US6607976B2 (en) 2001-09-25 2003-08-19 Applied Materials, Inc. Copper interconnect barrier layer structure and formation method
TW589684B (en) 2001-10-10 2004-06-01 Applied Materials Inc Method for depositing refractory metal layers employing sequential deposition techniques
US6566262B1 (en) 2001-11-01 2003-05-20 Lsi Logic Corporation Method for creating self-aligned alloy capping layers for copper interconnect structures
US20030091739A1 (en) 2001-11-14 2003-05-15 Hitoshi Sakamoto Barrier metal film production apparatus, barrier metal film production method, metal film production method, and metal film production apparatus
US6566250B1 (en) 2002-03-18 2003-05-20 Taiwant Semiconductor Manufacturing Co., Ltd Method for forming a self aligned capping layer
US6905543B1 (en) 2002-06-19 2005-06-14 Novellus Systems, Inc Methods of forming tungsten nucleation layer
TWI287559B (en) 2002-08-22 2007-10-01 Konica Corp Organic-inorganic hybrid film, its manufacturing method, optical film, and polarizing film
US6706625B1 (en) 2002-12-06 2004-03-16 Chartered Semiconductor Manufacturing Ltd. Copper recess formation using chemical process for fabricating barrier cap for lines and vias
US6962873B1 (en) 2002-12-10 2005-11-08 Novellus Systems, Inc. Nitridation of electrolessly deposited cobalt
US7311944B2 (en) 2002-12-23 2007-12-25 Applied Thin Films, Inc. Aluminum phosphate coatings
US6844258B1 (en) 2003-05-09 2005-01-18 Novellus Systems, Inc. Selective refractory metal and nitride capping
KR20060079144A (ko) 2003-06-18 2006-07-05 어플라이드 머티어리얼스, 인코포레이티드 배리어 물질의 원자층 증착
US7754604B2 (en) 2003-08-26 2010-07-13 Novellus Systems, Inc. Reducing silicon attack and improving resistivity of tungsten nitride film
JP4606006B2 (ja) 2003-09-11 2011-01-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR100557626B1 (ko) 2003-12-23 2006-03-10 주식회사 하이닉스반도체 반도체 소자의 비트라인 형성 방법
KR101108304B1 (ko) 2004-02-26 2012-01-25 노벨러스 시스템즈, 인코포레이티드 질화 텅스텐의 증착
US7605469B2 (en) 2004-06-30 2009-10-20 Intel Corporation Atomic layer deposited tantalum containing adhesion layer
US7429402B2 (en) 2004-12-10 2008-09-30 Applied Materials, Inc. Ruthenium as an underlayer for tungsten film deposition
US7220671B2 (en) 2005-03-31 2007-05-22 Intel Corporation Organometallic precursors for the chemical phase deposition of metal films in interconnect applications
US7517798B2 (en) 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
US7524765B2 (en) 2005-11-02 2009-04-28 Intel Corporation Direct tailoring of the composition and density of ALD films
US8258057B2 (en) 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
TW200746268A (en) 2006-04-11 2007-12-16 Applied Materials Inc Process for forming cobalt-containing materials
US8153831B2 (en) 2006-09-28 2012-04-10 Praxair Technology, Inc. Organometallic compounds, processes for the preparation thereof and methods of use thereof
US7655567B1 (en) 2007-07-24 2010-02-02 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
US7772114B2 (en) 2007-12-05 2010-08-10 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US8053365B2 (en) 2007-12-21 2011-11-08 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
US8062977B1 (en) 2008-01-31 2011-11-22 Novellus Systems, Inc. Ternary tungsten-containing resistive thin films
US8058170B2 (en) 2008-06-12 2011-11-15 Novellus Systems, Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US8551885B2 (en) 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
US8110877B2 (en) 2008-12-19 2012-02-07 Intel Corporation Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
US8623733B2 (en) 2009-04-16 2014-01-07 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US8207062B2 (en) 2009-09-09 2012-06-26 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
DE102009055392B4 (de) 2009-12-30 2014-05-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterbauelement und Verfahren zur Herstellung des Halbleiterbauelements
US8709948B2 (en) 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
US20120199887A1 (en) 2011-02-03 2012-08-09 Lana Chan Methods of controlling tungsten film properties

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109728091A (zh) * 2017-10-30 2019-05-07 台湾积体电路制造股份有限公司 半导体元件
TWI726209B (zh) * 2017-10-30 2021-05-01 台灣積體電路製造股份有限公司 半導體元件
US11062908B2 (en) 2017-10-30 2021-07-13 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structure
US11728170B2 (en) 2017-10-30 2023-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structure

Also Published As

Publication number Publication date
TWI605146B (zh) 2017-11-11
US9034760B2 (en) 2015-05-19
US20140011358A1 (en) 2014-01-09
KR20200116071A (ko) 2020-10-08
KR20140005777A (ko) 2014-01-15

Similar Documents

Publication Publication Date Title
TWI605146B (zh) 形成可伸展性鎢膜與可壓縮性鎢膜的方法
US10529722B2 (en) Tungsten for wordline applications
KR102572271B1 (ko) 몰리브덴을 함유하는 저 저항률 막들
KR102603859B1 (ko) 매우 낮은 저항률의 텅스텐을 증착하는 방법
KR102515236B1 (ko) 저 저항 텅스텐 피처 충진을 가능하게 하는 텅스텐 핵생성 프로세스
US10546751B2 (en) Forming low resistivity fluorine free tungsten film without nucleation
US20200402846A1 (en) Self-limiting growth
US9613818B2 (en) Deposition of low fluorine tungsten by sequential CVD process
US20120199887A1 (en) Methods of controlling tungsten film properties
KR102397797B1 (ko) 순차적인 cvd 프로세스에 의한 저 불소 텅스텐의 증착
KR20200125918A (ko) 작은 임계 치수의 피쳐에서 텅스텐 컨택 저항을 개선하는 방법
KR20140034081A (ko) 낮은 거칠기 및 낮은 저항을 갖는 텅스텐 막을 증착시키기 위한 방법
KR20210081436A (ko) 텅스텐을 위한 몰리브덴 템플릿들
KR20210110886A (ko) 금속 막들의 증착
KR20230104542A (ko) 텅스텐 저 저항 펄싱된 cvd
WO2013052145A1 (en) In-situ hydroxylation apparatus
TW202401671A (zh) 高縱橫比3d nand結構中的鎢字元線填充