TW201347092A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TW201347092A TW201347092A TW102116457A TW102116457A TW201347092A TW 201347092 A TW201347092 A TW 201347092A TW 102116457 A TW102116457 A TW 102116457A TW 102116457 A TW102116457 A TW 102116457A TW 201347092 A TW201347092 A TW 201347092A
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
一種半導體裝置,其包括:層間絕緣膜,形成於基底上,且包括溝渠;閘極絕緣膜,形成於溝渠中;功函數調整膜,沿著溝渠的側壁與底面而形成於溝渠中的閘極絕緣膜上,且包括相對於溝渠的側壁而具有銳角的斜面;以及金屬閘極圖案,形成於溝渠中的功函數調整膜上,以填滿溝渠。
Description
本申請案主張於2012年5月11日在韓國智慧財產局申請的韓國專利申請案第10-2012-0050344號的優先權,其全部內容以參考方式併入於此。
本發明的概念是有關於一種半導體裝置及其製造方法。
隨著金屬氧化物半導體(MOS)電晶體的尺寸縮小,閘極的長度以及形成在閘極下方的通道的長度也減少。因此,已進行各種努力來增加閘極與通道之間的電容,以改善MOS電晶體的操作特性。
一般用來做為閘極絕緣膜的氧化矽膜,隨著厚度減少而對電性具有物理限制。因此,已研究使用具有高介電常數(high-k)的高介電常數膜,來取代MOS電晶體中的氧化矽閘極絕緣膜。當
使用此高介電常數膜時,可能減少使用薄的等效氧化物膜時閘極電極與通道區之間的漏電流。
此外,一般用來做為閘極材料的多晶矽的電阻高於大部分金屬的電阻。因此,在許多MOS電晶體中,多晶矽閘極電極被金屬閘極電極取代。
本發明的概念提供具有改良的填溝(gap-fill)特性的半導體裝置。
本發明的概念亦提供具有改良的填溝特性的半導體裝置的製造方法。
本發明的概念的目的並不限於此,且本發明的概念的其他目的將描述以下實施例中或自其體現。
根據本發明的概念的目的,提供半導體裝置,其包括基底且具有位於基底上的層間絕緣膜,層間絕緣膜包括溝渠。閘極絕緣膜位於溝渠中。功函數調整膜(work function adjusting film)位於溝渠的第一側壁、第二側壁與底面上。功函數調整膜包括相對於溝渠的第一側壁形成銳角的斜面。金屬閘極圖案位於功函數調整膜上,以實質上填滿溝渠。
根據本發明的概念的另一目的,提供半導體裝置,其包括:基底;位於基底上的層間絕緣膜,層間絕緣膜中具有彼此分離的第一溝渠與第二溝渠;NMOS電晶體,包括形成於第一溝渠
中的第一金屬閘極;以及PMOS電晶體,包括形成於第二溝渠中的第二金屬閘極,其中第一金屬閘極包括沿著第一溝渠的第一側壁、第二側壁與底面形成的第一N型功函數調整膜,第二金屬閘極包括依序沿著第二溝渠的第一側壁、第二側壁與底面堆疊的P型功函數調整膜與第二N型功函數調整膜,且第二N型功函數調整膜包括相對於溝渠的第一側壁具有銳角的第一斜面。
根據本發明的概念的另一目的,提供半導體裝置,其包括:位於基底上的層間絕緣膜,層間絕緣膜中具有溝渠;位於溝渠中的閘極絕緣膜;位於溝渠中的閘極絕緣膜的上表面上的第一TiN膜;位於溝渠中的第一TiN膜的上表面上的TaN膜;位於溝渠中的TaN膜的上表面上的第二TiN膜;以及位於溝渠中的第二TiN膜的上表面上的TiAl膜,其中第二TiN膜與TiAl膜中的一者包括相對於溝渠的至少一個側壁具有銳角的斜面。
根據本發明的概念的另一目的,提供半導體裝置的製造方法,其中:於基底上形成層間絕緣膜,以包括溝渠;於溝渠中形成閘極絕緣膜;沿著溝渠的側壁與底面以及層間絕緣膜的上表面於閘極絕緣膜上形成功函數調整膜;移除部分功函數調整膜,使得功函數調整膜包括相對於溝渠的側壁具有銳角的斜面;以及於功函數調整膜上形成金屬閘極圖案,以填滿溝渠。
根據本發明的概念的另一目的,提供半導體裝置的製造方法,其中:於包括第一區域與第二區域的基底上形成層間絕緣膜。層間絕緣膜包括形成於第一區域中的第一溝渠與形成於第二
區域中的第二溝渠。於第一溝渠中形成第一閘極絕緣膜,以及於第二溝渠中形成第二閘極絕緣膜。於第二閘極絕緣膜上形成第一功函數調整膜,第一功函數調整膜沿著第二溝渠的側壁與底面以及層間絕緣膜的上表面配置。於第一閘極絕緣膜與第一功函數調整膜上形成第二功函數調整膜,第二功函數調整膜沿著第一溝渠的側壁與底面、第二溝渠的側壁與底面以及層間絕緣膜的上表面配置。移除部分第二功函數調整膜,使得第二功函數調整膜包括相對於第二溝渠的側壁具有銳角的第一斜面。形成第一金屬閘極圖案以填滿第一溝渠,以及形成第二金屬閘極圖案以填滿第二溝渠。
根據本發明的概念的另一目的,提供半導體裝置,其包括:基底;位於基底上的層間絕緣膜,層間絕緣膜具有溝渠;位於溝渠的第一側壁、第二側壁與底面上的閘極絕緣膜;以及位於閘極絕緣膜上的功函數調整膜,功函數調整膜具有第一側壁、第二側壁與底面。功函數調整膜的第一側壁與第二側壁的上部為倒角的(chamfered)。
藉由參照所附圖式詳細地描述示例性實施例,本發明的概念的上述以及其他目的與特徵將更為清楚。
1、2、3、4、5、6‧‧‧半導體裝置
100、200‧‧‧基底
110、210‧‧‧層間絕緣膜
112、212‧‧‧溝渠
119、219‧‧‧犧牲閘極圖案
130、130a、230、230a‧‧‧閘極絕緣膜
140、140a、240、240a‧‧‧蝕刻終止膜
150a、250、250a、250b‧‧‧P型功函數調整膜
170、170a、270、270a、270b‧‧‧N型功函數調整膜
180、180a、280、280a‧‧‧黏著膜
190、190a、290、290a‧‧‧金屬閘極圖案
198、298‧‧‧硬罩幕
199‧‧‧光阻膜
201‧‧‧元件隔離膜
220‧‧‧間隙壁
222‧‧‧閘極電極
225‧‧‧凹陷
256、276‧‧‧斜面
261‧‧‧源極/汲極
293‧‧‧光阻圖案
297‧‧‧硬罩幕圖案
310‧‧‧第一主動區
320‧‧‧第二主動區
330‧‧‧第三主動區
340‧‧‧第四主動區
350‧‧‧接觸窗
351‧‧‧第一閘極電極
352‧‧‧第二閘極電極
353‧‧‧第三閘極電極
354‧‧‧第四閘極電極
361、362‧‧‧共用接觸窗
371、372‧‧‧導線
1100‧‧‧電子系統
1110‧‧‧控制器
1120‧‧‧輸入/輸出裝置
1130‧‧‧記憶體裝置
1140‧‧‧介面
1150‧‧‧匯流排
BL‧‧‧位元線
/BL‧‧‧輔助位元線
INV1、INV2‧‧‧反相器
F1‧‧‧鰭
L1‧‧‧第一平均深度
L2‧‧‧第二平均深度
PD1‧‧‧第一下拉電晶體
PD2‧‧‧第二下拉電晶體
PS1‧‧‧第一通路電晶體
PS2‧‧‧第二通路電晶體
PU1‧‧‧第一上拉電晶體
PU2‧‧‧第二上拉電晶體
Vcc‧‧‧電源供應節點
Vss‧‧‧接地節點
WL‧‧‧字元線
X1‧‧‧第一方向
Y1‧‧‧第二方向
I‧‧‧第一區域
II‧‧‧第二區域
θ 1、θ 2‧‧‧銳角
圖1為根據本發明的概念的第一實施例的半導體元件的剖面圖。
圖2為圖1的區域III的放大圖。
圖3為根據本發明的概念的第二實施例的半導體裝置的剖面圖。
圖4為根據本發明的概念的第三實施例的半導體裝置的剖面圖。
圖5為根據本發明的概念的第四實施例的半導體裝置的剖面圖。
圖6為根據本發明的概念的第五實施例的半導體裝置的立體圖。
圖7為沿圖6的線A-A'的剖面圖。
圖8為沿圖6的線B-B'的剖面圖。
圖9與圖10分別為根據本發明的概念的第六實施例的半導體裝置的電路圖與佈局圖。
圖11為包括根據本發明的概念的一些實施例的半導體裝置的電子系統的方塊圖。
圖12與圖13為根據本發明的概念的一些實施例的半導體裝置可應用的示例性的半導體系統。
圖14至圖21為製造根據本發明的概念的第一實施例的半導體裝置的中間步驟的示意圖。
圖22為製造根據本發明的概念的第二實施例的半導體裝置的中間步驟的示意圖。
圖23至圖26為製造根據本發明的概念的第三實施例的
半導體裝置的中間步驟的示意圖。
本發明將參照所附圖式更完整描述於後,其展現本發明的多個實施例。然而,此發明可以不同形式體現,且不應解釋為限制於本文中的實施例。更確切地說,提供這些實施例以使得此揭露將更徹底且完整,且將完全地對本領域技術人員傳達本發明的範疇。在整個說明書中,相同的標號代表相同的元件。在所附的圖式中,為了清楚表示,膜層與區域的厚度可能為誇大的。
亦將瞭解的是,當一個膜層表示為在另一個膜層或基底上時,其可以直接地位於另一個膜層或基底上,或者可存在中間層。相反地,當一個元件表示為直接位於另一個元件上,則不存在中間元件。
與空間相關的名詞,例如"在……之下"、"下方"、"下方的"、"上方"、"上方的"等等,在此可用來簡單描述圖中一個元件或特徵對於其他元件或特徵的關係。將瞭解的是,除了圖中描述的方位之外,與空間相關的名詞傾向於包含在使用或操作中不同的裝置方位。舉例來說,若圖中的裝置倒轉,描述為在其他元件或特徵之下或下方的元件將定位為在其他元件或特徵上方。因此,示例性的名詞"下方"可包含在上方和下方的定位。除此之外,裝置可被定位(旋轉90度或其他方位),且文中所用的與空間相關的描述將相應地說明。
除非文中指明或清楚地表示在描述,否則本發明的內文中所使用的"一"與"所述"(特別是在以下申請專利範圍的內文中)表示為包含單個或多個。除非另外指明,否則"包括"、"具有"、"包含"與"含有"表示開放式的名詞(即,表示"包括但不限於")。
除非另外定義,文中所用的所有的技術與科學名詞具有如本領域技術人員所熟知的相同意義。要注意的是,除非明確說明,否則文中使用的實例或示例性名詞僅欲於較佳地解釋本發明,並不限制本發明的範圍。
本發明將以立體圖、剖面圖和/或平面圖描述,其展現本發明的多個實施例。因此,示例性角度的描述可根據技術或容忍度(allowance)來修改。也就是說,本發明的實施例不欲於限制本發明的範圍,且包含可起因於製程改變的所有的改變與修改。因此,圖示中的區域以概要的方式描繪,且區域的形狀為了說明而簡單地表示且不做為限制。
圖1為根據本發明的概念的第一實施例的半導體裝置1的剖面圖。圖2為圖1的區域III的放大圖。在圖1中,PMOS電晶體的閘極做為例子,但本發明不限於此。
參照圖1,根據本發明的概念的第一實施例的半導體裝置1可包括基底200、具有溝渠212的層間絕緣膜210、閘極絕緣膜230、蝕刻終止膜240、P型功函數調整膜250、N型功函數調整膜270、黏著膜280、金屬閘極圖案290等等。
元件隔離膜藉由淺溝渠隔離結構(STI)而形成於基底200
中,以定義主動區。舉例來說,基底200可由選自於Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC、InAs與InP所組成的族群中的至少一種半導體材料形成。此外,也可使用絕緣體上矽(silicon on insulator,SOI)基底。
層間絕緣膜210可形成於基底200上。溝渠212可提供於層間絕緣膜210中。在一些實施例中,層間絕緣膜210可藉由堆疊二層或更多層的絕緣膜來形成。如圖所示,間隙壁220可形成於溝渠212的側壁上,且基底200可配置於溝渠212的底面上,但並不限於此。間隙壁220可包括氮化物膜與氮氧化物膜中至少一者。
閘極絕緣膜230可共形地沿著溝渠212的側壁與底面而形成。閘極絕緣膜230可包括介電常數高於氧化矽膜的高介電常數材料。舉例來說,閘極絕緣膜230可包括選自由HfO2、ZrO2、Ta2O5、TiO2、SrTiO3與(Ba,Sr)TiO3所組成的族群中的材料。閘極絕緣膜230可根據待形成的裝置的類型而形成為具有適當的厚度。舉例來說,在閘極絕緣膜230為HfO2膜的情況下,閘極絕緣膜230可形成為具有約50 Å以下的厚度(約5 Å至50 Å)。
蝕刻終止膜240可形成於溝渠212中的閘極絕緣膜230上。如圖所示,蝕刻終止膜240可共形地沿著溝渠212的底面與側壁而形成。蝕刻終止膜240例如可包括TiN與TaN中的至少一者。或者,蝕刻終止膜240可為依序堆疊的TiN膜與TaN膜。當蝕刻多餘的N型功函數調整膜270(形成在不同區域中)(參照圖17
與圖18)時,可使用蝕刻終止膜240。蝕刻終止膜240可根據待形成的裝置的類型而形成為具有適當的厚度。舉例來說,若蝕刻終止膜240為TiN膜,則蝕刻終止膜240可形成為具有約5 Å至40 Å的厚度,且若蝕刻終止膜240為TaN膜,則蝕刻終止膜240可形成為具有約5 Å至30 Å的厚度。
P型功函數調整膜250可形成於溝渠212中的蝕刻終止膜240上。如圖所示,P型功函數調整膜250也可共形地沿著溝渠212的底面與側壁而形成。P型功函數調整膜250可藉由調整P型電晶體的功函數而調整P型電晶體的操作特性。舉例來說,P型功函數調整膜250可為TiN膜,但並不限於此。
N型功函數調整膜270可形成於溝渠212中的P型功函數調整膜250上。如圖所示,N型功函數調整膜270也可共形地沿著溝渠212的底面與側壁而形成。N型功函數調整膜270可藉由調整N型電晶體的功函數來調整N型電晶體的操作特性。若N型功函數調整膜270不會減弱P型電晶體的操作特性,則N型功函數調整膜270可包括於P型電晶體中而不被移除。此可減少微影製程的步驟。N型功函數調整膜270可為選自由TiAl、TiAlN、TaC、TiC與HfSi所組成的族群中的材料。舉例來說,N型功函數調整膜270可為TiAl膜。
黏著膜280可形成於溝渠212中的N型功函數調整膜270上。黏著膜280可包括TiN與Ti中的至少一者。或者,黏著膜280可為依序堆疊的TiN膜與Ti膜。黏著膜280可增加所形成的金屬
閘極圖案290的黏著力。
金屬閘極圖案290可形成於溝渠212中的黏著膜280上,以填滿溝渠212。金屬閘極圖案290可為Al、W或類似物,但不限於此。
如圖1與圖2所示,P型功函數調整膜250與N型功函數調整膜270可共形地沿著溝渠212的底面與側壁而形成。P型功函數調整膜250的第一部分沿著溝渠212的第一側壁(圖1與圖2中的右側壁)而配置,且P型功函數調整膜250的第二部分沿著溝渠212的第二側壁(圖1中的左側壁)而配置。P型功函數調整膜250的第一部分包括相對於溝渠212的第一側壁具有銳角θ 1的斜面256。P型功函數調整膜250的第二部分亦包括相對於溝渠212的第二側壁而形成銳角的斜面。
沿著溝渠212的側壁配置的N型功函數調整膜270包括具有斜面276(相對於溝渠212的第一側壁(圖1與圖2中的右側壁)具有銳角θ 2)的第一部分。N型功函數調整膜270的第二部分亦具有相對於溝渠212的第二側壁(圖1中的左側壁)而形成銳角的斜面。此處,若功函數調整膜中自溝渠的側壁至斜面所量測的角度小於90度,則功函數調整膜的斜面被認為相對於溝渠的側壁(或位於溝渠的側壁上的另一膜層)而形成銳角。由於這些銳角,P型功函數調整膜250與N型功函數調整膜270可各自具有倒角的形狀。
在圖式中,已說明的是,斜面256的銳角θ 1實質上與
斜面276的銳角θ 2相同,但本發明的概念的實施例不限於此。也就是說,在其他實施例中,斜面256的銳角θ 1可與斜面276的銳角θ 2不同。舉例來說,斜面276的銳角θ 2可大於斜面256的銳角θ 1,或者斜面276的銳角θ 2可小於斜面256的銳角θ 1。
如圖所示,P型功函數調整膜250的斜面256以及N型功函數調整膜270的斜面276可彼此直接接觸,以形成連續表面,但並不限於此。因此,在其他實施例中,斜面256的終點與斜面276的起點可不在相同位置。
如圖所示,自層間絕緣膜210的上表面至P型功函數調整膜250的頂面的第一平均深度L1,可與自層間絕緣膜210的上表面至N型功函數調整膜270的頂面的第二平均深度L2不同。舉例來說,第一平均深度L1可小於第二平均深度L2。在P型功函數調整膜250的斜頂面形成直線的實施例中,第一平均深度L1為自層間絕緣膜210的上表面至斜面256的中央的深度。類似地,在N型功函數調整膜270的斜頂面形成直線的實施例中,第二平均深度L2為自層間絕緣膜210的上表面至斜面276的中央的深度。
由於斜面256形成於P型功函數調整膜250的上側,因此P型功函數調整膜250的上部的寬度隨著離溝渠212的底面的距離增加可變得較小。由於斜面276形成於N型功函數調整膜270的上側,因此N型功函數調整膜270的上部的寬度隨著離溝渠212的底面的距離增加亦可變得較小。
由於P型功函數調整膜250與N型功函數調整膜270的形狀,金屬閘極圖案290的填溝特性可被改善。特別是,隨著半導體裝置的尺寸減小,各種元件(例如電晶體)的尺寸亦減小。因此,由於溝渠212的尺寸亦變得較小,而難以在溝渠212中形成多膜層(例如閘極絕緣膜、蝕刻終止膜、功函數調整膜、黏著膜、金屬閘極圖案等等)。
在根據本發明的概念的第一實施例的半導體元件1中,由於在P型功函數調整膜250的終點形成斜面256且在N型功函數調整膜270的終點形成斜面276,因此溝渠212中的上部開口保持為相對寬的。此可易於將金屬沈積至用於形成金屬閘極圖案290的溝渠212中。由於金屬可填滿溝渠212的深部,因此金屬的填溝特性可被改善,同時可改善半導體元件1的可靠度。
圖3為根據本發明的概念的第二實施例的半導體裝置的剖面圖。為了簡化說明,以下實施例的討論將著重於與參照圖1與圖2所描述的第一實施例的差異。
在一些實施例中,斜面256可形成小於80度的銳角θ 1。在其他實施例中,斜面256可形成小於70度的銳角θ 1。在其他實施例中,斜面256可形成小於60度的銳角θ 1。在其他實施例中,斜面256可形成小於45度的銳角θ 1。
類似地,在一些實施例中,斜面276可形成小於80度的銳角θ 2。在其他實施例中,斜面276可形成小於70度的銳角θ 2。在其他實施例中,斜面276可形成小於60度的銳角θ 2。在其他
實施例中,斜面276可形成小於45度的銳角θ 2。
要注意的是,此處所使用的"銳角"不包括僅些微程度小於90度的角度(其可能例如來自半導體成長與處理操作中的正常變化)。舉例來說,由於處理變化或限制,預期垂直的側壁可能不會完全地垂直。
參照圖3,在根據本發明的概念的第二實施例的半導體裝置2中,P型功函數調整膜250不包括相對於溝渠212的側壁形成銳角的斜面(例如斜面256),而是具有相對於溝渠212的第一側壁與第二側壁形成約90度的非傾斜表面。N型功函數調整膜270可包括相對於溝渠212的第一側壁形成銳角的斜面276。
由於N型功函數調整膜270包括斜面276,因此溝渠212的入口寬於當N型功函數調整膜270不包括斜面276時的溝渠212的入口。如上所討論,溝渠212中的上部開口變寬可較容易地藉由在溝渠212中沈積金屬而形成具有良好填溝特性的金屬閘極圖案290。
圖4為根據本發明的概念的第三實施例的半導體裝置3的剖面圖。為了簡化說明,以下實施例的討論將著重於與參照圖1與圖2所描述的第一實施例的差異。
參照圖4,根據本發明的概念的第三實施例的半導體裝置3不包括N型功函數調整膜270(見圖1)。如上所討論,若N型功函數調整膜270不減弱P型電晶體的操作特性,則N型功函數調整膜270可包括在P型電晶體中。然而,為了將P型電晶體的操
作特性最大化,N型功函數調整膜270可沈積在P型電晶體的膜層結構中且接著被移除。由於N型功函數調整膜270不存在,因此溝渠212中的開口更寬。此外,P型功函數調整膜250可包括相對於溝渠212的第一側壁而形成銳角的斜面256。如上所討論,溝渠212中較寬的開口可易於在溝渠212中形成具有良好填溝特性的金屬閘極圖案290。
圖5為根據本發明的概念的第四實施例的半導體裝置4的剖面圖。為了簡化說明,以下實施例的討論將著重於與參照圖1與圖2所描述的第一實施例的差異。
參照圖5,在根據本發明的概念的第四實施例的半導體裝置4中,於基底100與200上定義第一區域I與第二區域II。N型電晶體可形成在第一區域I中,而P型電晶體可形成在第二區域II中。
N型電晶體可包括第一置換金屬閘極(replacement metal gate)。第一置換金屬閘極可形成在包括溝渠112的層間絕緣膜110中。
閘極絕緣膜130可共形地沿著溝渠112的側壁與底面而形成。閘極絕緣膜130可包括具有介電常數高於氧化矽膜的高介電常數材料。舉例來說,閘極絕緣膜130可包括選自由HfO2、ZrO2、Ta2O5、TiO2、SrTiO3與(Ba,Sr)TiO3所組成的族群中的材料。
第一置換金屬閘極可包括蝕刻終止膜140、N型功函數調整膜170、黏著膜180與金屬閘極圖案190。如圖所示,蝕刻終止
膜140、N型功函數調整膜170與黏著膜180可共形地沿著溝渠112的底面與側壁而形成。蝕刻終止膜140可包括例如是TiN與TaN中的至少一者。或者,蝕刻終止膜140可為依序堆疊的TiN膜與TaN膜。N型功函數調整膜170可藉由調整N型電晶體的功函數而調整N型電晶體的操作特性。N型功函數調整膜170可為選自由TiAl、TiAlN、TaC、TiC與HfSi所組成的族群中的材料。舉例來說,N型功函數調整膜170可為TiAl膜。黏著膜180可包括TiN與Ti中的至少一者。或者,黏著膜180可為依序堆疊的TiN膜與Ti膜。黏著膜180可增加後續製程中所形成的金屬閘極圖案190的黏著力。金屬閘極圖案190可形成於溝渠112中的黏著膜180上,以填滿溝渠112。金屬閘極圖案190可為Al、W或類似物,但不限於此。
N型功函數調整膜170可沿著溝渠112的側壁而配置,且可包括相對於溝渠112的第一側壁形成銳角的斜面276。
此外,半導體裝置4可包括第二置換金屬閘極,第二置換金屬閘極可包括蝕刻終止膜240、P型功函數調整膜250、N型功函數調整膜270、黏著膜280、金屬閘極圖案290等等。P型功函數調整膜250可包括相對於溝渠112的第一側壁與第二側壁形成銳角的斜面(例如斜面256)。N型功函數調整膜270亦可包括相對於溝渠112的第一側壁形成銳角的斜面276。
雖然未繪示於圖中,將理解的是,圖3或圖4中的P型電晶體的閘極結構可選擇性地使用於第二區域II中。
圖6為根據本發明的概念的第五實施例的半導體裝置5的立體圖。圖7為沿圖6的線A-A'的剖面圖。圖8為沿圖6的線B-B'的剖面圖。圖6至圖8描述本發明的概念的實施例,其中繪示於圖1中的P型電晶體的閘極應用於鰭狀電晶體(FinFET)。
參照圖6至圖8,根據本發明的概念的第五實施例的半導體裝置5可包括鰭F1、閘極電極222、凹陷225、源極/汲極261與類似物。
鰭F1可沿著第二方向Y1而延伸。鰭F1可為基底200的一部分,且可包括自基底200成長的磊晶層。元件隔離膜201可覆蓋鰭F1的側面。
閘極電極222可形成於鰭F1上,以與鰭F1交叉。閘極電極222可沿著第一方向X1延伸。
如圖所示,閘極電極222可包括蝕刻終止膜240、P型功函數調整膜250、N型功函數調整膜270、黏著膜280、金屬閘極圖案290與類似物。
凹陷225可形成於閘極電極222二側的鰭F1中。由於凹陷225的側壁為傾斜的,因此凹陷225的寬度可隨著離基底100的距離增加而增加。如圖6所示,凹陷225的寬度可大於鰭F1的寬度。
源極/汲極261形成於凹陷225中。源極/汲極261可具有高起的源極/汲極形狀。也就是說,源極/汲極261的上表面可高於元件隔離膜201的上表面。此外,源極/汲極261與閘極電極222
可藉由間隙壁220而彼此隔離。如圖6中所示,可提供二個凹陷225與二個源極/汲極261,其中一個凹陷225與一個源極/汲極261提供於閘極電極222的其中一側。
在根據本發明的概念的第五實施例的半導體裝置5為P型電晶體的情況下,源極/汲極261可包括壓縮應力材料。舉例來說,壓縮應力材料可為晶格常數大於Si的材料,且可為例如是SiGe。壓縮應力材料可施加壓縮應力至鰭F1,以改善通道區中載子的遷移率。
雖然未繪示,將瞭解的是,圖3與圖4中的P型電晶體的閘極亦可應用於後續本發明的其他實施例的鰭型電晶體。
在根據本發明的概念的實施例的N型電晶體的閘極(例如形成於圖5的第一區域I中的閘極)應用於鰭型電晶體的情況下,源極/汲極261可含有與基底或壓縮應力材料相同的材料。舉例來說,若基底含有Si,則源極/汲極可含有Si或晶格常數小於Si(對於包括矽基底的實施例來說)的材料(例如SiC)。
圖9與圖10分別為根據本發明的概念的第六實施例的半導體裝置6的電路圖與佈局圖。
參照圖9與圖10,根據本發明的概念的第六實施例的半導體裝置6可包括一對反相器(inverter)INV1、INV2,其在電源供應節點(power supply node)Vcc與接地節點(ground node)Vss之間並聯連接;以及第一通路電晶體(pass transitor)PS1與第二通路電晶體PS2,其連接至反相器INV1與INV2各自的輸出節點(output
node)。第一通路電晶體PS1與第二通路電晶體PS2可分別連接至位元線BL與輔助位元線/BL。第一通路電晶體PS1與第二通路電晶體PS2的閘極可連接至字元線WL。
第一反相器INV1包括串聯連接的第一上拉電晶體(pull-up transistor)PU1與第一下拉電晶體(pull-down transistor)PD1。第二反相器INV2包括串聯連接的第二上拉電晶體PU2與第二下拉電晶體PD2。第一上拉電晶體PU1與第二上拉電晶體PU2可為PMOS電晶體,且第一下拉電晶體PD1與第二下拉電晶體PD2可為NMOS電晶體。
此外,第一反相器INV1與第二反相器INV2經組態使得第一反相器INV1的輸入節點(input node)連接至第二反相器INV2的輸出節點以及第二反相器INV2的輸入節點連接至第一反相器INV1的輸出節點,以構成閂鎖電路(latch circuit)。
參照圖9與圖10,彼此分離的第一主動區310、第二主動區320、第三主動區330與第四主動區340形成為在一個方向(例如圖10的垂直方向)上延伸。第二主動區320與第三主動區330的延伸長度可小於第一主動區310與第四主動區340的延伸長度。
此外,第一閘極電極351、第二閘極電極352、第三閘極電極353與第四閘極電極354在另一方向(例如圖10的水平方向)上延伸,且形成為與第一主動區310至第四主動區340交錯。特別是,第一閘極電極351可完全地與第一主動區310以及第二主動區320交錯,且可至少部分地與第三主動區330的終點重疊。
第三閘極電極353可完全地與第四主動區340以及第三主動區330交錯,且可至少部分地與第二主動區320的終點重疊。第二閘極電極352與第四閘極電極354分別形成為與第一主動區310以及第四主動區340交錯。
如圖所示,第一上拉電晶體PU1定義在第一閘極電極351與第二主動區320的交錯處的周圍,第一下拉電晶體PD1定義在第一閘極電極351與第一主動區310的交錯處的周圍,且第一通路電晶體PS1定義在第二閘極電極352與第一主動區310的交錯處的周圍。第二上拉電晶體PU2定義在第三閘極電極353與第三主動區330的交錯處的周圍,第二下拉電晶體PD2定義在第三閘極電極353與第四主動區340的交錯處的周圍,且第二通路電晶體PS2定義在第四閘極電極354與第四主動區340的交錯處的周圍。
源極/汲極可形成於第一閘極電極351至第四閘極電極354與第一主動區310、第二主動區320、第三主動區330與第四主動區340的每一交錯處的二側。
此外,可形成多個接觸窗350。
另外,共用接觸窗361與第二主動區320、第三閘極電極353以及導線371電性連接。共用接觸窗362與第三主動區330、第一閘極電極351以及導線372電性連接。
舉例來說,第一上拉電晶體PU1與第二上拉電晶體PU2可具有參照圖1至圖6中的至少一者所描述的架構。第一下拉電
晶體PD1、第一通路電晶體PS1、第二下拉電晶體PD2與第二通路電晶體PS2可具有包括形成於圖5的第一區域I中的閘極的架構。
圖11為包括根據本發明的概念的一些實施例的半導體裝置的電子系統的方塊圖。
參照圖11,電子系統1100包括控制器1110、輸入/輸出(I/O)裝置1120、記憶體裝置1130、介面1140與匯流排1150。控制器1110、I/O裝置1120、記憶體裝置1130和/或介面1140可經由匯流排1150而彼此連接。匯流排1150提供可傳輸資料的路徑。
控制器1110可包括微處理器、數位信號處理器、微控制器與其他進行類似功能的邏輯裝置中的至少一者。I/O裝置1120可包括小型鍵盤、鍵盤和/或顯示裝置。記憶體裝置1130可儲存資料和/或指令。介面1140用以傳送資料至通訊網路或自通訊網路接收資料。介面1140可為有線介面或無線介面。舉例來說,介面1140可包括天線或有線/無線收發器。雖然圖中未繪示,但電子系統1100可更包括做為操作記憶體的高速DRAM和/或SRAM,以改善控制器1110的操作。根據本發明的概念的實施例中的鰭場效電晶體可提供於記憶體裝置1130中及/或可提供做為控制器1110與I/O裝置1120的一部分。
舉例來說,電子系統1100可應用至個人數位助理(personal digital assistant,PDA)、攜帶式電腦、網路平板電腦、無線電話、行動電話、數位音樂撥放器、記憶卡或各種在無線環
境中能夠傳送和/或接收訊息的電子產品。
圖12與圖13為根據本發明的概念的一些實施例的半導體裝置可應用的示例性的半導體系統。圖12繪示出平板電腦,而圖13繪示出筆記型電腦。根據本發明的概念的實施例的半導體裝置1至半導體裝置6中的至少一者可用於平板電腦、筆記型電或類似物中。將瞭解的是,根據本發明的概念的實施例的半導體裝置可應用於其他未繪示的積體電路裝置。
在此,將參照圖1以及圖14至圖21來描述根據本發明的概念的第一實施例的半導體裝置的製造方法。圖14至圖21為製造根據本發明的概念的第一實施例的半導體裝置的中間步驟的示意圖。
首先,如圖14所示,提供其中定義有第一區域I與第二區域II的基底100。
在第一區域I中,形成犧牲閘極圖案119,以及於犧牲閘極圖案119的側壁形成間隙壁120。層間絕緣膜110圍繞犧牲閘極圖案119與間隙壁120,同時暴露出犧牲閘極圖案119的上表面。
在第二區域II中,形成犧牲閘極圖案219,以及於犧牲閘極圖案219的側壁形成間隙壁220。層間絕緣膜210圍繞犧牲閘極圖案219與間隙壁220,同時暴露出犧牲閘極圖案219的上表面。
犧牲閘極圖案119與犧牲閘極圖案219例如可由多晶矽形成,但並不限於此。
參照圖15,移除犧牲閘極圖案119與犧牲閘極圖案219,
使得在第一區域I中層間絕緣膜110包括溝渠112以及在第二區域II中層間絕緣膜210包括溝渠212。
接著,在溝渠112中形成閘極絕緣膜130a,以及在溝渠212中形成閘極絕緣膜230a。閘極絕緣膜130a共形地沿著溝渠112的底面與側壁以及層間絕緣膜110的上表面而形成。閘極絕緣膜230a共形地沿著溝渠212的底面與側壁以及層間絕緣膜210的上表面而形成。閘極絕緣膜130a與閘極絕緣膜230a可為高介電常數膜。
然後,於溝渠112中的閘極絕緣膜130a上形成蝕刻終止膜140a,以及於溝渠212中的閘極絕緣膜230a上形成蝕刻終止膜240a。蝕刻終止膜140a與蝕刻終止膜240a亦分別形成於層間絕緣膜110與層間絕緣膜210上,且可為共形地形成。
參照圖16,P型功函數調整膜150a與P型功函數調整膜250a形成於蝕刻終止膜140a與蝕刻終止膜240a上。
如圖所示,P型功函數調整膜150a與P型功函數調整膜250a共形地沿著溝渠112的底面與側壁、層間絕緣膜110的上表面、溝渠212的底面與側壁以及層間絕緣膜210的上表面而形成。
P型功函數調整膜150a與P型功函數調整膜250a例如可含有TiN。
參照圖17,移除形成於第一區域I中的P型功函數調整膜150a,且保留形成於第二區域II中的P型功函數調整膜250a。也就是說,P型功函數調整膜250a保留在溝渠212中的閘極絕緣
膜230a上。
參照圖18,N型功函數調整膜170a形成於溝渠112中的蝕刻終止膜140a上,而N型功函數調整膜270a形成於溝渠212中的P型功函數調整膜250a上。
如圖所示,N型功函數調整膜170a與N型功函數調整膜270a共形地沿著溝渠112的底面與側壁、層間絕緣膜110的上表面、溝渠212的底面與側壁以及層間絕緣膜210的上表面而形成。
參照圖19,硬罩幕198形成於第一區域I中的N型功函數調整膜170a上,而硬罩幕298形成於第二區域II中的N型功函數調整膜270a上。
如圖所示,硬罩幕198與硬罩幕298分別共形地沿著溝渠112的底面與側壁、層間絕緣膜110的上表面、溝渠212的底面與側壁以及層間絕緣膜210的上表面而形成。
硬罩幕198與硬罩幕298可為氧化物膜、氮氧化物膜、氮化物膜或類似物,但不限於此。
參照圖20,覆蓋第一區域I且暴露第二區域II的形成光阻膜199。
接著,移除第二區域II中的部分N型功函數調整膜270a(參照圖19)與部分P型功函數調整膜250a(參照圖19)。如此一來,N型功函數調整膜270包括相對於溝渠212的第一側壁形成銳角θ 2的斜面276,而P型功函數調整膜250包括相對於溝渠212的第一側壁形成銳角θ 1的斜面256。
舉例來說,可使用反應性離子蝕刻(reactive ion etching,RIE)來進行蝕刻。特別是,可進行蝕刻以自層間絕緣膜210的上表面移除硬罩幕298。當蝕刻層間絕緣膜210的上表面上的刻硬罩幕298時,P型功函數調整膜250a與N型功函數調整膜270a的電場集中的邊緣部分被蝕刻較多。也就是說,P型功函數調整膜250a與N型功函數調整膜270a的位於溝渠212的入口處的邊緣部分被較重地蝕刻。因此,如圖所示,整個的P型功函數調整膜250與N型功函數調整膜270可具有倒角的形狀。也就是說,P型功函數調整膜250與N型功函數調整膜270各自可具有相對於溝渠212的側壁形成銳角的斜面。同時,在將P型功函數調整膜250a與N型功函數調整膜270a去角之後,部分硬罩幕298可保留於第二區域II的溝渠212中。
然後,移除光阻膜199。
接著,移除硬罩幕298的保留部分。
參照圖21,於溝渠112中的N型功函數調整膜170a上形成黏著膜180a,以及於溝渠212中的N型功函數調整膜270b上形成黏著膜280a。
之後,於溝渠112中的黏著膜180a上形成金屬閘極圖案190a以填滿溝渠112,以及溝渠212中的黏著膜280a上形成金屬閘極圖案290a以填滿溝渠212。
由於P型功函數調整膜250b與N型功函數調整膜270b為倒角的,因此溝渠212的入口為寬廣的。此可使得金屬閘極圖
案290a較容易地填滿溝渠212。
再次參照圖1,進行平坦化製程,以暴露出層間絕緣膜210的上表面。經由平坦化製程,在第一區域I中完成N型電晶體的第一置換金屬閘極,以及在第二區域II中完成P型電晶體的第二置換金屬閘極。第二置換金屬閘極可包括倒角的P型功函數調整膜250與N型功函數調整膜270。
在此,將參照圖3以及圖22來描述根據本發明的概念的第二實施例的半導體裝置的製造方法。圖22為製造根據本發明的概念的第二實施例的半導體裝置的中間步驟的示意圖。為了簡化說明,以下描述將著重於與上述根據本發明的概念的第一實施例的半導體裝置的製造方法不同的步驟。圖22為顯示在圖19的步驟之後進行的製造步驟的示意圖。
在根據本發明的概念的第一實施例的半導體裝置的製造方法中,硬罩幕198形成於第一區域I中的N型功函數調整膜170a上,且硬罩幕298形成於第二區域II中的N型功函數調整膜270a上(參照圖19)。使用光阻膜199蝕刻形成於第二區域II中的部分P型功函數調整膜250a與部分N型功函數調整膜270a。由於光阻膜199未暴露第一區域I,因此第一區域I中的N型功函數調整膜170a未被蝕刻(參照圖20)。
在根據本發明的概念的第二實施例的半導體裝置的製造方法中,不使用光阻膜199(參照圖20)。因此,基底100與基底200的整個表面被蝕刻。也就是說,當第二區域II中的部分P型
功函數調整膜250a(參照圖19)與部分N型功函數調整膜270a(參照圖19)被蝕刻時,第一區域I中的部分N型功函數調整膜170a也被蝕刻。因此,N型功函數調整膜170具有相對於溝渠112的側壁具有銳角的斜面。在此例中,在將P型功函數調整膜250a與N型功函數調整膜270a去角之後,部分硬罩幕可保留於溝渠112與溝渠212中。
然後,移除硬罩幕的保留部分。
再次參照圖3,於溝渠212中N型功函數調整膜270b的上形成黏著膜280a。接著,於溝渠21中的黏著膜280a上形成2金屬閘極圖案290a,以填滿溝渠212。然後,進行平坦化製程,以暴露出層間絕緣膜210的上表面。
在此,將參照圖23至圖26來描述根據本發明的概念的第三實施例的半導體裝置的製造方法。圖23至圖26為製造根據本發明的概念的第三實施例的半導體裝置的中間步驟的示意圖。圖23為顯示在圖19的步驟之後進行的製造步驟的示意圖。
參照圖23,硬罩幕圖案297形成於暴露第一區域I以及覆蓋第二區域II的P型功函數調整膜150a與P型功函數調整膜250a上(參照圖16)。
接著,使用硬罩幕圖案297來移除第一區域I的P型功函數調整膜150a。
參照圖24,在移除第一區域I的P型功函數調整膜150a之後,於第一區域I與第二區域II上形成N型功函數調整膜170a
與N型功函數調整膜270a。
參照圖25,光阻圖案293形成於暴露第二區域II以及覆蓋第一區域I的N型功函數調整膜170a與N型功函數調整膜270a上。
接著,移除第二區域II的N型功函數調整膜270a。此例如可藉由使用光阻圖案293做為蝕刻罩幕的濕式蝕刻來實行。由於硬罩幕圖案297位於N型功函數調整膜270a與P型功函數調整膜250a之間,因此可移除N型功函數調整膜270a而不影響P型功函數調整膜250a。
然後,移除硬罩幕圖案297。
參照圖26,於溝渠112中的N型功函數調整膜170a(參照圖25)以及溝渠212中的P型功函數調整膜250a(參照圖25)上形成黏著膜180與黏著膜280。
接著,將金屬材料填入溝渠112與溝渠212中。在本實施例中,溝渠212中未包括N型功函數調整膜270且僅包括P型功函數調整膜250。因此,由於溝渠212的入口為寬廣的,所以更容易將金屬材料沈積於溝渠212中。
然後,進行平坦化製程,以暴露出層間絕緣膜110與層間絕緣膜210的上表面。
因此,第二區域II的第二置換金屬閘極未包括N型功函數調整膜270且僅包括P型功函數調整膜250。
1‧‧‧半導體裝置
200‧‧‧基底
210‧‧‧層間絕緣膜
212‧‧‧溝渠
220‧‧‧間隙壁
230‧‧‧閘極絕緣膜
240‧‧‧蝕刻終止膜
250‧‧‧P型功函數調整膜
270‧‧‧N型功函數調整膜
280‧‧‧黏著膜
290‧‧‧金屬閘極圖案
Claims (20)
- 一種半導體裝置,包括:基底;層間絕緣膜,包括位於所述基底上的溝渠;閘極絕緣膜,位於所述溝渠中;功函數調整膜,位於所述溝渠中的所述閘極絕緣膜上,且沿著所述溝渠的第一側壁、第二側壁與底面,所述功函數調整膜包括相對於所述溝渠的所述第一側壁而形成銳角的斜面;以及金屬閘極圖案,位於所述功函數調整膜上,填滿所述溝渠。
- 如申請專利範圍第1項所述的半導體裝置,其中所述功函數調整膜包括第一功函數調整膜,所述斜面包括第一斜面,且所述銳角包括第一銳角,所述半導體裝置更包括位於所述第一功函數調整膜上的第二功函數調整膜。
- 如申請專利範圍第2項所述的半導體裝置,其中所述第二功函數調整膜具有第二斜面,所述第二斜面相對於所述溝渠的所述第一側壁而形成第二銳角,且所述第一斜面與所述第二斜面形成連續表面。
- 如申請專利範圍第2項所述的半導體裝置,其中自所述層間絕緣膜的上表面至沿著所述第一功函數調整膜的頂面的中點的第一深度不同於自所術層間絕緣膜的上表面至沿著所述第二功函數調整膜的頂面的中點的第二深度。
- 如申請專利範圍第4項所述的半導體裝置,其中所述第一深度小於所述第二深度。
- 如申請專利範圍第2項所述的半導體裝置,其中所述第二功函數調整膜具有相對於所述溝渠的所述第一側壁而形成直角的上表面。
- 如申請專利範圍第1項所述的半導體裝置,其中所述功函數調整膜的上部的寬度隨著離所述溝渠的所述底面的距離增加而增加。
- 一種半導體裝置,包括:基底;層間絕緣膜,位於所述基底上,包括彼此分離的第一溝渠與第二溝渠;NMOS電晶體,包括形成於所述第一溝渠中的第一金屬閘極;以及PMOS電晶體,包括形成於所述第二溝渠中的第二金屬閘極,其中所述第一金屬閘極包括第一N型功函數調整膜,所述第一N型功函數調整膜沿著所述第一溝渠的第一側壁、第二側壁與底面而形成,所述第二金屬閘極包括P型功函數調整膜與第二N型功函數調整膜,所述P型功函數調整膜與所述第二N型功函數調整膜沿著所述第二溝渠的第一側壁、第二側壁與底面而依序堆疊,且 所述第二N型功函數調整膜包括相對於所述第二溝渠的第一側壁而形成銳角的第一斜面。
- 如申請專利範圍第8項所述的半導體裝置,其中所述P型功函數調整膜包括相對於所述第二溝渠的第一側壁而形成銳角的第二斜面。
- 如申請專利範圍第9項所述的半導體裝置,其中所述第一斜面與所述第二斜面彼此連續。
- 如申請專利範圍第8項所述的半導體裝置,其中所述第一N型功函數調整膜包括包括相對於所述第一溝渠的第二側壁而形成銳角的第三斜面。
- 一種半導體裝置,包括:層間絕緣膜,包括位於基底上的溝渠;閘極絕緣膜,形成於所述溝渠中;第一TiN膜,位於所述溝渠中的所述閘極絕緣膜的上表面上;TaN膜,位於所述溝渠中的所述第一TiN膜的上表面上;第二TiN膜,位於所述溝渠中的所述TaN膜的上表面上;以及TiAl膜,位於所述溝渠中的所述第二TiN膜的上表面上,其中所述第二TiN膜與所述TiAl膜中的一者包括相對於所述溝渠的至少一側壁而具有銳角的斜面。
- 一種半導體裝置的製造方法,包括: 於基底上形成層間絕緣膜,以包括溝渠;於所述溝渠中形成閘極絕緣膜;沿著所述溝渠的側壁與底面以及所述層間絕緣膜的上表面於閘極絕緣膜上形成功函數調整膜;移除部分所述功函數調整膜,使得所述功函數調整膜包括相對於所述溝渠的側壁而具有銳角的斜面;以及於所述功函數調整膜上形成金屬閘極圖案,以填滿所述溝渠。
- 如申請專利範圍第13項所述的半導體裝置的製造方法,其中移除部分所述功函數調整膜包括:沿著所述溝渠的側壁與底面以及所述層間絕緣膜的上表面於所述功函數調整膜上形成硬罩幕;以及蝕刻並移除形成於所述層間絕緣膜的上表面上的所述硬罩幕。
- 一種半導體裝置的製造方法,包括:提供包括第一區域與第二區域的基底;於所述基底上形成層間絕緣膜,所述層間絕緣膜包括形成於所述第一區域中的第一溝渠以及形成於所述第二區域中的第二溝渠;於所述第一溝渠中形成第一閘極絕緣膜以及於所述第二溝渠中形成第二閘極絕緣膜; 於所述第二閘極絕緣膜上形成第一功函數調整膜,所述第一功函數調整膜沿著所述第二溝渠的側壁與底面以及所述層間絕緣膜的上表面而配置;於所述第一閘極絕緣膜與所述第一功函數調整膜上形成第二功函數調整膜,所述第二功函數調整膜沿著所述第一溝渠的側壁與底面、所述第二溝渠的側壁與底面以及所述層間絕緣膜的上表面而配置;移除部分所述第二功函數調整膜,使得所述第二功函數調整膜包括相對於所述第二溝渠的側壁而具有銳角的第一斜面;以及形成第一金屬閘極圖案以填滿所述第一溝渠以及形成第二金屬閘極圖案以填滿所述第二溝渠。
- 一種半導體裝置,包括:基底;層間絕緣膜,具有位於所述基底上的溝渠;閘極絕緣膜,位於所述溝渠的第一側壁、第二側壁與底面上;以及功函數調整膜,位於所述閘極絕緣膜上,所述功函數調整膜具有第一側壁與、第二側壁與底面,其中所述功函數調整膜第一側壁與第二側壁的上部為倒角的。
- 如申請專利範圍第16項所述的半導體裝置,更包括位於所述閘極絕緣膜與所述功函數調整膜之間的蝕刻終止膜。
- 如申請專利範圍第16項所述的半導體裝置,其中所述功函數調整膜包括第一功函數調整膜,所述半導體裝置更包括位於所述第一功函數調整膜與所述閘極絕緣膜之間的第二功函數調整膜。
- 如申請專利範圍第18項所述的半導體裝置,其中所述第二功函數調整膜具有第一側壁、第二側壁與底面,且其中所述第二功函數調整膜的第一側壁與第二側壁的上部為倒角的。
- 如申請專利範圍第18項所述的半導體裝置,其中所述第二功函數調整膜具有第一側壁、第二側壁與底面,且其中所述第二功函數調整膜的第一側壁與第二側壁的上部不為倒角的。
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US9324716B2 (en) | 2016-04-26 |
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CN103390638A (zh) | 2013-11-13 |
US9627380B2 (en) | 2017-04-18 |
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US20130299918A1 (en) | 2013-11-14 |
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US9721952B2 (en) | 2017-08-01 |
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