CN108022874B - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN108022874B
CN108022874B CN201610927451.9A CN201610927451A CN108022874B CN 108022874 B CN108022874 B CN 108022874B CN 201610927451 A CN201610927451 A CN 201610927451A CN 108022874 B CN108022874 B CN 108022874B
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CN108022874A (zh
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Abstract

本发明公开了一种半导体装置的制造方法，涉及半导体技术领域。所述方法包括：提供包括具有第一沟槽的PMOS区域和具有第二沟槽的NMOS区域的衬底结构，第一和第二沟槽的底面和侧面具有高K电介质层和在高K电介质层上的第一P型功函数调节层；在衬底结构上依次形成第一和第二保护层；在第二保护层上沉积掩模层；通过干法刻蚀工艺去除NMOS区域上的掩模层，以暴露NMOS区域上的第二保护层；去除NMOS区域上的第二保护层，以暴露NMOS区域上的第一保护层；通过干法刻蚀工艺去除PMOS区域上的掩模层，以暴露PMOS区域上的第二保护层；去除NMOS区域上的第一保护层和第一P型功函数调节层；去除PMOS区域上的第二和第一保护层。本发明可以减小高K电介质层受到的损害。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体装置的制造方法。
背景技术
在包括NMOS器件和PMOS器件的半导体装置的制造工艺中，往往需要通过功函数调节层来调节栅极的功函数。一个典型的这样的制造工艺通常会包括如下步骤：在NMOS区域和PMOS区域上沉积高K电介质层，在高K电介质层上沉积P型功函数调节层，在P型功函数调节层上沉积掩模层(例如光刻胶)，去除NMOS区域的掩模层，去除NMOS区域的P型功函数调节层，以及去除PMOS区域的掩模层。
本公开的发明人发现：在通过干法刻蚀工艺去除NMOS区域和PMOS区域的掩模层时，由于掩模层下的功函数调节层通常是导电的，因此，等离子体会对功函数调节层下的高K电介质层造成损害，从而影响器件的性能。
发明内容
本公开的一个目的在于减小在去除掩模层时高K电介质层受到的损害。
根据本公开的一个实施例，提供了一种半导体装置的制造方法，包括：提供衬底结构，所述衬底结构包括具有第一沟槽的PMOS区域和具有第二沟槽的NMOS区域，所述第一沟槽和所述第二沟槽的底面和侧面具有高K电介质层和在所述高K电介质层上的第一P型功函数调节层；在所述衬底结构上依次形成第一保护层和第二保护层；在所述第二保护层上沉积掩模层；通过干法刻蚀工艺去除NMOS区域上的掩模层，以暴露NMOS区域上的第二保护层；去除NMOS区域上的第二保护层，以暴露NMOS区域上的第一保护层；通过干法刻蚀工艺去除PMOS区域上的掩模层，以暴露PMOS区域上的第二保护层；去除NMOS区域上的第一保护层和第一P型功函数调节层；去除PMOS区域上的第二保护层和第一保护层。
在一个实施例中，所述第一保护层包括硅的氧化物；所述第二保护层包括非晶硅或多晶硅。
在一个实施例中，采用稀释的HF去除NMOS区域和PMOS区域上的第一保护层。
在一个实施例中，采用NH4OH或TMAH去除NMOS区域和PMOS区域上第二保护层。
在一个实施例中，所述第一沟槽中具有第一鳍片，所述第二沟槽中具有第二鳍片；在所述第一鳍片和所述第二鳍片的上表面和侧面依次形成有所述高K电介质层和所述第一P型功函数调节层。
在一个实施例中，所述提供衬底结构的步骤包括：提供初始衬底结构，所述初始衬底结构包括具有第一沟槽的PMOS区域和具有第二沟槽的NMOS区域；在所述第一沟槽和所述第二沟槽的底面和侧面沉积高K电介质层；在所述高K电介质层上沉积帽层，所述帽层包括TiN层和在TiN层上的非晶硅层；去除所述帽层，从而形成所述衬底结构。
在一个实施例中，所述方法还包括：在PMOS区域上的第一P型功函数调节层和NMOS区域上的高K电介质层上沉积第二P型功函数调节层；在所述第二P型功函数调节层上沉积N型功函数调节层；在所述N型功函数调节层之上沉积金属。
在一个实施例中，所述在所述N型功函数调节层之上沉积金属包括：在所述N型功函数金属层上沉积粘附层；在所述粘附层上沉积金属。
在一个实施例中，所述方法还包括：对沉积的金属进行平坦化。
在一个实施例中，所述第一P型功函数调节层包括TiN、TaN或TaC；所述第二P型功函数调节层包括TiN、TaN或TaC。
在一个实施例中，所述N型功函数金属层包括TiAl、TiCAl、TiNAl或TiSiAl。
在一个实施例中，所述第一沟槽和所述第二沟槽的底面与所述高K电介质层之间具有界面层。
本公开提供的半导体装置的制造方法中，在通过干法刻蚀工艺去除NMOS区域上的掩模层时，第一保护层可以减小高K电介质层受到的等离子的损害；在去除PMOS区域上的掩模层时，第一保护层和第二保护层可以减小PMOS和NMOS区域的高K电介质层受到的等离子的损害，从而提升了器件的性能。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本公开的示例性实施例，并且连同说明书一起用于解释本发明的原理，在附图中：
图1是根据本公开一个实施例的半导体装置的制造方法的简化流程图；
图2-图14示出了根据本公开的一些实施例的半导体装置的制造方法的各个阶段的示意截面图。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本发明范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
图1是根据本公开一个实施例的半导体装置的制造方法的简化流程图。图2-图14示出了根据本公开的一些实施例的半导体装置的制造方法的各个阶段的示意截面图。下面结合图1、以及图2-图14对本公开的半导体装置的制造方法进行详细说明。
如图1所示，首先，在步骤102，提供衬底结构。
图2是根据本公开一个实施例的衬底结构的示意截面图。如图2所示，衬底结构包括具有第一沟槽201的PMOS区域和具有第二沟槽202的NMOS区域。PMOS区域和NMOS区域可以通过隔离结构(例如浅沟槽隔离结构)隔离开。第一沟槽201和第二沟槽202的底面和侧面具有高K电介质层203和在高K电介质层203上的第一P型功函数调节层204。在一个实施例中，第一沟槽201中可以具有第一鳍片211，第二沟槽202中可以具有第二鳍片212，第一鳍片211和第二鳍片212位于衬底200上。在第一鳍片211和第二鳍片212的上表面和侧面依次形成有高K电介质层和第一P型功函数调节层。示例性地，高K电介质层可以包括但不限于氧化铪、氧化钽、氧化铝、氧化锆或氧化钛等其他高K电介质材料，第一P型功函数调节层可以包括但不限于TiN、TaN或TaC等。第一P型功函数调节层的厚度可以为约20-30埃，例如25埃等。
在一个实现方式中，可以通过如下方式来形成上述衬底结构：
步骤S1，提供初始衬底结构，该初始衬底结构包括具有第一沟槽201的PMOS区域和具有第二沟槽202的NMOS区域。例如可以通过如下步骤形成第一沟槽和第二沟槽：在沉积层间介质层205之后，进行平坦化工艺，以暴露第一沟槽201和第二沟槽202中的伪栅，然后去除伪栅和伪栅下的伪栅氧化层，从而形成第一沟槽201和第二沟槽202。第一沟槽201和第二沟槽202的侧壁上保留有间隔物206。间隔物206例如可以是硅的氧化物、硅的氮化物、硅的氮氧化物等等。
步骤S2，沉积高K电介质层203，从而在第一沟槽201和第二沟槽202的底面和侧面形成高K电介质层203。优选地，在沉积高K电介质层301之前，可以在第一沟槽201和/或第二沟槽202的底面上形成界面层(Interface Layer，IL)，例如热氧化层，从而改善高K电介质层与第一沟槽201和/或第二沟槽202的底面之间的界面性质。
步骤S3，沉积第一P型功函数调节层204，从而在高K电介质层203上形成第一P型功函数调节层204，如此形成了衬底结构。
在另一个实现方式中，在上述步骤S2与步骤S3之间还可以包括如下步骤：
步骤S4，在高K电介质层203上沉积帽层。这里，帽层可以包括TiN层和在TiN层上的非晶硅层。之后，可以进行尖峰退火。尖峰退火的温度范围例如可以是800-1000℃，例如900℃、950℃等。
步骤S5，去除帽层。
该实现方式中，通过在高K电介质层上沉积帽层再去除帽层的方式可以改善高K电介质层的性能，有利于提升器件的可靠性。
另外，如图2所示，在第一沟槽201的两侧的第一半导体鳍片211中以及第二沟槽202的两侧的第二半导体鳍片212中可以分别形成有抬升的源区/漏区221和抬升的源区/漏区222。在PMOS区域中，抬升的源区/漏区221可以通过外延生长SiGe来形成，外延生长的SiGe可以向沟道区引入压应力，从而提高空穴的迁移率。在NMOS区域中，抬升的源区/漏区222可以通过外延生长SiC或Si来形成，外延生长的SiC或Si可以向沟道区引入拉应力，从而提高电子的迁移率。
回到图1，在步骤104，在衬底结构上依次形成第一保护层301和第二保护层302，如图3所示。在一个实施例中，第一保护层301可以包括硅的氧化物，例如二氧化硅等；第二保护层302可以包括非晶硅或多晶硅。优选地，第二保护层302为非晶硅。应理解，第一保护层301和第二保护层302的材料并不限于上面给出的优选材料，本领域技术人员可以根据实际需求选取合适的材料作为保护材料。另外，第一保护层301的厚度可以是约5-15埃，例如10埃等。第二保护层302的厚度可以是约15-25埃，例如20埃等。
然后，在步骤106，在第二保护层302上沉积掩模层401，如图4所示。掩模层401例如可以包括光刻胶。优选地，光刻胶的底部可以有底部抗反射涂层BARC(Bottom AntiReflective Coating)，光刻胶的顶部可以有顶部抗反射涂层TARC(Bottom AntiReflective Coating)。
接下来，在步骤108，通过干法刻蚀工艺去除NMOS区域上的掩模层401，以暴露NMOS区域上的第二保护层302，如图5所示。在去除NMOS区域上的掩模层401时由于有第一保护层301和第二保护层302的保护，从而可以减小NMOS区域的高K电介质层受到的等离子的损害。
之后，在步骤110，去除NMOS区域上的第二保护层302，以暴露NMOS区域上的第一保护层301，如图6所示。在一个实施例中，可以通过湿法刻蚀，例如采用NH4OH或TMAH作为刻蚀液去除NMOS区域上的第二保护层302。
接下来，在步骤112，通过干法刻蚀工艺去除PMOS区域上的掩模层401，以暴露PMOS区域上的第二保护层302，如图7所示。在去除PMOS区域上的掩模层401时，PMOS区域有第一保护层301和第二保护层302的保护，NMOS区域有第一保护层301的保护，从而可以减小PMOS和NMOS区域的高K电介质层受到的等离子的损害。
之后，在步骤114，去除NMOS区域上的第一保护层301(如图8所示)和第一P型功函数调节层204(如图9所示)。在一个实施例中，可以通过湿法刻蚀，例如采用稀释的HF去除NMOS区域上的第一保护层301。另外，可以采用SC1或SC2清洗液去除第一P型功函数调节层204。这里，SC1清洗液例如可以包括氢氧化铵、双氧水和去离子水等。SC2清洗液例如可以包括盐酸、双氧水和去离子水等。
之后，在步骤116，去除PMOS区域上的第二保护层302和第一保护层301，如图10所示。在一个实施例中，可以通过湿法刻蚀去除PMOS区域上的第二保护层302和第一保护层301。例如，可以采用NH4OH或TMAH作为刻蚀液去除NMOS区域上的第二保护层301，可以采用稀释的HF去除NMOS区域上的第一保护层301。
如上描述了根据本公开实施例的半导体装置的制造方法。根据该方法，在通过干法刻蚀工艺去除NMOS区域上的掩模层时，第一保护层可以减小高K电介质层受到的等离子的损害；在去除PMOS区域上的掩模层时，第一保护层和第二保护层可以减小PMOS和NMOS区域的高K电介质层受到的等离子的损害，从而提升了器件的性能。
在去除PMOS区域上的第二保护层302和第一保护层301之后，可以进行后续的工艺，例如形成栅极等。
图11-图14提供了根据本公开一些实施例的后续工艺的不同阶段。
如图11所示，在PMOS区域上的第一P型功函数调节层204和NMOS区域上的高K电介质层203上沉积第二P型功函数调节层1101。第二P型功函数调节层1101可以包括但不限于TiN、TaN或TaC等。第二P型功函数调节层1101的厚度可以为约10-20埃，例如15埃等。
如图12所示，在第二P型功函数调节层1101上沉积N型功函数调节层1201。这里，N型功函数调节层1201可以包括但不限于TiAl、TiCAl、TiNAl或TiSiAl等。
如图13所示，在N型功函数调节层1201之上沉积金属1301，例如钨等，从而形成金属电极。在一个实施例中，可以在N型功函数调节层1301上沉积粘附层，例如TiN、Ti或者二者组成的叠层结构；然后在粘附层上沉积金属1301，从而使得金属1301与N型功函数调节层1201之间的结合更加紧密。
之后，还可以对沉积的金属1301进行平坦化，例如化学机械抛光，如图14所示。
至此，已经详细描述了根据本公开实施例的半导体装置的制造方法。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本公开的精神和范围。

Claims (12)

1.一种半导体装置的制造方法，其特征在于，包括：
提供衬底结构，所述衬底结构包括具有第一沟槽的PMOS区域和具有第二沟槽的NMOS区域，所述第一沟槽和所述第二沟槽的底面和侧面具有高K电介质层和在所述高K电介质层上的第一P型功函数调节层；
在所述衬底结构上依次形成第一保护层和第二保护层；
在所述第二保护层上沉积掩模层，所述掩模 层完全地填充所述第一沟槽和所述第二沟槽；
通过干法刻蚀工艺去除NMOS区域上的掩模层，以暴露NMOS区域上的第二保护层；
去除NMOS区域上的第二保护层，以暴露NMOS区域上的第一保护层；
通过干法刻蚀工艺去除PMOS区域上的掩模层，以暴露PMOS区域上的第二保护层；
在去除PMOS区域上的掩模层后，去除NMOS区域上的第一保护层和第一P型功函数调节层；
去除PMOS区域上的第二保护层和第一保护层。
2.根据权利要求1所述的方法，其特征在于，
所述第一保护层包括硅的氧化物；
所述第二保护层包括非晶硅或多晶硅。
3.根据权利要求1或2所述的方法，其特征在于，
采用稀释的HF去除NMOS区域和PMOS区域上的第一保护层。
4.根据权利要求1或2所述的方法，其特征在于，
采用NH4OH或TMAH去除NMOS区域和PMOS区域上第二保护层。
5.根据权利要求1所述的方法，其特征在于，所述第一沟槽中具有第一鳍片，所述第二沟槽中具有第二鳍片；
在所述第一鳍片和所述第二鳍片的上表面和侧面依次形成有所述高K电介质层和所述第一P型功函数调节层。
6.根据权利要求1所述的方法，其特征在于，所述提供衬底结构的步骤包括：
提供初始衬底结构，所述初始衬底结构包括具有第一沟槽的PMOS区域和具有第二沟槽的NMOS区域；
在所述第一沟槽和所述第二沟槽的底面和侧面沉积高K电介质层；
在所述高K电介质层上沉积帽层，所述帽层包括TiN层和在TiN层上的非晶硅层；
去除所述帽层，从而形成所述衬底结构。
7.根据权利要求1所述的方法，其特征在于，还包括：
在PMOS区域上的第一P型功函数调节层和NMOS区域上的高K电介质层上沉积第二P型功函数调节层；
在所述第二P型功函数调节层上沉积N型功函数调节层；
在所述N型功函数调节层之上沉积金属。
8.根据权利要求7所述的方法，其特征在于，所述在所述N型功函数调节层之上沉积金属包括：
在所述N型功函数金属层上沉积粘附层；
在所述粘附层上沉积金属。
9.根据权利要求7所述的方法，其特征在于，还包括：
对沉积的金属进行平坦化。
10.根据权利要求7所述的方法，其特征在于，
所述第一P型功函数调节层包括TiN、TaN或TaC；
所述第二P型功函数调节层包括TiN、TaN或TaC。
11.根据权利要求7所述的方法，其特征在于，所述N型功函数金属层包括TiAl、TiCAl、TiNAl或TiSiAl。
12.根据权利要求1所述的方法，其特征在于，所述第一沟槽和所述第二沟槽的底面与所述高K电介质层之间具有界面层。
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