TW201332083A - 封裝結構與其製法 - Google Patents

封裝結構與其製法 Download PDF

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Publication number
TW201332083A
TW201332083A TW101125106A TW101125106A TW201332083A TW 201332083 A TW201332083 A TW 201332083A TW 101125106 A TW101125106 A TW 101125106A TW 101125106 A TW101125106 A TW 101125106A TW 201332083 A TW201332083 A TW 201332083A
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Taiwan
Prior art keywords
package component
package
polymer
component
underfill
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TW101125106A
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English (en)
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TWI464859B (zh
Inventor
Szu-Wei Lu
ying-da Wang
Li-Chung Kuo
Jing-Cheng Lin
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Taiwan Semiconductor Mfg
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Publication of TW201332083A publication Critical patent/TW201332083A/zh
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Abstract

本發明提供一種封裝結構與其製法。製法包括以下步驟：接合第一封裝元件與第二封裝元件至第三封裝元件之上表面上；分佈第一高分子，其中第一高分子包括：第一部份位於第一封裝元件與第三封裝元件之間的空隙；第二部份位於第二封裝元件與第三封裝元件之間的空隙；第三部份位於第一封裝元件與第二封裝元件之間的空隙；對第一高分子進行一固化步驟；以及於固化步驟之後，切割第一高分子之第三部份，以形成溝槽於第一封裝元件與第二封裝元件之間。

Description

封裝結構與其製法
本發明係有關於一種積體電路結構，且特別是有關於一種封裝結構。
於積體電路的封裝中，複數個晶粒接合到一中介晶圓(interposer wafer)上，其中該中介晶圓包括複數個中介層形成於其中。於晶粒接合之後，將底部填充物分佈(disperse)到晶粒與中介晶圓之間的縫隙(gap)中。之後，進行固化步驟，以固化底部填充物。
已經發現於固化之後，底部填充物可能會收縮(shrink)。如此一來，已固化的底部填充物會施加一外力到晶粒與中介晶圓上，因而造成中介晶圓產生翹曲的現象。此中介晶圓的翹曲，將進一步提高後續製程的困難度。舉例而言，於後續製程中(例如模造(molding)、研磨(grinding)、薄膜(thin film)、或類似之製程)，中介晶圓需要藉由真空吸力被固定到工作盤(chuck table)上。然而，當中介晶圓有翹曲的現象時，其無法被固定到工作盤上。
本發明提供一種封裝結構之製法，包括以下步驟：接合一第一封裝元件與一第二封裝元件至一第三封裝元件之一上表面上；分佈一第一高分子，其中該第一高分子包括：一第一部份位於該第一封裝元件與該第三封裝元件之間的空隙(space)；一第二部份位於該第二封裝元件與該第三封裝元件之間的空隙(space)；一第三部份位於該第一封裝元 件與該第二封裝元件之間的空隙(space)；對該第一高分子進行一固化步驟；以及於該固化步驟之後，切割該第一高分子之第三部份，以形成一溝槽(trench)於該第一封裝元件與該第二封裝元件之間。
本發明另提供一種封裝結構之製法，包括以下步驟：接合一第一晶粒與一第二晶粒至一晶圓的每一晶粒之上表面上；分佈一底部填充物到介於該第一晶粒、該第二晶粒與該晶圓之間的空間，其中該底部填充物包括一部份設置於該第一晶粒與該第二晶粒之間的縫隙(gap)；對該底部填充物進行一固化步驟；於該固化步驟之後，切割部份之該底部填充物，以形成一溝槽(trench)；以及於切割步驟之後，進行一熱處理步驟以退火該底部填充物。
本發明又提供一種封裝結構，包括：一第一封裝元件；一第二封裝元件與一第三封裝元件接合到該第一封裝元件之上表面；一第一高分子區域包括一第一部份，其中該第一部份接觸該第一封裝元件之一第一側壁，且該第一部份位於該第二封裝元件與該第三封裝元件之間的縫隙(gap)中；以及一第二高分子區域設置於該縫隙中，其中該第二高分子接觸該第一高分子之第一部份之側壁，以形成一第一可見界面(visible interface)，且其中該第一可見界面包括一部份大致上垂直於該第一封裝元件之上表面。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本發明之各種實施例提供一種封裝積體電路的方法。示範實施例顯示形成三維積體電路(3DIC)之中間步驟。此處討論各種實施例之變化。於各種示範實施例中，相同的標號代表相同的元件。
依據本發明之一些示範實施例，第1圖至第7C圖為一系列剖面圖，用以顯示積體電路封裝的中間步驟。第1圖顯示封裝元件20之剖面圖。封裝元件20可包括基板22。於一些實施例中，基板22為半導體基板，其可以為結晶矽基板，雖然亦可包括其他半導體材料，例如矽鍺(silicon germanium)、碳化矽(silicon carbon)或類似之材料。於另一實施例中，基板22可以是介電基板。封裝元件20可以是元件晶圓(device wafer)，其包括主動元件，例如電晶體(圖中未顯示)形成於半導體基板22之表面22A。當封裝元件20為元件晶圓，其可包括被動元件(圖中未顯示)，例如電阻及/或電容。於另一實施例中，封裝元件20為中介晶圓(interposer wafer)，其並不具有主動元件於其中。於一些實施例中，封裝元件20可包括被動元件形成於其中。基板通孔(through-substrate vias,TVs)24可從基板22之上表面22A延伸到基板22中。有時當基板通孔(through-substrate vias,TVs)24形成於矽基板時，可亦稱為矽通孔。封裝元件20包括複數個封裝元件40，封裝元件40可能彼此相同。複數個切割線42位於相鄰的封裝元件40之間。封裝元件40可以是元件晶粒(如晶片)、中介晶粒或類似之元件。
內連線結構(interconnect structure)28形成於半導體基板22之上，並且用以電性連接到積體電路元件及/或基板 通孔(through-substrate vias,TVs)24。內連線結構28可包括複數層介電層30。金屬線32形成於介電層30之中。導通孔34形成於上層金屬線32與下層金屬線32之間，並且使其彼此電性相連。金屬線32與導通孔34有時稱為重新分佈層(redistribution layer,RDL)32/34。於一些實施例中，介電層30包括氧化矽、氮化矽、碳化矽、氮氧化矽、或上述之組合、及/或包含上述之多層。另外，介電層30可包括一或多層具有低介電常數(low-k)之介電層，例如此低介電常數材料之介電常數值(k)可低於3.0，或低於2.5。
連接結構38形成於封裝元件20的上表面。於一些實施例中，連接結構38包括金屬柱(metal pillar)，其中焊料蓋(solder cap)可形成或可不形成於金屬柱上表面之上。於另一實施例中，連接結構38包括焊料區域。於又一實施例中，連接結構38可包括凸塊(bump)，凸塊包括銅柱(copper post)、鎳層、焊料蓋層、無電極電鍍鎳化金(electroless Nickel Immersion Gold,ENIG)、無電極電鍍鎳鈀金(Electroless Nickel Electroless Palladium Immersion Gold,ENEPIG)，及/或類似之結構。
請參見第2圖，封裝元件44接合到封裝元件40，例如，藉由覆晶接合(flip-chip bonding)。連接結構38因此可使封裝元件44中的電路電性耦合(electrically couple)到封裝元件20中的重新分佈層(redistribution layer,RDL)32/34與基板通孔(through-substrate vias,TVs)24。封裝元件44可以是元件晶粒，元件晶粒包括邏輯電路，記憶體電路或類似之結構。據此，封裝元件44於此之後可另外稱為晶粒 44。另外地，封裝元件44可包括封裝結構，包括結合到對應的中介層(interposer)之晶粒、封裝基板及/或類似之結構。於每一個晶粒40之上，可有兩個或多個晶粒44結合於其上。
之後，請參見第3圖，高分子52分佈(dispense)到介於晶粒44與封裝元件20之間的空間(縫隙)。高分子52可以是底部填充物(underfill)，因此，於此之後可稱之為底部填充物，雖然其可包括其他高分子，例如環氧樹脂(epoxy)。底部填充物52可以是模造底部填充物(molding underfill)。底部填充物52也可填充到介於相鄰的晶粒44之間的縫隙(於第2圖中的符號45)中，其中該相鄰的晶粒44接合到相同的封裝元件40。底部填充物52可以不填充到縫隙47中，其中縫隙47為接合到不同封裝元件40之相鄰兩晶粒44間的縫隙。另外，底部填充物亦可填充到縫隙47中。
底部填充物52接著進行固化步驟。於固化步驟之後，底部填充物52可以部份固化或完全固化。於部份固化或完全固化之後，底部填充物52變得較固化之前更為堅固。部份固化不會使底部填充物完全固化。於底部填充物52部份固化的期間，底部填充物52可能會收縮，而部份固化並不會造成底部填充物完全收縮。如此一來，經過部份固化之後，底部填充物52仍然為膠狀(gel)。於一些實施例中，使用熱固化製程進行固化步驟。於一些實施例中，相對完全固化底部填充物52所需的溫度與加熱時間，採取較低的溫度或較短的加熱時間。於一些示範的實施例中，進行部份固化的溫度為約80℃-120℃。示範的實施例的部份固化時 間可介於1小時至3小時之間。能理解的是，部份固化所需的條件將視所使用的底部填充物52種類而定。再者，亦可使用其他固化方法，例如紫外光(Ultra-Violet)固化，可依據底部填充物52的種類而定。當固化製程為完全固化製程，底部填充物52會完全被固化。
請參見第4A-4C圖，對底部填充物52進行切割步驟，以形成溝槽(trench)54。可使用雷射或刀片(blade)(圖中未顯示)切割步驟。於一些實施例中，溝槽54形成於接合到相同封裝元件40的相鄰晶粒44之間。於另一實施例中，底部填充物52亦可填充到縫隙(gap)中(第3圖中的標號47)，其中縫隙47為接合到不同封裝元件40之相鄰兩晶粒44間的縫隙。溝槽54亦可形成於縫隙47的位置，藉以切斷接合到不同晶粒40的兩相鄰晶粒44。於一些實施例中，溝槽54的側壁54B大致上垂直於封裝元件20的頂表面20A，側壁54B的部份在後文中稱為垂直側壁。於一些實施例中，垂直側壁部份包括側壁54B之上部份。
於一些示範實施例中，溝槽54之深度D可以為晶粒44上表面到封裝元件20頂表面20A之總高度的5%-100%。溝槽54之寬度W可介於約5-500 μm。直接位於溝槽54下方的底部填充物52部份之厚度T1為約0-700 μm。如第4A圖所示，溝槽54之底部54A可大致上與晶粒44之底表面44A等高。另外，如第4B圖所示，底部54A可高於底表面44A。如第4C圖所示，溝槽54之底部54A可低於底表面44A，且可位在高於封裝元件20之上表面20A的任何高度。
請再次參見第4A圖，於一些實施例中，溝槽54之寬度W可小於相鄰晶粒44之間的間距(spacing)S。於切割步驟之後，部份的底部填充物52殘留在一或兩晶粒44之側壁上，且可形成於溝槽54之一側或相對側。舉例而言，底部填充物52殘留的部份之厚度T2可為約0-500 μm。第4B圖顯示另一實施例之封裝結構，其中溝槽54之寬度W可大於相鄰晶粒44之間的間距(spacing)S。據此，部份的晶粒44被切割。第4C圖顯示另一實施例，其中溝槽54之寬度W大致上等於間距S。
於一實施例中，其中底部填充物52被部份固化，於切割步驟之後，進行熱處理步驟(在後文中稱為熱處理步驟)，以退火與固化底部填充物52。進行熱處理步驟之溫度高於玻璃轉化溫度(glass transition temperature)。於一些示範實施例中，熱處理的溫度介於140℃-170℃之間。舉例而言，示範之熱處理時間可為約1小時-3小時，且可為約1.5小時-2.5小時。固化可能會造成底部填充物52收縮。需注意的是，如果底部填充物52未被切割，設置於相鄰晶粒44之間的部份底部填充物52會將晶粒44拉向彼此，因而造成封裝元件20的翹曲現象。於一實施例中，由於切割步驟的實施，底部填充物52不再造成晶粒44拉向彼此，至少可減少，甚至大致上消除因為底部填充物52固化而引起的封裝元件20之翹曲現象。
第4D圖顯示第4A-4C圖之俯視圖，其中第4A-4C圖來自於第4D圖中剖線4-4之平面。如第4D圖所示，溝槽54可從底部填充物52之一邊延伸到另一邊，因此，降低 底部填充物52之拉力的效益可達到最大化。
接著，請參見第5A-5C圖，模造(mold)高分子56到晶粒44與封裝元件20之上，例如使用壓縮成型(compress molding)。第5A、5B與5C圖分別來自於第4A、4B與4C圖。於一些實施例中，高分子56包括模造化合物，例如環氧樹脂、矽膠(silicon)或類似之材料。高分子56可包括第一部份、第二部份與第三部份，其中第一部份填充到溝槽54中，第二部份填充到接合到不同封裝元件40上的相鄰晶粒44之間的縫隙，以及第三部份覆蓋晶粒44。之後，固化高分子56。於一些實施例中，於固化高分子56之後，進行一平坦化步驟，例如研磨(griding)，以使高分子56之上表面等高，以致於第三部份被移除且暴露晶粒44之上表面。
第6A-6C圖顯示形成封裝元件20之背側結構。第6A、6B與6C圖分別來自於第5A、5B與5C圖。於形成背側結構時，第5A、5B與5C圖中的封裝結構先被翻轉向下，且半導體基板22面向上。對半導體基板22的背側進行研磨，以薄化半導體基板22，直到暴露基板通孔(through-substrate vias,TVs)24。形成介電層60於半導體基板22之背側。連接結構58可形成於封裝元件20之背側且電性耦合到基板通孔(through-substrate vias,TVs)24。於一些實施例中，連接結構58為焊料球(solder ball)。於另一實施例中，連接結構58可包括金屬墊(metal pad)、金屬凸塊、焊料蓋或類似之結構。重新分佈層(redistribution layer,RDL)可視需要地形成於封裝元件20之背側與形成於介電層60之中，其中 結構特徵59代表重新分佈層(redistribution layer,RDL)。連接結構58用於接合到另一電子元件(圖中未顯示)，其中該電子元件可以為半導體基板、封裝基板、印刷電路板(PCB)或類似之結構。
第6A-6C圖顯示為形成封裝結構64而進行的晶粒切割步驟(die-saw step)，其中線66代表裁切線(kerf lines)。第7A、7B與7C圖之封裝結構64分別來自於第6A、6B與6C圖。於第7A圖中的封裝結構64，底部填充物52包括介於相鄰晶粒44之間的頂表面52A。底部填充物52之側壁52B與頂表面52A以及位於高分子56底下的底部填充物52之部份上表面共同形成一階梯狀之結構。頂表面52A與側壁52B形成陡峭的轉變，而非(instead of)平滑的(smooth)轉變。再者，介於高分子56與底部填充物52之間的界面52B大致上垂直。界面52B的部份(例如上部份)可大致上垂直於晶粒40之頂表面20A。因為高分子56與底部填充物52由不同步驟而形成，且因為高分子56與底部填充物52可包括不同的高分子，所以界面52B是可見的(visible)。於第7B圖中，藉由切開晶粒44，高分子56延伸到晶粒44的部份中。於第7C圖中，高分子56的部份56’可具有寬度W大致上等於相鄰晶粒44之間的間距(spacing)S。
依據本發明之實施例，藉由對底部填充物進行部份固化或完全固化步驟，切割底部填充物，以及對底部填充物進行熱退火(thermal annealing)，可明顯減少位於底部填充物下方之晶圓的翹曲現象。實驗由第一樣品晶圓與第二樣 品晶圓分別形成第一樣品封裝結構與第二樣品封裝結構。除了當形成第一樣品封裝結構時，對於各自的底部填充物並不進行部份固化步驟與切割步驟之外，形成第一樣品封裝結構與第二樣品封裝結構之製法彼此類似。如此一來，第一樣品晶圓的翹曲現象為約800 μm。相較之下，於形成第二樣品封裝結構時，對各自的底部填充物進行部份固化與切割步驟。第二封裝晶圓的翹曲現象降低至為約350 μm。此項結果顯示底部填充物的部份固化步驟與切割步驟會明顯降低晶圓翹曲現象。
於一實施例中，本發明提供一種封裝結構之製法，包括以下步驟：接合一第一封裝元件與一第二封裝元件至一第三封裝元件之一上表面上；分佈一第一高分子，其中該第一高分子包括：一第一部份位於該第一封裝元件與該第三封裝元件之間的空隙(space)；一第二部份位於該第二封裝元件與該第三封裝元件之間的空隙(space)；一第三部份位於該第一封裝元件與該第二封裝元件之間的空隙(space)；對該第一高分子進行一固化步驟；以及於該固化步驟之後，切割該第一高分子之第三部份，以形成一溝槽(trench)於該第一封裝元件與該第二封裝元件之間。
於另一實施例中，本發明提供一種封裝結構之製法，包括以下步驟：接合一第一晶粒與一第二晶粒至一晶圓的每一晶粒之上表面上；分佈一底部填充物到介於該第一晶粒、該第二晶粒與該晶圓之間的空間，其中該底部填充物包括一部份設置於該第一晶粒與該第二晶粒之間的縫隙(gap)；對該底部填充物進行一固化步驟；於該固化步驟之 後，切割部份之該底部填充物，以形成一溝槽(trench)；以及於切割步驟之後，進行一熱處理步驟以退火該底部填充物。
於又一實施例中，本發明提供一種封裝結構，包括：一第一封裝元件；一第二封裝元件與一第三封裝元件接合到該第一封裝元件之上表面；一第一高分子區域包括一第一部份，其中該第一部份接觸該第一封裝元件之一第一側壁，且該第一部份位於該第二封裝元件與該第三封裝元件之間的縫隙(gap)中；以及一第二高分子區域設置於該縫隙中，其中該第二高分子接觸該第一高分子之第一部份之側壁，以形成一第一可見界面(visible interface)，且其中該第一可見界面包括一部份大致上垂直於該第一封裝元件之上表面。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧封裝元件
20A‧‧‧封裝元件之頂表面
22‧‧‧半導體基板
22A‧‧‧基板之頂表面
24‧‧‧基板通孔(through-substrate vias,TVs)
28‧‧‧內連線結構(interconnect)
30‧‧‧介電層；
32‧‧‧金屬線
34‧‧‧導通孔(vias)
38‧‧‧連接結構(connector)
40‧‧‧封裝元件
42‧‧‧切割線(scribe line)
44‧‧‧晶粒(dies)
44A‧‧‧晶粒之底表面
45‧‧‧縫隙(gap)
47‧‧‧縫隙(gap)
52‧‧‧底部填充物
52A‧‧‧底部填充物之頂表面
52B‧‧‧底部填充物之側壁
54‧‧‧溝槽
54A‧‧‧溝槽之底部
54B‧‧‧溝槽之側壁
56‧‧‧高分子
56’‧‧‧高分子的部份
58‧‧‧連接結構
59‧‧‧重新分佈層(redistribution layer,RDL)
60‧‧‧介電層
64‧‧‧封裝結構
66‧‧‧裁切線(kerf lines)
第1-3圖、第4A-4D圖、第5A-5C圖、第6A-6C圖及第7A-7C圖為一系列剖面圖，用以說明本發明一較佳實施例的封裝積體電路之中間步驟。
20A‧‧‧封裝元件之頂表面
40‧‧‧封裝元件
44‧‧‧晶粒(dies)
52‧‧‧底部填充物
52A‧‧‧底部填充物之頂表面
52B‧‧‧底部填充物之側壁
56‧‧‧高分子
58‧‧‧連接結構
64‧‧‧封裝結構

Claims (10)

  1. 一種封裝結構之製法，包括以下步驟：接合一第一封裝元件與一第二封裝元件至一第三封裝元件之一上表面上；分佈一第一高分子，其中該第一高分子包括：一第一部份位於該第一封裝元件與該第三封裝元件之間的空隙(space)；一第二部份位於該第二封裝元件與該第三封裝元件之間的空隙(space)；一第三部份位於該第一封裝元件與該第二封裝元件之間的空隙(space)；對該第一高分子進行一固化步驟；以及於該固化步驟之後，切割該第一高分子之第三部份，以形成一溝槽(trench)於該第一封裝元件與該第二封裝元件之間。
  2. 如申請專利範圍第1項所述之封裝結構之製法，其中該固化步驟為部份固化，且其中於切割該第一高分子之第三部份之後，該製法尚包括進行一熱處理步驟，以完全固化該第一高分子。
  3. 如申請專利範圍第1項所述之封裝結構之製法，其中於該固化步驟之後，該第一高分子完全被固化。
  4. 如申請專利範圍第1項所述之封裝結構之製法，尚包括：於該切割之後，用一第二高分子模造(molding)該第一封裝元件、第二封裝元件與第三封裝元件，其中該第二高分子填入該溝槽中。
  5. 如申請專利範圍第1項所述之封裝結構之製法，其中該溝槽具有一底部大致上與該第一封裝元件與該第二封裝元件之底表面等高，或或低於該第一封裝元件與該第二封裝元件之底表面，且其中該溝槽之該底部高於該第三封裝元件之頂表面。
  6. 如申請專利範圍第1項所述之封裝結構之製法，其中於該第一高分子之第三部份被切割之後，該第一高分子之第三部份包括一剩餘部份位於該溝槽之相對側，且其中該剩餘部份接觸該第一封裝元件與該第二封裝元件之側壁。
  7. 一種封裝結構，包括：一第一封裝元件；一第二封裝元件與一第三封裝元件接合到該第一封裝元件之上表面；一第一高分子區域包括一第一部份，其中該第一部份接觸該第一封裝元件之一第一側壁，且該第一部份位於該第二封裝元件與該第三封裝元件之間的縫隙(gap)中；以及一第二高分子區域設置於該縫隙中，其中該第二高分子接觸該第一高分子之第一部份之側壁，以形成一第一可見界面(visible interface)，且其中該第一可見界面包括一部份大致上垂直於該第一封裝元件之上表面。
  8. 如申請專利範圍第7項所述之封裝結構，其中該第一高分子區域尚包括一第二部份位於該縫隙中，其中該第二高分子區域設置於該第一高分子區域之該第一部份與該第二部份之間，且其中該第二高分子區域接觸該第一高分 子區域之第二部份，以形成一第二可見界面，以及其中該第二可見界面包括一部份大致上垂直於該第一封裝元件之上表面。
  9. 如申請專利範圍第7項所述之封裝結構，其中該第二高分子區域之一底部大致上與該第二封裝元件之底表面與該第三封裝元件之底表面等高。
  10. 如申請專利範圍第7項所述之封裝結構，其中該第二高分子區域之一底部大致上低於該第二封裝元件之底表面與該第三封裝元件之底表面，且高於該第一封裝元件之頂表面。
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CN103219293B (zh) 2015-06-24
KR20130086109A (ko) 2013-07-31
US20130187258A1 (en) 2013-07-25
TWI464859B (zh) 2014-12-11
US20170213809A1 (en) 2017-07-27
US10840215B2 (en) 2020-11-17
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US20210125964A1 (en) 2021-04-29
US20210057383A1 (en) 2021-02-25

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