TW201709434A - 電子封裝結構及其製法 - Google Patents
電子封裝結構及其製法 Download PDFInfo
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Abstract
一種電子封裝結構之製法,係包括:提供一具有複數導電穿孔之中介板,且該中介板中形成有位於該些導電穿孔周圍之開孔,接著,設置電子元件於該中介板上,再結合蓋板於該電子元件上,並形成用以包覆該電子元件之封裝層,而該封裝層復形成於該開孔中,以令該開孔中之封裝層接觸空氣,故於進行後續的高溫製程時,該封裝層中之溶劑於揮發後,可經由該些開孔排出該封裝層外,而不會於該封裝層中形成氣泡,以避免發生氣爆。本發明復提供該電子封裝結構。
Description
本發明係有關一種封裝製程,尤指一種提升製程可靠度之電子封裝結構及其製法。
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術,例如晶片尺寸構裝(Chip Scale Package,簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached,簡稱DCA)或多晶片模組封裝(Multi-Chip Module,簡稱MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1A至1B圖係為習知半導體封裝件1的製法之示意圖。
如第1A圖所示,提供一蓋板12及一具有複數導電矽穿孔(Through-silicon via,簡稱TSV)與線路重佈層(Redistribution layer,簡稱RDL)之矽中介板(Through Silicon interposer,簡稱TSI)10,且藉由CoW(Chip on Wafer)製程,將複數半導體晶片11藉由複數導電凸塊110設於該
矽中介板10上。
如第1B圖所示,將該蓋板12與該矽中介板10相壓合,再進行模封(molding)製程,即形成用以包覆該些半導體晶片11之封裝層13於該蓋板12與該矽中介板10之間。詳細地,由於該些半導體晶片11之厚度太薄,故於形成該封裝層13之前,會在該些半導體晶片11上方設置該蓋板12,以供固定支撐使用。
目前的模封技術,可有效減少封裝層13之膠材於流動時所產生的氣室(void)問題。
再者,當完成模封製程之後,常會進行其它溫度高於200℃的高溫製程,例如,於該矽中介板10下方植球,再回銲結合其它電子裝置。
惟,該封裝層13之材料除了包含環氧樹脂,還包含各式溶劑(solvent)(如硬化劑、填充劑、催化劑及脫模劑),且於溫度200℃以上的環境下,上述各種溶劑會逐漸裂解成氣體,此時,因該蓋板12與該矽中介板10遮擋該封裝層13之上、下兩側,而無法排除該氣體,故該氣體將存在於該封裝層13中而形成氣泡a,以致於當進行另一高溫製程時,如採用表面黏著技術(SMT)之產品終端製程,該氣泡a會受熱膨脹而發生氣爆,導致產品不良。
因此,如何克服上述習知技術的種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種電
子封裝結構,係包括:一具有複數導電穿孔之中介板,復具有相對之第一表面與第二表面及鄰接該第一與第二表面之側面,且該些導電穿孔連通該第一與第二表面,而該側面係具有缺口;電子元件,係設於該中介板之第一表面上;以及封裝層,係形成於該中介板之第一表面上並包覆該電子元件,且該封裝層覆蓋該缺口。
前述之電子封裝結構中,該缺口係位於該中介板之第一表面與側面之交界處。
前述之電子封裝結構中,形成該封裝層之材質係為封裝膠體或介電材。
本發明復提供一種電子封裝結構之製法,係包括:提供一具有複數導電穿孔之中介板,且該中介板中形成有位於該些導電穿孔周圍之至少一開孔;設置電子元件於該中介板上;以及結合蓋板於該電子元件上,並形成封裝層於該蓋板與該中介板之間,以令該封裝層包覆該電子元件,且該封裝層復形成於該開孔中。
前述之製法中,形成該開孔之方法係包括機械成孔、雷射或蝕刻。
前述之製法中,於形成該封裝層後,沿該開孔進行切單製程。
前述之製法中,形成該封裝層之方法係為模封或壓合。
前述之電子封裝結構及其製法中,該中介板具有電性連接該電子元件或該些導電穿孔之線路重佈層。
前述之電子封裝結構及其製法中,於形成該封裝層後,移除該蓋板,使該電子元件外露於該封裝層之表面。
前述之電子封裝結構及其製法中,於形成該封裝層後,形成複數導電元件於該中介板上,並使該些導電元件電性連接該中介板
另外,前述之電子封裝結構及其製法中,於形成該封裝層後,結合一封裝基板於該中介板上,並使該封裝基板電性連接該中介板。
由上可知,本發明之電子封裝結構及其製法,主要藉由先於該中介板上形成開孔,使位於該開孔中之封裝層外露於該中介板而接觸空氣,故相較於習知技術,當本發明之電子封裝結構進行後續的高溫製程時,該封裝層中之溶劑於揮發後,將經由該些開孔(或缺口)排出該封裝層外,而不會存留於該中介板與該蓋板之間,以避免於該封裝層中形成氣泡,進而能避免發生氣爆。
1‧‧‧半導體封裝件
10‧‧‧矽中介板
11‧‧‧半導體晶片
110,211‧‧‧導電凸塊
12,22‧‧‧蓋板
13,23‧‧‧封裝層
2,2’,2”,3‧‧‧電子封裝結構
20‧‧‧中介板
20a‧‧‧第一表面
20b,20b’‧‧‧第二表面
20c‧‧‧側面
200‧‧‧導電穿孔
201,201’‧‧‧線路重佈層
202‧‧‧開孔
202’‧‧‧缺口
21‧‧‧電子元件
21a‧‧‧作用面
21b‧‧‧非作用面
210‧‧‧電極墊
23a‧‧‧上表面
24‧‧‧導電元件
25‧‧‧封裝基板
a‧‧‧氣泡
S‧‧‧切割路徑
第1A至1B圖係為習知半導體封裝件之製法之立體與剖面示意圖;以及第2A至2F圖係為本發明之電子封裝結構之製法之剖面示意圖;其中,第2B’圖係為第2B圖之上視圖,第2E’及2E”圖係為第2E圖之其它實施例。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地
瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之電子封裝結構2,2’,2”,3之製法之剖面示意圖。
如第2A圖所示,提供一具有複數導電穿孔200之中介板20,且該中介板20具有相對之第一表面20a與第二表面20b,以令該些導電穿孔200連通該第一表面20a,又該中介板20之第一表面20a上形成有位於該些導電穿孔200周圍之複數開孔202。
於本實施例中,該中介板20之第一表面20a上具有電性連接該些導電穿孔200之線路重佈層201。
再者,形成該開孔202之方法係包括機械成孔(如鑽、鋸、銑等方式)、雷射或蝕刻。
如第2B及2B’圖所示,設置複數電子元件21於該中
介板20之第一表面20a上。
於本實施例中,該電子元件21係為主動元件、被動元件或其二者組合等,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。
再者,該電子元件21以覆晶方式設於該線路重佈層201上。具體地,該電子元件21具有相對之作用面21a與非作用面21b,且該作用面21a具有複數電極墊210,該電極墊210係以複數導電凸塊211結合於該線路重佈層201上。
又,該電子元件21並未遮蓋該些開孔202,如第2B’圖所示。
如第2C圖所示,結合一蓋板22於該電子元件21之非作用面21b上,且形成一封裝層23於該蓋板22與該中介板20之第一表面20a之間,以令該封裝層23包覆該電子元件21與該些導電凸塊211,且該封裝層23復形成於該些開孔202中。
於本實施例中,形成該封裝層23之方法係為模封(molding)或壓合,故形成該封裝層23之材質係為封裝膠體或介電材。具體地,當採用模封製程時,先將該蓋板22結合於該電子元件21上,再形成如環氧樹脂(epoxy)之封裝膠體於該蓋板22與該中介板20之第一表面20a之間。
再者,當採用壓合製程時,先將如ABF(Ajinomoto Build-Up Film)或預浸材之介電材點膠式地附著於該電子
元件21上,再以該蓋板22壓合該介電材;或者,先將介電材塗佈於該蓋板22上,再以該介電材朝向該電子元件21而壓合該蓋板22與該中介板20。
再者,該電子元件21之非作用面21b係齊平該封裝層23之上表面23a。
如第2D圖所示,移除該中介板20之第二表面20b之部分材質,使該些導電穿孔200與該些開孔202係連通該中介板20之第二表面20b’。
於本實施例中,利用整平製程(如研磨),使該些導電穿孔200之端面與該些開孔202之端面齊平該中介板20之第二表面20b’,以令位於該開孔202中之封裝層23外露於該中介板20之第二表面20b’。
如第2E圖所示,沿該些開孔202(如第2D圖所示之切割路徑S)進行切單製程,以令該些開孔202形成位於該中介板20之側面20c的缺口202’,且於該中介板20之第二表面20b’上形成複數導電元件24。
於本實施例中,將移除該蓋板22,使該電子元件21之非作用面21b外露於該封裝層23之上表面23a,但於其它實施例中,如第2E’圖所示,亦可保留該蓋板22。
再者,該些導電元件24係電性連接該些導電穿孔200,且該些導電元件24係為銲料球、金屬凸塊或其它適合的導電構造,並無特別限制。
又,該缺口202’係連通該中介板20之第一表面20a與第二表面20b’。
另外,該封裝層23亦可形成於該中介板20之側面20c上。
於另一實施例中,如第2E”圖所示,可於該中介板20之第二表面20b’上形成有電性連接該些導電穿孔200之另一線路重佈層201’,以令該些導電元件24形成於該另一線路重佈層201’。
如第2F圖所示,該中介板20藉由該些導電元件24結合於一封裝基板25上。
於本實施例中,該封裝基板25具有用以電性連接該些導電元件24之複數線路層(圖略)。
本發明之製法,係藉由先於該中介板20上形成至少一開孔202,待移除該中介板20之第二表面20b之部分材質後,使該些開孔202連通該中介板20之第二表面20b’,則位於該開孔202中之封裝層23便會外露於該中介板20之第二表面20b’而接觸空氣,故相較於習知技術,當本發明之電子封裝結構2,2’,2”,3進行後續的高溫製程時,該封裝層23中之溶劑於揮發後,便可經由該些開孔202(或缺口202’)排出該封裝層23外,而不會存留於該中介板20與該蓋板22之間,進而不會形成氣泡。
因此,本發明之製法具有排放高分子材料裂解氣體的功效,藉以避免因形成氣泡而發生氣爆之問題,故能提升終端產品之可靠度。
本發明復提供一種電子封裝結構2,2’,2”,3,係包括:一具有複數導電穿孔200之中介板20、一設於該中介板20
上之電子元件21以及一包覆該電子元件21之封裝層23。
所述之中介板20具有相對之第一表面20a與第二表面20b’及鄰接該第一與第二表面20a,20b’之複數側面20c,且該些導電穿孔200連通該第一與第二表面20a,20b,而各該側面20c係具有一缺口202’。
所述之電子元件21係設於該中介板20之第一表面20a上。
所述之封裝層23係形成於該中介板20之第一表面20a上並包覆該電子元件21,且該封裝層23覆蓋該缺口202’。
於一實施例中,該中介板20具有一電性連接該電子元件21之線路重佈層201。
於一實施例中,該中介板20具有至少一電性連接該些導電穿孔202之線路重佈層201,201’。
於一實施例中,該缺口202’係位於該中介板20之第一表面20a與側面20c之交界處。
於一實施例中,形成該封裝層23之材質係為封裝膠體或介電材。
於一實施例中,該電子元件21之非作用面21b係外露於該封裝層23之上表面23a。
於一實施例中,所述之電子封裝結構2’復包括一蓋板22,係結合於該電子元件21上,使該封裝層23位於該中介板20之第一表面20a與該蓋板22之間。
於一實施例中,所述之電子封裝結構2,2’,2”,3復包括複數導電元件24,係形成於該中介板20之第二表面20b
上並電性連接該中介板20。
於一實施例中,所述之電子封裝結構3復包括一封裝基板25,係結合於該中介板20之第二表面20b上並電性連接該中介板20。
綜上所述,本發明之電子封裝結構及其製法,主要藉由該中介板形成有開孔(或缺口),使位於該開孔中(或缺口上)之封裝層外露於該中介板而接觸空氣,故當該電子封裝結構進行後續的高溫製程時,該封裝層中之溶劑於揮發後,便可經由該些開孔(或缺口)排出該封裝層外,而不會存留於該中介板與該蓋板之間,進而不會形成氣泡。因此,本發明之電子封裝結構及其製法具有排放高分子材料裂解氣體的功效,因而能避免發生氣爆,故能提升終端產品之可靠度。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2‧‧‧電子封裝結構
20‧‧‧中介板
20a‧‧‧第一表面
20b’‧‧‧第二表面
20c‧‧‧側面
200‧‧‧導電穿孔
201‧‧‧線路重佈層
202’‧‧‧缺口
21‧‧‧電子元件
21b‧‧‧非作用面
23‧‧‧封裝層
23a‧‧‧上表面
24‧‧‧導電元件
Claims (19)
- 一種電子封裝結構,係包括:一具有複數導電穿孔之中介板,該中介板復具有相對之第一表面與第二表面及鄰接該第一與第二表面之側面,其中,該些導電穿孔連通該第一與第二表面,且該側面係形成有缺口;電子元件,係設於該中介板之第一表面上;以及封裝層,係形成於該中介板之第一表面上並包覆該電子元件,且該封裝層覆蓋該缺口。
- 如申請專利範圍第1項所述之電子封裝結構,其中,該中介板具有電性連接該電子元件之線路重佈層。
- 如申請專利範圍第1項所述之電子封裝結構,其中,該中介板具有電性連接該些導電穿孔之線路重佈層。
- 如申請專利範圍第1項所述之電子封裝結構,其中,該缺口係位於該中介板之第一表面與側面之交界處。
- 如申請專利範圍第1項所述之電子封裝結構,其中,形成該封裝層之材質係為封裝膠體或介電材。
- 如申請專利範圍第1項所述之電子封裝結構,其中,該電子元件係外露於該封裝層之表面。
- 如申請專利範圍第1項所述之電子封裝結構,復包括蓋板,係結合於該電子元件上,使該封裝層位於該中介板之第一表面與該蓋板之間。
- 如申請專利範圍第1項所述之電子封裝結構,復包括複數導電元件,係形成於該中介板之第二表面上並電 性連接該中介板。
- 如申請專利範圍第1項所述之電子封裝結構,復包括封裝基板,係結合於該中介板之第二表面上並電性連接該中介板。
- 一種電子封裝結構之製法,係包括:提供一具有複數導電穿孔之中介板,且該中介板中形成有位於該些導電穿孔周圍之至少一開孔;設置電子元件於該中介板上;以及結合蓋板於該電子元件上,並形成封裝層於該蓋板與該中介板之間,以令該封裝層包覆該電子元件,且該封裝層復形成於該開孔中。
- 如申請專利範圍第10項所述之電子封裝結構之製法,其中,該中介板具有電性連接該電子元件之線路重佈層。
- 如申請專利範圍第10項所述之電子封裝結構之製法,其中,該中介板具有電性連接該些導電穿孔之線路重佈層。
- 如申請專利範圍第10項所述之電子封裝結構之製法,其中,形成該開孔之方法係包括機械成孔、雷射或蝕刻。
- 如申請專利範圍第10項所述之電子封裝結構之製法,其中,形成該封裝層之方法係為模封或壓合。
- 如申請專利範圍第10項所述之電子封裝結構之製法,復包括於形成該封裝層後,移除該蓋板。
- 如申請專利範圍第15項所述之電子封裝結構之製法,其中,該電子元件係外露於該封裝層之表面。
- 如申請專利範圍第10項所述之電子封裝結構之製法,復包括於形成該封裝層後,沿該開孔進行切單製程。
- 如申請專利範圍第10項所述之電子封裝結構之製法,復包括於形成該封裝層後,形成複數導電元件於該中介板上,並使該些導電元件電性連接該中介板。
- 如申請專利範圍第10項所述之電子封裝結構之製法,復包括於形成該封裝層後,結合一封裝基板於該中介板上,並使該封裝基板電性連接該中介板。
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US10548228B2 (en) * | 2016-03-03 | 2020-01-28 | International Business Machines Corporation | Thermal interface adhesion for transfer molded electronic components |
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TWI620287B (zh) * | 2017-03-21 | 2018-04-01 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
CN107993937B (zh) * | 2017-12-01 | 2020-03-31 | 华进半导体封装先导技术研发中心有限公司 | 一种临时键合工艺的辅助结构及利用该结构的晶圆加工方法 |
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US8647963B2 (en) * | 2009-07-08 | 2014-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of wafer level chip molded packaging |
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US8643148B2 (en) * | 2011-11-30 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip-on-Wafer structures and methods for forming the same |
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