TW201324613A - 用於蝕刻低k及其它介電質膜的製程腔室 - Google Patents
用於蝕刻低k及其它介電質膜的製程腔室 Download PDFInfo
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- TW201324613A TW201324613A TW101139110A TW101139110A TW201324613A TW 201324613 A TW201324613 A TW 201324613A TW 101139110 A TW101139110 A TW 101139110A TW 101139110 A TW101139110 A TW 101139110A TW 201324613 A TW201324613 A TW 201324613A
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- plasma
- chamber
- shower head
- chuck
- coupled
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Classifications
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
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- C23C16/0245—Pretreatment of the material to be coated by cleaning or etching by etching with a plasma
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/31105—Etching inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Abstract
本發明描述用於蝕刻低k及其它介電質膜的方法及製程腔室。舉例而言,方法包括以電漿製程修改低k介電層之部分。在遮罩層及低k介電層之未經修改的部分上有選擇地蝕刻低k介電層之經修改的部分。描述具有用於交替地產生不同電漿之多個腔室區域的蝕刻腔室。在實施例中,在一個操作模式中提供第一電荷耦合的電漿源以產生至工作件的離子流,而在另一操作模式中提供第二電漿源以提供反應性物種流而無至工作件的顯著離子流。控制器操作以隨時間重複循環操作模式以移除介電材料之期望的累積量。
Description
本申請案主張於2011年10月27日提出申請之標題為「Process Chamber for Etching Low K and Other Dielectric Films」的美國臨時申請案第61/552,183號的權益,該申請案之內容在此為所有目的以引用之方式整體併入本文。
本發明之實施例係關於微電子元件處理領域,且特定而言係關於低k介電質膜之電漿蝕刻。
在半導體製造業中,低k介電質係相對於二氧化矽具有小介電常數的材料。低k介電材料實施係用於允許微電子元件之持續擴大尺寸的若干策略中之一者。在數位電路中,絕緣介電質使導電部分(例如,互連電線及電晶體)彼此分隔。隨著組件的尺寸擴大且電晶體更加靠近在一起,絕緣介電質已薄化至電荷積聚及串擾不利地影響元件效能的程度。用相同厚度的低k介電質替換二氧化矽降低寄生電容,賦能更快的切換速度及更低的熱耗散。
然而,因為已經發現此等膜之處理(特別是此等膜之
蝕刻)會損壞材料及/或致使材料不穩定或不適於元件製造,所以在低k介電質處理技術之發展中需要顯著改良。
一種電漿蝕刻腔室,包含:夾盤,該夾盤在蝕刻製程期間支撐工作件;第一噴淋頭,該第一噴淋頭設置在夾盤上方以分配第一饋送氣體進入第一腔室區域,其中夾盤及第一噴淋頭形成第一射頻耦合電極對,以電容激發第一噴淋頭與夾盤之間的第一腔室區域內之第一饋送氣體的第一電漿;第二電極,該第二電極設置在第一噴淋頭上方,與夾盤相對,其中第二電極及第一噴淋頭形成第二射頻耦合電極對以使第一噴淋頭與第二電極之間的第二腔室區域內之第二饋送氣體的第二電漿電容放電;及控制器,該控制器在蝕刻製程期間藉由交替地自動供電第一射頻耦合電極對及第二射頻耦合電極對來交替地激發第一電漿及第二電漿。
一種電漿蝕刻腔室,包含:夾盤,該夾盤在蝕刻製程期間支撐工作件;第一噴淋頭,該第一噴淋頭設置在夾盤上方以分配第一饋送氣體進入第一腔室區域,其中夾盤及第一噴淋頭形成第一射頻耦合電極對以使第一噴淋頭與夾盤之間的第一腔室區域內的第一饋送氣體之第一電漿電容放電並提供射頻偏壓電位於夾盤上;遠端射頻電漿源,該遠端射頻電漿源設置在第一噴淋頭上方,與
夾盤相對,其中遠端射頻電漿源將使遠端電漿源內的第二饋送氣體之第二電漿放電而不提供射頻偏壓電位於夾盤上;及控制器,該控制器在蝕刻製程期間藉由交替地自動供電第一射頻耦合電極對及遠端射頻電漿源來交替地激發第一電漿及第二電漿。
一種電漿蝕刻腔室,包含:夾盤,該夾盤在蝕刻製程期間支撐工作件;第一噴淋頭,該第一噴淋頭設置在夾盤上方以分配第一饋送氣體進入第一腔室區域,其中夾盤及第一噴淋頭形成第一射頻耦合電極對以使第一噴淋頭與夾盤之間的第一腔室區域內的第一饋送氣體之射頻電漿電容放電並提供射頻偏壓電位於夾盤上;高壓直流(DC)電源,該高壓直流電源耦接至設置在第一噴淋頭上方的電極對以產生直流電漿放電,該電極對藉由介電隔片與第一噴淋頭電絕緣,其中第一噴淋頭負偏壓至一陽極電位,該陽極電位相對直流電源耦合電極之陰極;及控制器,該控制器在蝕刻製程期間藉由交替地自動供電第一射頻耦合電極對及直流電源耦合電極對來交替地激發射頻電漿及直流電漿。
一種電漿蝕刻腔室,包含:夾盤,該夾盤在蝕刻製程期間支撐工作件;第一噴淋頭,該第一噴淋頭設置在夾盤上方以分配第一饋送氣體進入第一腔室區域,其中夾盤及第一噴淋頭形成第一射頻耦合電極對以使第一噴淋頭與夾盤之間的第一腔室區域內的第一饋送氣體之射頻電漿電容放電並提供射頻偏壓電位於夾盤上;導電線
圈,該導電線圈設置在蝕刻腔室之介電腔室蓋上方並耦接至射頻源以在設置於介電腔室蓋與第一噴淋頭之間的第二腔室區域中產生感應耦合的電漿放電;及控制器,該控制器在蝕刻製程期間藉由交替地自動供電第一射頻耦合電極對及導電線圈來交替地激發電容耦合的電漿及感應耦合的電漿。
一般而言,本文描述之電漿蝕刻方法的實施例使用破壞機制蝕刻低k(及其它介電質)材料並留下狀況良好的剩餘蝕刻膜。本文描述之電漿蝕刻方法的實施例循環真空(亦即,不破壞真空)執行至少二次單獨的基於電漿的操作,並較佳地係在相同腔室中執行以獲得最大產量優勢。在此等操作之一個操作期間,各向異性(定向的)電漿修改被蝕刻的介電質膜的塊狀結構及/或組成之一部分成更似二氧化矽(SiO2)或子氧化矽(SiOx)。此膜修改操作可概念化為可控制地及有選擇地用第一電漿條件破壞一部分介電質膜。在此等操作之第二個操作期間,各向同性(不定向的)條件有選擇地移除在具有塊狀性質之下層介電質膜上方的經修改膜部分(具有經修改的結構或組成)。可順序地且重複地執行此等操作以實現膜移除之任一期望的累積量(亦即,實現期望的蝕刻深度)。經由塊狀膜蝕刻分成兩個不同操作或操作模式的
此分隔,電漿條件之設計以及提供彼等條件的蝕刻腔室之設計具有明顯更高的自由度及/或更大的製程窗。
介電質膜蝕刻製程區分成至少此等兩個獨立操作模式亦提供對蝕刻參數的控制程度,此控制程度賦能將各向異性剖面蝕刻成低k或其它介電質膜,該低k或其它介電質膜有利地極小修改在鄰近於蝕刻特徵結構之區域中的介電質膜組成(例如,暴露於電漿蝕刻不負面影響側壁)。此精確控制之重要來源來自本質上具高化學性質之各向同性蝕刻條件,且因而在具有背離SiO2的整體性質之塊狀性質(例如,在一定程度上結合碳)的下層介電質之間提供非常高的選擇性。儘管在兩種材料組成物之間的高選擇性係經常用於在消耗第一材料層後停止蝕刻(例如,在多材料沉積膜堆疊中作為用具有不可蝕刻的組成物之下層蝕刻停止層終止具有可蝕刻的組成物之層蝕刻的方式),本文之技術用對塊狀膜本身為高選擇性的蝕刻製程來漸進地蝕刻穿過塊狀膜。
在實施例中,多操作模式蝕刻製程完全不含碳氟化合物。儘管習知介電質蝕刻依賴沉積在經蝕刻的介電層之側壁上的CF聚合物來實現蝕刻各向異性,但本文之方法經由膜修改製程(模式)之各向異性結合膜蝕刻製程(模式)之高選擇性來實現蝕刻各向異性。避免通常基於碳氟化合物(基於CxFy)的蝕刻製程以及伴隨的CF聚合物致使任一鈍化聚合物之經蝕刻介電質表面相對較清潔。因而,可避免藉由電漿或可破壞介電質(例如,經
由膜中之碳物種的氧化)的其它構件進行之後蝕刻處理(post-etch treatment;PET)。
現提供蝕刻方法、如何可在單個腔室中執行此方法以及適於執行此蝕刻方法之實施例的腔室硬體之更詳細描述。首先描述蝕刻方法,第1圖係圖示根據本發明之實施例以單個電漿蝕刻腔室來蝕刻低k介電質膜之多操作模式蝕刻製程100的流程圖。第3A圖至第3F圖圖示表示根據本發明之實施例多操作模式蝕刻製程100之方法對暴露於製程之示例性工作件的效果之橫截面圖。
從操作105開始,將工作件載入電漿處理腔室中。儘管工作件大體可採取任何形式,但在第2A圖提供的說明性實施例中,工作件包括基板302,將要蝕刻之介電質係設置在該基板302上。基板302可具有適於承受製造製程的任一材料且作為可設置及/或形成微電子元件層(諸如,針對積體電路、光學、太陽能、微機電系統,或類似的微/毫微製造元件之彼等層)的基底。根據本發明之實施例,基板302由基於第IV族的材料組成,該等材料諸如(但不限於)結晶矽、鍺或矽/鍺。在具體實施例中,基板302係單晶矽基板。在另一實施例中,基板302由III-V族材料組成。在另一實施例中,複數個主動元件設置在標定為基板302之區域內。
工作件進一步包括待蝕刻之暴露的介電質。在第1圖及第3A圖至第3F圖所圖示的示例性實施例中,暴露的介電質係低k材料,但更大體而言可為非二氧化矽但藉
由本文描述之機制可修改為更似氧化矽(SiOx)之材料的任一材料。在第3A圖所圖示之示例性實施例中,低k介電層304具有小於二氧化矽之介電係數(例如,小於約3.9)的介電係數。在進一步實施例中,低k介電層304係諸如(但不限於)以下之材料:氟摻雜二氧化矽、碳摻雜二氧化矽、多孔二氧化矽、多孔碳摻雜二氧化矽、基於旋塗式矽氧烷(silicone)的聚合介電質,或旋塗式有機聚合介電質。根據一個說明性實施例,低k介電層304係具有小於2.7的塊狀介電常數之多孔SiCOH層。
儘管多操作模式蝕刻製程100適用於無遮罩蝕刻,例如在下層構形用於形成低k介電層中之特徵結構的蝕刻中(例如,低k間隔物蝕刻),但在說明性實施例中遮住低k介電層304(例如,針對通孔或渠溝蝕刻)。如第3A圖所圖示,遮罩層306係設置在低k介電層304之一部分上的光阻層或硬遮罩層。光阻劑可為此項技術中已知的任何光阻劑(例如,193、EUV等)。類似地,在遮罩層306係硬遮罩時,可使用此項技術中已知的能夠提供對SiOx蝕刻製程的期望選擇性的任何材料。示例性材料包括:無定形碳(例如,APF®)、矽或金屬(例如,鈦或鉭)之氮化物、矽或金屬之碳化物等。
回到第1圖,在操作110處,用離子流轟擊工作件之暴露部分以改變暴露材料層的性質,且更特定而言降低低k膜之頂部厚度中的碳含量。離子流較佳地為各向異性的以使遮罩下方的區域不暴露於該離子流。離子流可
具有具低離子能量之一或多個類型的原子物種或分子物種。因而,在一個有利的實施例中,該等物種將機械研磨低k材料中的組分(例如,敲掉甲基)而非與低k材料中的該等組分化學反應,且因此離子流將來源於與目標組分具有相對低的化學反應性之源氣體。示例性離子物種包括:氦離子、氖離子、氙離子、氮離子,或較佳Ar+具有低游離電位(例如,2-4 eV)之氬離子,以可提供極低電漿直流偏壓來降低離子流之能級。正電性稀釋劑(如氖及氦)亦可添加至氬環境以進一步調和離子流能量。製程壓力有利地低於10 mTorr以獲得多定向性,且更有利地低於5 mTorr。已發現約為50 W至100 W(取決於饋送氣體之游離電位)的低射頻功率對於藉由自氧化矽基質擊出碳物種來修改低k介電質膜係有利的。
第3B圖圖示操作110對工作件的效果。如圖所示,離子流307形成低k介電層304之經修改的部分308。在實施例中,經修改的部分308耗盡了碳,且因此相對於低k介電層304之未經修改的塊狀部分富集SiOx。亦可改變與低k介電層304有關之經修改的部分308之膜密度及形態。舉例而言,可在操作110期間緻密化或藉由離子轟擊機械地破壞(例如,粗糙化)經修改的部分308。取決於離子流,經修改的部分308之深度可總計為50 Å或更小。
回到第1圖,在操作120處,乾式蝕刻製程用於在下層塊體上方有選擇地移除低k介電層之SiOx富集之經修
改的部分(或第3C圖中之低k介電層304之未經修改的部分304B)。因為已移除之經修改的部分約為低k介電質膜中之分子組分的尺寸,所以應將蝕刻操作120視為原子層蝕刻或分子級別蝕刻(molecular level etching;MLE)。在一個實施例中,操作120必需自至少三氟化氮(NF3)及氫氣源(諸如氨(NH3)或水汽(H2O))產生的電漿以產生反應性蝕刻物種NH4F及/或NH4F.HF。在進一步實施例中,在操作120處伴隨NF3及NH3提供水汽(H2O)以進一步提高SiOx蝕刻速率。亦可在操作120期間使用非反應性氣體(例如,He)。
在另一實施例中,蝕刻製程100使用siconi類型之蝕刻技術,必需將在操作120期間執行的二步驟機制,在共同讓渡的美國專利申請案第12/620,806號中更詳細地進一步描述該siconi類型之蝕刻技術。在此實施例中,在較低的第一工作件溫度(例如,30℃)下形成水汽(H2O)及薄固體矽酸鹽蝕刻副產物(例如,(NH4)2SiF6)且然後在較高的第二工作件溫度(例如,100℃)下自工作件昇華矽酸鹽。然而在某些實施例中,例如在需要較高的蝕刻速率時,在固定的升高之工作件溫度下執行siconi蝕刻。在無循環基質溫度之其它額外負擔的情況下,為了獲得更高的蝕刻速率可更快速地循環蝕刻製程100。較佳地,操作120處的固定工作件溫度係在約80℃與100℃之間。儘管用於方法100之硬遮罩及無遮罩實施例的較高溫度係可能的,但在操作120處用於使用光
阻劑之實施例的最大固定工作件溫度低於約120℃以避免網狀結構。在某些實施例中,在固定高溫下執行操作110及操作120兩者以避免關於循環工作件溫度之任何額外負擔。
回到第1圖,蝕刻製程控制器決定在完成操作120後是否滿足蝕刻製程終止標準。蝕刻製程終止標準可基於製程持續時間、端點訊號(光學或其它)等。若滿足了蝕刻製程終止標準,則製程100係完成的並自腔室150卸載工作件。若還未滿足蝕刻製程終止標準,則藉由回到操作110開始後續迭代。
對於進一步實施例,在操作130處將低溫保形矽基介電層沉積在工作件上。可在蝕刻製程100期間週期性地執行沉積操作130,例如以抵消由修改操作110引起之任一剖面底切或弓形,該修改操作110根據非理想的無碰撞傳送模式之離子流具不完美的各向異性。如第1圖所圖示,僅以在每一蝕刻循環必需單次執行操作110及操作120兩者的情況下已滿足蝕刻循環計數臨限值的條件執行沉積操作130。因而,對於以預定比率或工作循環將蝕刻操作與沉積操作交錯在一起的「多X」循環過程,可以每個蝕刻循環(蝕刻循環計數臨限值為1)或以某一較低的速率(蝕刻循環計數臨限值大於1)執行沉積操作130。
如在第3D圖中進一步圖示,沉積操作130形成保護層312,保護層312至少形成在由蝕刻操作120暴露的
塊狀低k介電質304B之側壁上。保護層312之厚度取決於相對於蝕刻操作120執行操作130的頻率而可變化很大。一般而言,沉積操作130必需保形沉積製程以確保側壁覆蓋。在實施例中,保形沉積製程係低溫製程(例如,低於130℃)以保存覆蓋遮罩材料(例如,光阻劑)。在實施例中,保護層312係二氧化矽層。然而,在一個有利的實施例中,保護層312係碳摻雜的氧化矽層。碳摻雜層之沉積可有利地增大保護層130對蝕刻操作120的阻力,以使經由蝕刻操作120之後續迭代(iteration)不會完全移除保護層130,特別是不會從渠溝310之側壁完全移除保護層130。在又一實施例中,保護層312係氮化矽層。對於保護層130提供對蝕刻操作120的選擇性的碳摻雜實施例及氮化物實施例,可使蝕刻循環計數臨限值更大以得到較大部分消耗在蝕刻中的製程100,並增大總低k介電質蝕刻速率。
取決於實施例,可在操作130處使用任何普遍已知的矽前驅物,該等矽前驅物諸如,但不限於:四氟化矽(SiF4)、四氯化矽(SiCl4)、矽烷(SiH4),或任何普遍已知的含矽碳化前驅物,諸如,但不限於:八甲基環四矽氧烷(octamethylcyclotetrasiloxane;OMCTS)、四甲基二矽氧烷(tetramethyl-disiloxane;TMDSO)、四甲基環四矽氧烷(tetramethylcyclotetrasiloxane;TMCTS)、四甲基二乙氧基二矽氧烷(tetramethyl-diethoxyl-disiloxane;TMDDSO)、二甲基二
甲氧基矽烷(dimethyl-dimethoxyl-silane;DMDMS)。在進一步實施例中,在保護層為氮化物時,可使用諸如,但不限於,三矽胺烷(trisillylamine;TSA)及二矽胺烷(disillylamine;DSA)之前驅物。在PECVD製程中,此等源之任何源可與氧自由基源,諸如,但不限於:氧(O2)、臭氧(O3)、二氧化碳(CO2),或水(H2O)反應。
在操作130之後,藉由回到操作110來執行後續迭代。以此方式,穿過目標膜漸進地推進蝕刻前部(如在第3E圖及第3F圖所進一步圖示)以形成逐步加深的渠溝210B。
第2圖係一流程圖,進一步說明蝕刻腔室如何在蝕刻製程100之多個模式中操作。方法200自操作205處於腔室中接收工作件開始。在設置於距工作件最近之噴淋頭下方的腔室之第一區域中激發離子研磨電漿。射頻源在工作件上提供直流偏壓電位以產生本文其它處描述的離子流用於修改操作110。在實施例中,經由基座或夾盤電容耦合射頻源以在直接位於工作件上之第一腔室區域中產生電漿,該基座或夾盤支撐該工作件。在一個此類實施例中,自夾盤(亦即,夾盤係射頻驅動的)開始電容耦合的電漿(capacitively coupled plasma;CCP)且距工作件最近的噴淋頭提供射頻返迴路徑(亦即,作為陽極)。
在操作320期間,在腔室之第二區域中激發SiO蝕刻電漿,以誘導離子流至工作件的方式來最小化或避免對
工作件偏壓。在一個實施例中,為了致使蝕刻操作320具高化學性質,將第二腔室區域設置在距工作件最近的噴淋頭上方,因此第二腔室距工作件比距在操作310期間產生的離子研磨電漿相對更遠。在實施例中,在操作320期間,基座或夾盤未經射頻供電,以最小化工作件偏壓電位。在操作320處使用遠端及/或軟游離技術以形成用於本文其它處描述之蝕刻操作120的反應性物種而不在工作件上形成顯著的偏壓電位。在一個此類實施例中,從設置在自晶圓與噴淋頭相對的側上之電極到距工作件最近的噴淋頭或從該噴淋頭到該電極(例如,從或到距工作件最近之噴淋頭上方的電極)開始第二CCP。在另一實施例中,在蝕刻操作120期間使用直流放電作為用於軟游離之電子源。在替代性實施例中,在腔室之第二區域中使用遠端電漿源(RPS)形成電漿。在又一實施例中,在腔室之第二區域中使用感應耦合的電漿(ICP)形成電漿。在本文其它處進一步描述用於此等實施例之每一實施例之蝕刻腔室硬體配置。
對於沉積保護層(例如,在第1圖中之操作130)之實施例,在腔室之遠端第二區域中產生氧化電漿並將含矽(及碳)前驅物引入至腔室中(例如引入至第一腔室區域中)以與傳送到工作件的氧化物種反應。因而,可使用電漿蝕刻腔室之第一區域及第一操作模式用於修改低k介電質膜之部分厚度,且可使用電漿蝕刻腔室之第二區域及第二操作模式用於蝕刻低k介電質膜之經修改
的厚度。可以第三操作模式進一步操作第二區域以沉積保護層。
對於使用siconi類型之製程的實施例,siconi類型之蝕刻的兩個階段可進一步必需在蝕刻腔室之不同區域中開始並產生兩種不同的電漿。舉例而言,可使用第一腔室區域及第二腔室區域兩者執行siconi類型之製程,或可使用第二腔室區域及第三腔室區域執行siconi類型之製程。
如第4圖中所圖示,如在本文其它處所描述經配置的一或多個低k蝕刻腔室405耦接至整合平臺以形成多腔室處理系統。可藉由在第4圖中圖示之多腔室系統中的低k蝕刻腔室405之每一低k蝕刻腔室405執行描述用於多操作模式蝕刻製程100的實施例之一或多個實施例。參照第4圖,多腔室處理平臺400可為此項技術中已知的能夠適應性地同時控制複數個製程模組的任何平臺。示例性實施例包括OpusTM AdvantEdgeTM系統、ProducerTM系統或CenturaTM系統,所有該等系統全部可購自美國加州聖克拉拉市的應用材料公司。
處理平臺400可進一步包括整合測量(IM)腔室425以提供控制信號來允許本文描述之蝕刻製程之任何蝕刻製程的適應性控制。IM腔室425可包括此項技術中普遍已知的測量各個膜性質(諸如,厚度、粗糙度、組成)之任何測量法,且IM腔室425可進一步能夠以自動化方式在真空下特徵化光柵參數(諸如,臨界尺寸(CD)、
側壁角度(SWA)、特徵結構高度(HT))。如在第4圖中所進一步圖示,多腔室處理平臺400進一步包括固持前開式統集盒(front opening unified pod;FOUP)435及445之負荷鎖定腔室430,負荷鎖定腔室430耦接至具有機器人機械手450之移送腔室401。
隨著在低k蝕刻腔室405中執行的蝕刻製程與製程100之每一循環迭代地進行,低k蝕刻腔室405可自動地循環通過製程200,致動將射頻源耦接至不同電極及/或操作單獨地耦接至不同電極的不同射頻源之中繼器以在操作模式之間調變。可藉由一或多個控制器470提供對低k蝕刻腔室405之此控制。控制器470可為任一形式之通用資料處理系統之一個通用資料處理系統,該通用資料處理系統可用於控制各個子處理器及子控制器之工業環境中的。一般而言,控制器470包括與記憶體473及輸入/輸出(I/O)電路系統474通訊之中央處理單元(CPU)472,亦包括其它常見組件。由CPU 472執行的軟體指令使多腔室處理平臺400(例如)將基板載入到低k蝕刻腔室405中、執行多操作模式蝕刻製程200,並自低k蝕刻腔室405卸載基板。如先前技術中已知,提供機器人的機械手450或負荷鎖定腔室430之額外控制器來管理多個低k蝕刻腔室405的整合。
本文其它處詳細描述之蝕刻製程腔室之一或多個蝕刻製程腔室可使用用於分配及輸送流體(反應性物種、氣體等)至工作件的習知噴淋頭或「雙區」噴淋頭(「dual
zone」showerhead;DZSH)。儘管DZSH之詳細描述可見於共同讓渡的美國專利第12/836,726號,但第5A圖及第5B圖圖示可有利地用於多操作模式電漿蝕刻腔室之特定實施例中之DZSH 500的一些特徵結構。第5A圖圖示DZSH之切口透視圖且第5B圖圖示第5A圖之切口透視圖的放大部分。如圖所示,DZSH 500包括具有複數個第一孔514之上歧管510及具有複數個第二孔524之下歧管530。第一流體流F3在進入設置在DZSH 500下方的處理區域之前經由孔514、中心歧管中的第二開口524及底歧管530中的第二開口534穿過噴淋頭。第二流體流F4穿過通道網路至第二氣體通道538之一或多個第二氣體通道538並經由孔542傳送至處理區域。第一流體及第二流體在DZSH中彼此隔離直到該第一流體及該第二流體各別傳送進處理區域。因而,可提供激發狀態之第一流體(例如,作為自由基物種或離子物種)而第二流體可以未反應狀態及/或未激發狀態提供。
在實施例中,電漿蝕刻腔室包括耦接至DZSH的電漿源。在一個實施例中,可由Siconi蝕刻/預清洗腔室(可購自應用材料公司)修改「Siconi蝕刻」源,以提供用於本文描述之多個操作模式腔室的至少一種電漿。舉例而言,Siconi蝕刻源可提供實施離子研磨操作(例如,第1圖之110)之第一電容性電漿源,以及實施本文描述之蝕刻操作(例如,第1圖之120)及/或可選的沉積操作(例如,第1圖之130)之第二電容耦合的電漿源
中之至少一個電漿源。
第6A圖、第6B圖及第6C圖圖示根據實施例之蝕刻腔室的橫剖面圖,該蝕刻腔室被配置為多個操作模式(狀態)以執行蝕刻製程100中之操作的每一操作。一般而言,蝕刻腔室601包括實施離子研磨操作的第一電容耦合的電漿源、實施蝕刻操作及實施可選的沉積操作之第二電容耦合的電漿源。第6A圖圖示根據實施例之蝕刻腔室601的橫截面圖,該蝕刻腔室601經配置以執行(第1圖)修改操作110。蝕刻腔室601具有環繞夾盤650之接地的腔室壁640。在實施例中,夾盤650係在處理期間夾持工作件302至夾盤650之頂表面的靜電夾盤(ESC),儘管亦可使用此項技術中已知的其它夾持機構。
夾盤650包括嵌入的熱交換器線圈617。在示例性實施例中,熱交換器線圈617包括一或多個傳熱流道,傳熱流體(諸如乙二醇/水混合物、Galden®或Fluorinert®等)可通過該等一或多個傳熱流道以控制夾盤650之溫度並最終控制工作件302之溫度。
夾盤650包括耦接至高壓直流電源648之網格649以使網格649可傳送直流偏壓電位以實施工作件302之靜電夾緊。夾盤650耦接至第一射頻功率源且在一個此類實施例中,網格649耦接至第一射頻功率源以使直流電壓偏移及射頻電壓電位兩者耦接在夾盤650頂表面上之薄介電層上。在說明性實施例中,第一射頻功率源包括
第一射頻產生器652及第二射頻產生器653。射頻產生器652、653可以此項技術中已知的任一工業頻率操作,然而在示例性實施例中射頻產生器652以60 MHz操作以提供有利的定向性。在亦提供第二射頻產生器653時,示例性頻率為2 MHz。
在夾盤650係經射頻供電的情況下,藉由第一噴淋頭625提供射頻返迴路徑。第一噴淋頭625設置在夾盤上方以分配第一饋送氣體進入由第一噴淋頭625及腔室壁640界定的第一腔室區域684。因而,夾盤650及第一噴淋頭625形成第一射頻耦合電極對以電容激發第一腔室區域684內之第一饋送氣體的第一電漿670。由射頻功率夾盤之電容耦合引起的直流電漿偏壓(亦即,射頻偏壓)產生從第一電漿670至工作件302的離子流(例如,在第一饋送氣體係Ar時為Ar離子)以提供離子研磨電漿(例如,在第2圖中之操作220)。第一噴淋頭625可為接地的或耦接至射頻源628,射頻源628具有可以不同於夾盤650之頻率的一頻率(例如,13.56 MHz或60 MH)操作的一或多個產生器。在所圖示的實施方式中,第一噴淋頭625經由中繼器627可選擇地耦接至接地或耦接至射頻源628,在蝕刻製程期間可(例如)由控制器420自動地控制中繼器627。
如在第6A圖中進一步圖示,蝕刻腔室601包括能夠在低製程壓力下具有高產量之泵堆。在實施例中,至少一個渦輪分子泵665、666經由閘閥660耦接至第一腔室
區域684並設置在夾盤650下方,與第一噴淋頭625相對。一或多個渦輪分子泵665、666可為具有適合的產量之任何可購得的渦輪分子泵且更特定而言係經適當地調整尺寸以在第一饋送氣體之期望的流動速率下(例如,Ar之50 sccm至500 sccm)維持低於10 mtorr且較佳地低於5 mTorr的製程壓力。在第6A圖圖示之實施例中,夾盤650形成在兩個渦輪泵665及666之間中心處之基座的一部分,然而在替代性配置中,夾盤650可在基座上,該基座藉由具有中心與夾盤650之中心對準之單個渦輪分子泵自腔室壁640懸臂支撐。
設置在第一噴淋頭625上方的係第二噴淋頭610。在一個實施例中,在處理期間,第一饋送氣體源(例如氬瓶690)耦接至氣體入口676,且第一饋送氣體流動通過延伸穿過第二噴淋頭610的複數個孔680,進入第二腔室區域681,並經由延伸穿過第一噴淋頭625的複數個孔682進入第一腔室區域684。具有孔678之額外流分配器615可進一步分配第一饋送氣體流616遍及蝕刻腔室601之直徑。在替代實施例中,第一饋送氣體經由與第二腔室區域681隔離的孔683直接流動進入第一腔室區域684(由虛線623指示)。舉例而言,在第一噴淋頭係DZSH時,孔683對應於第5B圖中的孔542。
第6B圖圖示根據實施例自第6A圖中圖示之狀態經重新配置以執行第1圖之蝕刻操作120之蝕刻腔室601的橫截面圖。如圖所示,第二電極605設置在第一噴淋頭
625上方,在第一噴淋頭625與第二電極605之間具第二腔室區域681。第二電極605可進一步形成蝕刻腔室601的蓋。第二電極605與第一噴淋頭625藉由介電質環620電絕緣並形成第二射頻耦合電極對以使第二腔室區域681內之第二饋送氣體的第二電漿691電容放電。有利地,第二電漿691不在夾盤650上提供顯著的射頻偏壓電位。如第6B圖所圖示,第二射頻耦合電極對之至少一個電極耦接至射頻源用於激發第2圖中之操作220處的蝕刻電漿(在第1圖中之蝕刻操作120期間)。第二電極605電耦合至第二噴淋頭610。在較佳實施例中,第一噴淋頭625耦接至接地平面或為浮動的並可經由中繼器627耦接至接地,中繼器627允許第一噴淋頭625在離子研磨操作模式期間亦由射頻電源628供電。在第一噴淋頭625為接地的情況下,儘管若第一噴淋頭625被供電,亦可使第二電極605為浮動的,但具有以13.56 MHz或60 MHz操作之一或多個射頻產生器之射頻電源608(例如)經由中繼器607耦接至第二電極605,中繼器607將允許第二電極605在其它操作模式期間(例如,在離子研磨操作110期間)亦為接地的。
第二饋送氣體源(諸如NF3瓶691)及氫氣源(諸如NH3瓶692)耦接至氣體入口676。在此模式中,第二饋送氣體流動穿過第二噴淋頭610並在第二腔室區域681中受激發。反應性物種(例如,NH4F)隨後進入第一腔室區域684以與工作件302反應。如進一步圖示,對於
第一噴淋頭625係DZSH之實施例,可提供一或多種饋送氣體以與由第二電漿691產生的反應性物種反應。在一個此類實施例中,水源693可耦接至複數個孔683。
在實施例中,夾盤650在與第一噴淋頭625垂直的方向上可移動距離△H2。夾盤650在由波紋管655等環繞的致動機構上,以允許夾盤650移動更靠近或更遠離第一噴淋頭625作為控制夾盤650與第一噴淋頭625之間的傳熱(處於80℃-150℃或以上之高溫)之方式。因而,可藉由在相對於第一噴淋頭625的第一預定位置與第二預定位置之間移動夾盤650來實施siconi蝕刻製程。或者,夾盤650包括升降機以提升工作件302離開夾盤650之頂表面一距離△H1以在蝕刻製程期間控制第一噴淋頭325的加熱。在其它實施例中,在以固定溫度(例如,約90℃-110℃)執行蝕刻製程時,可避免夾盤位移機構。
控制器420在蝕刻製程期間藉由交替地自動供電第一及第二射頻耦合電極對來交替地激發第一電漿690及第二電漿691。
第6C圖圖示根據實施例經重新配置以執行第1圖所圖示之沉積操作130之蝕刻腔室601的橫截面圖。如圖所示,在第二腔室區域681中由射頻放電產生第三電漿692,可以描述用於第二電漿691之方式中之任一方式實施該射頻放電。在第一噴淋頭625在沉積期間被供電以產生第三電漿692時,第一噴淋頭625藉由介電隔片630與接地的腔室壁640絕緣以使第一噴淋頭625相對於腔
室壁為電學上浮動的。在示例性實施例中,氧化劑(O2)饋送氣體源694耦接至氣體入口676。在第一噴淋頭625係DZSH之實施例中,本文其它處描述之含矽前驅物中之任一含矽前驅物(例如,OMCTS源695)可耦接進入第一腔室區域684以與自第二電漿692通過第一噴淋頭625的反應性物種反應。或者,含矽前驅物亦伴隨氧化劑流動通過氣體入口676。
第7圖圖示根據實施例經配置以執行修改操作110之蝕刻腔室701的橫截面圖。如圖所示,蝕刻腔室701具有懸臂式夾盤660及中心與夾盤660之中心對準的單個渦輪泵665。如進一步圖示,第一噴淋頭625係接地的而夾盤660及第二電極605兩者經由中繼器607耦接至相同的射頻源以在離子研磨210與蝕刻操作220之間交替夾盤660與第二電極605之間的驅動電極以分別實施修改操作110與蝕刻操作120,其中電漿之位置以描述在腔室601內容中的方式於第一腔室區域684與第二區域681之間變化。或者,射頻源608可獨立於射頻源供電夾盤660(例如,產生器652及653之一或多個產生器)而供電第二電極,其中電漿之位置以描述在腔室601內容中的方式於第一腔室區域684與第二區域681之間變化。
第8A圖圖示根據實施例之蝕刻腔室801的橫截面圖,該蝕刻腔室801經配置以執行第1圖所圖示之蝕刻製程的修改操作110。一般而言,蝕刻腔室801包含實
施離子研磨操作的第一電容耦合的電漿源、實施蝕刻操作的遠端電漿源,以及實施沉積操作的可選第二電容耦合的電漿源。
蝕刻腔室801包括設置在第一噴淋頭625上方與夾盤660相對的遠端射頻電漿源823。在離子研磨操作模式中,蝕刻腔室801提供實質上如描述用於蝕刻腔室601之第一腔室區域684內之電容耦合的第一電漿670。在圖示的實施方式中,夾盤660耦接至第一射頻電源(射頻產生器652及653),且第一噴淋頭625經由中繼器607B可選擇地耦接至接地或第二射頻電源,該第二射頻電源包含一或多個射頻產生器608,該一或多個射頻產生器608可在不同於第一射頻電源652、653之頻率的一頻率下操作。在供電第一噴淋頭625時,第一噴淋頭625藉由介電隔片630與接地的腔室壁640絕緣以使第一噴淋頭625相對於腔室壁640為電學上浮動的。對於供電第一噴淋頭625的實施例,第二噴淋頭610與第二電極605可電連接至與第一噴淋頭625相同的電位。
第8B圖圖示根據實施例自第8A圖圖示之蝕刻腔室801經重新配置以執行第1圖所圖示之蝕刻操作120的蝕刻腔室801之橫截面圖。如第8B圖中圖示,在蝕刻操作模式中,遠端射頻電漿源823將使經由氣體入口824提供的第二饋送氣體之第二電漿693放電。在一個示例性實施例中,遠端射頻電漿源823與第一噴淋頭625兩者經由可由控制器控制的中繼器607A耦接至相同的射
頻電源821以交替地供電第一電漿670與遠端電漿693。將在不於夾盤660上置放顯著的射頻偏壓電位的情況下產生遠端電漿693。在較佳實施例中,第一噴淋頭625係接地的或浮動的。第二饋送氣體源691、692(NF3、NH3)耦接至氣體入口824,伴隨反應性物種(例如,NH4F)隨後流動穿過第一噴淋頭625。如本文其它處描述,額外流體分配可具備第二噴淋頭610及/或流體分配器615。在第一噴淋頭625包括DZSH的實施例中,可經由孔693提供水蒸氣693以使水蒸氣693與經由孔682進入第一腔室區域684的反應性物種反應。
第8C圖圖示根據實施例自第8A圖及第8B圖圖示之狀態經重新配置以執行第1圖所圖示之沉積操作130之蝕刻腔室801的橫截面圖。如第8C圖中圖示,儘管在沉積操作模式中,但夾盤660仍耦接至包含可為無供電(例如,浮動的)之一或多個射頻產生器652、653的第一射頻電源。第一噴淋頭625耦接至包含一或多個射頻產生器608的第二射頻電源,該一或多個射頻產生器608可處於不同於射頻產生器652之頻率的頻率下(例如,13.56 MHz)。在第一噴淋頭625藉由介電隔片630與接地的腔室壁640絕緣並藉由介電隔片620進一步與第二噴淋頭601絕緣的情況下,到第一噴淋頭625的射頻電源將在第二腔室區域681中產生(例如,諸如O2 694之氧化源氣體之)第三電漿692。在一個示例性實施例中,第一噴淋頭625與遠端射頻電漿源823兩者經由可由控
制器470控制的中繼器607A耦接至相同的射頻電源821以交替地供電蝕刻與沉積(例如,分別為第1圖中的操作120及操作130)之間的第三電漿692與遠端電漿693。
控制器420將在蝕刻製程期間藉由交替地自動供電兩個源來交替地激發第一電漿670與遠端電漿693。控制器420可類似地使腔室801進入沉積模式。
第9A圖圖示根據實施例經配置以執行第1圖所圖示之修改操作110之蝕刻腔室901的橫截面圖。一般而言,蝕刻腔室901包含實施離子研磨操作的電容耦合的電漿源,以及實施蝕刻操作及實施可選的沉積操作之電子束源。如第9A圖中所圖示,在第一噴淋頭625設置在夾盤650上方的情況下提供實質上如本文其它處描述之電容性放電以分配第一饋送氣體690進入第一腔室區域684。夾盤660與第一噴淋頭625形成第一射頻耦合電極對以使第一饋送氣體(例如,Ar)之射頻電漿670電容放電。
第9B圖圖示根據實施例經重新配置以執行第1圖所圖示之蝕刻操作120之蝕刻腔室901的橫截面圖。如圖所示,高壓直流電源943耦接至第二電極605與第二噴淋頭610以形成設置在第一噴淋頭625上方的直流電極對以在直流電極之間的腔室區域中產生直流輝光放電618。直流電極對藉由介電隔片620與第一噴淋頭625電絕緣。第一噴淋頭625藉由介電隔片630進一步與腔室壁640絕緣以允許對第一噴淋頭625的控制。
在操作期間,以陰極直流電位(例如4-8 kV)偏壓第二電極605而以陽極電位(例如,-100 V至-200 V)偏壓第二噴淋頭610。來自產生自第一饋送氣體(例如,Ar瓶690)之直流輝光放電618的電子通過孔680進入第二腔室區域681。第一噴淋頭625亦經由中繼器耦接至直流電源(例如耦接至第二噴淋頭610),以使第一噴淋頭625相對於第二電極605之陰極電位負偏壓至陽極電位。第一噴淋頭625上之負偏壓允許電子通過第一噴淋頭625並進入第一腔室區域684。為了進一步推進此目的,第一噴淋頭625可具有大洞。以此方式,「電子束」源係軟游離第一腔室區域684中之饋送氣體(例如,在DZSH實施例中由孔683提供的NF3及NH3)以提供反應性蝕刻物種(例如,NH4F等)而在工作件302上無顯著偏壓的構件。
如在第9B圖進一步圖示,儘管夾盤660在離子研磨模式期間耦接至射頻源(產生器652及653),但夾盤660亦可在蝕刻操作及沉積操作之一者或兩者期間維持在接地電位或陰極電位。提供於接地電位與正偏壓之間的可控制之可變夾盤電位963將控制從直流輝光放電618到工作件302的電子通量。在進一步實施例中,蝕刻腔室901包括設置在第一噴淋頭625與夾盤660之間的分流電極(thief electrode)947。分流電極625經由可變電容器964耦接至接地以進一步控制至工作件305的電子通量。如圖所示,分流電極947係藉由第一介電隔片630
與第一噴淋頭625絕緣並藉由第二介電隔片937與接地的腔室壁640絕緣的導電環。
第9C圖圖示根據實施例經重新配置以執行第1圖所圖示之沉積操作130之蝕刻腔室901的橫截面圖。使用實質上如本文其它處描述之用於蝕刻操作120的直流電源或在第二腔室區域681中產生的第二射頻電漿,以執行保護層之PECVD沉積。在使用直流電源時,來自第二噴淋頭610的電子通過第一噴淋頭625並經由孔683提供含矽前驅物(諸如,OMCTS 695)。亦可藉由孔683供應氧以藉由電子通量游離氧。
控制器420將在蝕刻製程期間藉由交替地自動供電兩個源來交替地激發第一電漿670與直流輝光放電618。控制器420可類似地使腔室901進入沉積模式。
在進一步實施例中,可用電子通量執行沉積的保護層之原位硬化,本質上執行電子束硬化類型之製程。提供於接地電位與正偏壓之間的可控制之可變夾盤電位963亦為此目的可控制從直流輝光放電618到工作件302的電子通量。具體而言,在需要硬化時,工作件302將處在接地電位處;在不需要硬化時,工作件302處於陰極電位處。
第10圖圖示根據實施例之蝕刻腔室1001的橫截面圖,該蝕刻腔室1001經配置以執行第1圖所圖示之蝕刻製程100的各個模式。一般而言,蝕刻腔室1001包含實施離子研磨操作的CCP,以及實施蝕刻操作及實施可選
的沉積操作之感應耦合的電漿源(inductively coupled Plasma source;IPS)。
如第10圖中所圖示,提供上文在用於第一腔室區域684中之修改操作110(第1圖)之CCP電漿之情境中描述的所有腔室組件,夾盤660及第一噴淋頭625再次形成射頻電極對。在實施例中,第一噴淋頭625係實質上如本文其它處描述的可被供電的、電學上浮動的或接地的DZSH。對於蝕刻操作(例如,第1圖中之120),導電線圈組1052耦接至包括產生器608的射頻源,以用此項技術中已知的任一方式產生感應耦合的電漿692。在第一噴淋頭之DZSH實施例中結合大尺寸洞之ICP源能夠有效地游離經由介電質蓋1006所引入的饋送氣體(諸如,NF3 691及NH3 692)。
控制器420將在蝕刻製程期間藉由交替地自動供電兩個源來交替地激發第一電漿670與ICP電漿692。控制器420可類似地使腔室1001進入沉積模式。
應瞭解上文之描述旨在說明而非限制。此外,熟習該項技術者在閱讀及理解以上描述後將明白除了詳細描述的實施例之外的許多其它實施例。雖然已參考具體的示例性實施例描述了本發明,但將認識到本發明不局限於描述的實施例,而是可用在隨附申請專利範圍之精神及範圍內的修改及變更來實踐本發明。因此應參考隨附申請專利範圍及此申請專利範圍允許的全部等效物決定本發明之範疇。
100‧‧‧蝕刻製程
105‧‧‧操作
110‧‧‧操作
120‧‧‧操作
130‧‧‧操作
150‧‧‧腔室
200‧‧‧方法、製程
205‧‧‧操作
210‧‧‧離子研磨
220‧‧‧蝕刻操作
230‧‧‧操作
304‧‧‧低k介電層
302‧‧‧基板
306‧‧‧遮罩層
304B‧‧‧未經修改的部分
310‧‧‧渠溝
305‧‧‧工作件
312‧‧‧保護層
308‧‧‧經修改的部分
400‧‧‧多腔室處理平臺
310B‧‧‧渠溝
405‧‧‧低k蝕刻腔室
401‧‧‧移送腔室
425‧‧‧IM腔室
430‧‧‧負荷鎖定腔室
435‧‧‧前開式統集盒
445‧‧‧前開式統集盒
450‧‧‧機械手
472‧‧‧中央處理單元
470‧‧‧控制器
474‧‧‧電路系統
473‧‧‧記憶體
514‧‧‧孔
500‧‧‧DZSH
534‧‧‧第二開口
524‧‧‧第二開口
542‧‧‧孔
538‧‧‧第二氣體通道
605‧‧‧第二電極
601‧‧‧蝕刻腔室
608‧‧‧射頻源
607‧‧‧中繼器
615‧‧‧流體分配器
607B‧‧‧中繼器
617‧‧‧熱交換器線圈
610‧‧‧第二噴淋頭
620‧‧‧介電隔片
616‧‧‧第一饋送氣體流
627‧‧‧中繼器
618‧‧‧直流輝光放電
630‧‧‧介電隔片
623‧‧‧虛線
648‧‧‧高壓直流電源
625‧‧‧第一噴淋頭
650‧‧‧夾盤
628‧‧‧射頻源
652‧‧‧產生器、第一射頻電源
640‧‧‧腔室壁
655‧‧‧波紋管
649‧‧‧網格
665‧‧‧渦輪分子泵
653‧‧‧產生器、第一射頻電源
670‧‧‧第一電漿
660‧‧‧夾盤、閘閥
678‧‧‧孔
666‧‧‧渦輪分子泵
681‧‧‧第二區域
676‧‧‧氣體入口
683‧‧‧孔
680‧‧‧孔
690‧‧‧第一饋送氣體、Ar瓶
682‧‧‧孔
692‧‧‧第二饋送氣體源
684‧‧‧第一腔室區域
694‧‧‧氣體源、O2
691‧‧‧第二饋送氣體源、NF3瓶
701‧‧‧蝕刻腔室
693‧‧‧第二電漿、遠端電漿
821‧‧‧射頻電源
695‧‧‧OMCTS源、OMCTS
824‧‧‧氣體入口
801‧‧‧蝕刻腔室
937‧‧‧第二介電隔片
823‧‧‧遠端射頻電漿源
947‧‧‧分流電極
901‧‧‧蝕刻腔室
964‧‧‧可變電容器
943‧‧‧高壓直流電源
1006‧‧‧介電質蓋
963‧‧‧可變夾盤電位
1001‧‧‧蝕刻腔室
1052‧‧‧導電線圈組
F3‧‧‧第一流體流
F4‧‧‧第二流體流
235‧‧‧操作
△H2‧‧‧距離
△H1‧‧‧距離
本發明之實施例係以舉例方式而非限制地圖示於隨附圖式之諸圖中,其中:第1圖係圖示根據本發明之實施例之多操作模式蝕刻製程的流程圖,以單個電漿蝕刻腔室來蝕刻低k介電質膜;第2圖係根據一實施例之流程圖,進一步說明蝕刻腔室如何在由第1圖所圖示之蝕刻製程所使用之多個模式中操作;第3A圖、第3B圖、第3C圖、第3D圖、第3E圖及第3F圖圖示根據本發明實施例之橫截面圖,說明多操作模式蝕刻製程100之方法對暴露於製程之示例性工作件的效果;第4圖係根據實施例之多腔室處理平臺的平面圖,該多腔室處理平臺可經配置以包括一或多個蝕刻腔室以執行第1圖所圖示之多操作模式蝕刻製程;第5A圖圖示根據實施例之雙區噴淋頭的切口透視圖,該雙區噴淋頭可用於蝕刻腔室中以執行第1圖所圖示之多操作模式蝕刻製程;第5B圖圖示根據本發明實施例的第5A圖之切口透視圖的放大部分;第6A圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之蝕刻製程的修改
操作;第6B圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之蝕刻製程的蝕刻操作;第6C圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之蝕刻製程的沉積操作;第7圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之蝕刻製程的修改操作;第8A圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之蝕刻製程的修改操作;第8B圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之蝕刻製程的蝕刻操作;第8C圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之蝕刻製程的沉積操作;第9A圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之蝕刻製程的修改操作;第9B圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之蝕刻製程的蝕刻
操作;第9C圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之蝕刻製程的沉積操作;及第10圖圖示根據實施例之蝕刻腔室的橫截面圖,該蝕刻腔室經配置以執行第1圖所圖示之各個操作。
200‧‧‧方法、製程
205‧‧‧操作
210‧‧‧離子研磨
220‧‧‧蝕刻操作
230‧‧‧操作
235‧‧‧操作
Claims (20)
- 一種電漿蝕刻腔室,包含:一夾盤,該夾盤在一蝕刻製程期間支撐一工作件;一第一噴淋頭,該第一噴淋頭設置在該夾盤上方以分配一第一饋送氣體進入該第一腔室區域,其中該夾盤及該第一噴淋頭形成一第一射頻耦合電極對以電容激發該第一噴淋頭與該夾盤之間的一第一腔室區域內之該第一饋送氣體之一第一電漿;一第二電極,該第二電極設置在該第一噴淋頭上方,與該夾盤相對,其中該第二電極及該第一噴淋頭形成一第二射頻耦合電極對以使該第一噴淋頭與該第二電極之間的一第二腔室區域內之一第二饋送氣體的一第二電漿電容放電;以及一控制器,該控制器在該蝕刻製程期間藉由交替地自動供電該第一射頻耦合電極對與該第二射頻耦合電極對來交替地激發該第一電漿與該第二電漿。
- 如請求項1所述之電漿蝕刻腔室,其中該第二電極係分配該第一饋送氣體及該第二饋送氣體進入該第二腔室區域的一第二噴淋頭,且其中該第一噴淋頭進一步將該第一饋送氣體或一反應性物種從該第二電漿輸送到該第一腔室區域。
- 如請求項1所述之電漿蝕刻腔室,其中該夾盤與該第二電極兩者經由可由該控制器切換的一中繼器耦接至一相同的射頻電源。
- 如請求項1所述之電漿蝕刻腔室,其中該夾盤耦接至包含一或多個射頻產生器的一第一射頻電源,且其中該第一噴淋頭經由一中繼器可選擇地耦接至一接地平面與一第二射頻電源兩者,該第二射頻電源包含一或多個射頻產生器,該一或多個射頻產生器可在不同於該第一射頻電源之頻率的一頻率下操作,該中繼器可由該控制器控制。
- 如請求項1所述之電漿蝕刻腔室,其中該夾盤可在垂直於該第一噴淋頭的一方向上移動、或該夾盤包括一升降機,以提升該工作件離開該夾盤,以控制在該蝕刻製程期間藉由該第一噴淋頭對該工作件的加熱。
- 如請求項1所述之電漿蝕刻腔室,其中該第一噴淋頭係一雙區噴淋頭,該雙區噴淋頭具有一第一複數個孔與一第二複數個孔,該第一複數個孔流體地耦接該第一腔室區域及該第二腔室區域,以及該第二複數個孔將該第一腔室區域流體地耦接至與該第二腔室區域絕緣的一流體源。
- 一種電漿蝕刻腔室,包含:一夾盤,該夾盤在一蝕刻製程期間支撐一工作件; 一第一噴淋頭,該第一噴淋頭設置在該夾盤上方以分配一第一饋送氣體進入該第一腔室區域,其中該夾盤與該第一噴淋頭形成一第一射頻耦合電極對以使該第一噴淋頭與該夾盤之間的一第一腔室區域內的該第一饋送氣體之一第一電漿電容放電並提供一射頻偏壓電位於該夾盤上;一遠端射頻電漿源,該遠端射頻電漿源設置在該第一噴淋頭上方,與該夾盤相對,其中該遠端射頻電漿源將使該遠端電漿源內的一第二饋送氣體之一第二電漿放電而不提供一射頻偏壓電位於該夾盤上;以及一控制器,該控制器在該蝕刻製程期間藉由交替地自動供電該第一射頻耦合電極對與該遠端射頻電漿源來交替地激發該第一電漿與該第二電漿。
- 如請求項7所述之電漿蝕刻腔室,其中該夾盤耦接至包含一或多個射頻產生器的一第一射頻電源,且其中該第一噴淋頭耦接至一第二射頻電源,該第二射頻電源包含可在不同於該第一射頻電源之頻率的一頻率下操作的一或多個射頻產生器,該第一噴淋頭藉由一介電隔片與一接地的腔室壁絕緣,以使該第一噴淋頭相對於該腔室壁為電學浮動的。
- 如請求項8所述之電漿蝕刻腔室,其中該第一噴淋頭與該遠端射頻電漿源兩者經由可由該控制器控制的一中繼器 耦接至該第二射頻電源。
- 如請求項7所述之電漿蝕刻腔室,該電漿蝕刻腔室進一步包含設置在該遠端射頻電漿源與該第一噴淋頭之間的一第二噴淋頭,該第二噴淋頭分配由該射頻電漿源產生的蝕刻物種。
- 如請求項7所述之電漿蝕刻腔室,其中該第一噴淋頭係一雙區噴淋頭,該雙區噴淋頭具有一第一複數個孔與一第二複數個孔,該第一複數個孔流體地耦接該第一腔室區域及該遠端電漿源,以及該第二複數個孔將該第一腔室區域流體地耦接至與該遠端電漿源絕緣的一流體源。
- 一種電漿蝕刻腔室,包含:一夾盤,該夾盤在一蝕刻製程期間支撐一工作件;一第一噴淋頭,該第一噴淋頭設置在該夾盤上方以分配一第一饋送氣體進入該第一腔室區域,其中該夾盤與該第一噴淋頭形成一第一射頻耦合電極對,以使該第一噴淋頭與該夾盤之間的一第一腔室區域內的該第一饋送氣體之一射頻電漿電容放電並提供一射頻偏壓電位於該夾盤上;一高壓直流電源,該高壓直流電源耦接至設置在該第一噴淋頭上方的一電極對以產生一直流電漿放電,該電極對藉由一介電隔片與該第一噴淋頭電絕緣,其中該第一噴淋頭負偏壓至一陽極電位,該陽極電位相對該等直流電源 耦合電極之一陰極;以及一控制器,該控制器在該蝕刻製程期間藉由交替地自動供電該第一射頻耦合電極對與該直流電源耦合電極對來交替地激發該射頻電漿與該直流電漿。
- 如請求項12所述之電漿蝕刻腔室,其中該等直流電源耦合電極之一陽極為一第二噴淋頭,該第二噴淋頭具有傳遞來自該直流電漿放電之電子的孔,且其中該第一噴淋頭進一步輸送該第一饋送氣體或傳遞該等電子到該第一腔室區域。
- 如請求項12所述之電漿蝕刻腔室,其中該夾盤在接地電位與一正偏壓之間具有一可控制的直流電位,以控制從該直流電漿到該工作件的電子通量。
- 如請求項14所述之電漿蝕刻腔室,該電漿蝕刻腔室進一步包含設置在該第一噴淋頭與該夾盤之間的一分流電極,其中該分流電極經由一可變電容器接地,以控制從該直流電漿到該工作件的電子通量。
- 如請求項12所述之電漿蝕刻腔室,其中該第一噴淋頭係一雙區噴淋頭,該雙區噴淋頭具有一第一複數個孔與一第二複數個孔,該第一複數個孔傳遞來自該直流電漿放電之電子,以及該第二複數個孔將該第一腔室區域流體地耦 接至與該直流電漿放電絕緣的一流體源。
- 如請求項12所述之電漿蝕刻腔室,其中該夾盤可在垂直於該第一噴淋頭的一方向上移動,以控制在該蝕刻製程期間由該第一噴淋頭對該工作件的加熱。
- 一種電漿蝕刻腔室,包含:一夾盤,該夾盤在一蝕刻製程期間支撐一工作件;一第一噴淋頭,該第一噴淋頭設置在該夾盤上方以分配一第一饋送氣體進入該第一腔室區域,其中該夾盤及該第一噴淋頭形成一第一射頻耦合電極對以使該第一噴淋頭與該夾盤之間的一第一腔室區域內的該第一饋送氣體之一射頻電漿電容放電並提供一射頻偏壓電位於該夾盤上;一導電線圈,該導電線圈設置在該蝕刻腔室之一介電腔室蓋上方並耦接至一射頻源以在設置於該介電腔室蓋與該第一噴淋頭之間的一第二腔室區域中產生一感應耦合的電漿放電;以及一控制器,該控制器在該蝕刻製程期間藉由交替地自動供電該第一射頻耦合電極對及該導電線圈來交替地激發該電容耦合的電漿及該感應耦合的電漿。
- 如請求項18所述之電漿蝕刻腔室,其中該第一噴淋頭係一雙區噴淋頭,該雙區噴淋頭具有一第一複數個孔與一第二複數個孔,該第一複數個孔將來自該第二腔室區域之 反應性物種傳遞至該第一腔室區域,以及該第二複數個孔將該第一腔室區域流體地耦接至與該第二腔室區域絕緣的一流體源。
- 如請求項18所述之電漿蝕刻腔室,其中該夾盤耦接至包含一或多個射頻產生器的一第一射頻電源,且其中該第一噴淋頭耦接至一第二射頻電源,該第二射頻電源包含可在不同於該第一射頻電源之頻率的一頻率下操作的一或多個射頻產生器,該第一噴淋頭藉由一介電隔片與一接地的腔室壁絕緣以使該第一噴淋頭相對於該腔室壁係電學浮動的。
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