TW201314866A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201314866A
TW201314866A TW101129402A TW101129402A TW201314866A TW 201314866 A TW201314866 A TW 201314866A TW 101129402 A TW101129402 A TW 101129402A TW 101129402 A TW101129402 A TW 101129402A TW 201314866 A TW201314866 A TW 201314866A
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Taiwan
Prior art keywords
source
lead
gate
semiconductor wafer
mosfet
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TW101129402A
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English (en)
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TWI538161B (zh
Inventor
Takamitsu Kanazawa
Satoru Akiyama
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
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Abstract

本發明係提供一種可提高半導體裝置之可靠性之技術。在本發明中，形成於半導體晶片CHP1之表面上之閘極焊墊GPj係以比其他引線(汲極引線DL或閘極引線GL)更接近源極引線SL之方式配置。其結果，根據本發明，由於可縮短閘極焊墊GPj與源極引線SL間之距離，故可縮短連接閘極焊墊GPj與源極引線SL之導線Wgj之長度。因此，根據本發明，可充分降低存在於導線Wgj中之寄生電感。

Description

半導體裝置
本發明係關於半導體裝置，特別是關於對例如空調之變換器、電腦電源之DC/DC轉換器、混合動力汽車或電動汽車之逆變器模組等所使用之功率半導體裝置適用且有效之技術。
日本特表2000-506313號公報(專利文獻1)中揭示有提供使低導通電阻與高耐壓兼備之開關元件之技術。具體而言，專利文獻1中揭示有將以碳化矽(SiC)為材料之接合FET(Junction Field Effect Transistor：接面場效電晶體)、與以矽(Si)為材料之MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金屬氧化物半導體場效電晶體)進行串疊連接之構成。
日本特開2008-198735號公報(專利文獻2)中，揭示有為以低導通電壓提供高耐壓之元件，而將以SiC為材料之FET、與以Si為材料之二極體串聯連接之構成。
日本特開2002-208673號公報(專利文獻3)中，揭示有為削減電源模組之面積而包夾平板連接端子，將開關元件與二極體進行疊層之構造。
日本特開2010-206100號公報(專利文獻4)中，揭示有藉由提高以SiC為材料之常關型之接合FET之臨限值電壓而防止滲漏之技術。具體而言，於SiC基板上配置接合FET與MOSFET，於接合FET之閘極電極中將MOSFET進行二極體 連接。
[先行技術文獻] [專利文獻]
[專利文獻1]日本特表2000-506313号公報
[專利文獻2]日本特開2008-198735号公報
[專利文獻3]日本特開2002-208673号公報
[專利文獻4]日本特開2010-206100号公報
作為謀求兼備耐壓之提高與導通電阻之降低之開關元件，有使用串疊連接方式之開關元件。使用串疊連接方式之開關元件係例如將使用比矽(Si)能帶隙更大之材料之常開型接合FET(Junction Field Effect Transistor：接面場效電晶體)、與使用矽(Si)之常關型MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金屬氧化物半導體場效電晶體)串聯連接之構成。根據該串疊連接方式之開關元件，藉由絕緣耐壓較大之接合FET可確保耐壓，且藉由常開型之接合FET所造成之導通電阻之降低、與低耐壓之MOSFET所造成之導通電阻之降低，可獲得使耐壓之提高與導通電阻之降低兼備之開關元件。
在該串疊連接之開關元件之安裝構成中，採用將形成接合FET之半導體晶片、與形成MOSFET之半導體晶片以接合導線進行連接之構成。本發明者新發現：該構成之情形，因存在於接合導線中之寄生電感之影響、或接合FET 之洩漏電流之影響，會造成切換時對低耐壓之MOSFET之源極與汲極間施加設計耐壓以上之大小之電壓。如此般，若對低耐壓之MOSFET施加設計耐壓以上之電壓，則有MOSFET被破壞之虞，而導致半導體裝置之可靠性下降。
發明之目的在於提供一種可提高半導體裝置之可靠性之技術。
本發明之上述以及其他之目的與新穎之特徵係自本說明書之記述及附加圖式而明瞭。
若簡單說明本申請案所揭示之發明中代表性者之概要，則如下。
一實施形態之半導體裝置，其特徵在於：形成接合FET之半導體晶片之閘極焊墊係以比其他引線(閘極引線或汲極引線)更接近於源極引線之方式配置。
若簡單說明本申請案所揭示之發明中藉由代表性者所獲得之效果，則如下。
根據一實施形態，可提高半導體裝置之可靠性。另，可謀求提高半導體裝置之電性特性。
在以下之實施形態中，方便起見有其必要時，分割成複數個部分或實施形態進行說明，除了特別明示之情形，該等並非相互毫無關係者，一方有為另一方之一部分或全部之變化例、詳情、補充說明等之關係。
另，在以下之實施形態中，除了言及要件之數量等(包含個數、數值、量、範圍等)之情形、特別明示之情形及原理上明確限定於特定之數量之情形等，並非限定於該特定之數量，亦可在特定之數量以上或以下。
再者，不言而喻，在以下之實施形態中，其構成要件(亦包含要件步驟)除了特別明示之情形及原理上明確認為必須之情形等，並非完全必須。
同樣，在以下之實施形態中，言及構成要件等之形狀、位置關係等時，除了特別明示之情形及原理上明確認為並非如此之情形等，實質上設為包含近似或類似該形狀等者。該點對上述數值及範圍而言亦相同。
另，在用以說明實施形態之全部圖中，對同一構件按原則標註同一符號，其重複之說明省略。此外，為使圖式易於理解，即便是俯視圖，亦有標註陰影線之情形。
(實施形態1)
<本發明者發現之課題之詳情>
在保護地球環境之社會大潮流中，降低環境負荷之電子技術事業之重要性增大。其中，電源裝置(功率半導體裝置)使用於鐵路車輛、混合動力汽車、電動汽車之變換器或空調之變換器、電腦等民生機器之電源，電源裝置之性能改善較大地有助於次系統或民生機器之電力效率改善。所謂改善電力效率，即可削減系統運轉所需要之能量資源，換言之，係二氧化碳之排放量削減，即可降低環境負荷。因此，適於電源裝置之性能改善之研究開發正在各公 司積極地進行。
一般而言，電源裝置與大規模積體電路(LSI(Large Scale Integration))同樣以矽為材料。但，近年來，比起矽，能帶隙較大之碳化矽(SiC)更受關注。SiC因能帶隙較大，故而絕緣破壞耐壓為矽的10倍左右。因此，將SiC作為材料之裝置，相較於以Si為材料之裝置，可使膜厚更薄，其結果，可使導通時之電阻值(導通電阻值)Ron大幅下降。故，以SiC為材料之裝置可使以電阻值Ron與導通電流i之積表示之導通損失(Ron×i2)大幅削減，從而可較大地有助於電力效率之改善。著眼於此類特徵，在國內外，使用SiC之MOSFET或肖特基二極體或接合FET之開發不斷進展。
特別是，當著眼於開關器件時，以SiC為材料之接合FET(JFET)之產品化迅速發展。該接合FET與以SiC為材料之MOSFET相比較，無須例如由氧化矽膜構成之閘極絕緣膜，故，可迴避以氧化矽膜與SiC之界面之缺陷、及隨之元件特性劣化為代表之問題。另，由於該接合FET可控制由pn接合所致之空乏層之延伸而控制通道之導通/斷開，故，可容易分別製作常關型之接合FET、與常開型之接合FET。如此般，以SiC為材料之接合FET與以SiC為材料之MOSFET相比較，具有長期可靠性優越且易於製作裝置之特徵。
以SiC為材料之接合FET中，常開型之接合FET，通常，通道導通而電流流動，需要斷開通道時，對閘極電極施加 負電壓而從pn接合使空乏層延伸，從而斷開通道。因此，接合FET因某些原因損壞之情形，通道會保持導通而電流繼續流動。通常，從安全性(故障自動保險)之觀點來看，期望接合FET損壞之情形時電流不流動，在常開型之接合FET中，因即便接合FET損壞之情形時電流仍繼續流動而限定用途。因此，從故障自動保險之觀點來看，期望常關型之接合FET。
但，常關型接合FET具有如下之課題。即，由於接合FET之閘極電極與源極區域各自具有由p型半導體區域(閘極電極)與n型半導體區域(源極區域)構成之pn接合二極體構造，故，閘極電極與源極區域之間的電壓一旦成為3 V左右，則閘極電極與源極區域之間的寄生二極體將導通。其結果，有閘極電極與源極區域之間流通大電流之情形，因此，有導致接合FET過度發熱之損壞之風險。因此，為將接合FET作為常關型之開關元件進行利用，期望將閘極電壓限制為2.5 V左右之低電壓，而在寄生二極體不導通之狀態、或閘極電極與源極區域之間之二極體電流充分小之狀態下進行利用。另，在以Si為材料之通常之MOSFET中，施加0至15 V或20 V左右之閘極電壓。因此，為利用常關型之接合FET，除了現有之MOSFET之閘極驅動電路以外，有必要追加產生2.5 V左右之電壓之降壓電路(DC/DC轉換器)、或位準轉換電路等。該設計變更即零件之追加會導致系統整體之成本上升。因此，雖為具有長期可靠性優越且易製作之特徵之接合FFT，但由於用以進行 驅動之閘極電壓與一般之MOSFET差別較大，故，重新利用接合FET之情形時，需要包含驅動電路等之較大之設計變更，因此，存在系統整體之成本上升之課題。
作為解決該間題之方法，有串疊連接方式。該串疊連接方式係將以SiC為材料之常開型接合FET、與以Si為材料之低耐壓MOSFET串聯連接之方式。若採用如此之連接方式，則閘極驅動電路將驅動低耐壓MOSFET，故，無需閘極驅動電路之變更。另一方面，汲極與源極間之耐壓可以絕緣耐壓較高之接合FET之特性決定。再者，即便是串疊連接之情形，由於成為接合FET之低導通電阻與低耐壓MOSFET之低導通電阻之串聯連接，故，亦可比較小地抑制串疊連接之開關元件之導通電阻。如此般，串疊連接方式有能夠解決常關型之接合FET之問題點之可能性。
圖1係顯示採用串疊連接方式之開關元件之電路構成圖。如圖1所示，採用串疊連接方式之開關元件係於源極S與汲極D間將常開型之接合FETQ1與常關型之MOSFETQ2串聯連接之構成。具體而言，於汲極D側配置接合FETQ1，於源極S側配置有MOSFETQ2。即，接合FETQ1之源極Sj與MOSFETQ2之汲極Dm連接，MOSFETQ2之汲極Sm與開關元件之源極S連接。另，接合FETQ1之閘極電極Gj與開關元件之源極S連接，MOSFETQ2之閘極電極Gm與閘極驅動電路(未圖示)連接。
另，如圖1所示，與MOSFETQ2逆向並聯連接有自由電力隔通二極體。該自由電力隔通二極體具有釋放使逆方向 電流迴流而累積成電感之能量之功能。即，圖1所示之開關元件連接於包含電感之負荷之情形，斷開開關元件後，藉由包含於負荷之電感，產生與MOSFETQ2之電流流動方向反向之反向電流。因此，藉由與MOSFETQ2逆向並列地設置自由電力隔通二極體，釋放使反向電流迴流而累積成電感之能量。
如此之連接方式係共基共射放大器連接方式，根據採用共基共射放大器連接方式之開關元件，首先，閘極驅動電路(未圖示)驅動MOSFETQ2之閘極電極Gm，故，從將MOSFET單體作為開關元件利用之情形來看，具有無需閘極驅動電路之變更之優勢。
再者，由於接合FETQ1將以比矽(Si)能帶隙更大之碳化矽(SiC)為代表之物質作為材料使用，故，接合FETQ1之絕緣耐壓較大。因此，串疊連接之開關元件之耐壓係主要以接合FETQ1之特性決定。故，可使對與接合FETQ1串聯連接之MOSFETQ2要求之絕緣耐壓低於使用MOSFET單體之開關元件。即，即便作為開關元件需要絕緣耐壓之情形，仍可使用低耐壓(例如數十V左右)之MOSFET作為MOSFETQ2。因此，可降低MOSFETQ2之導通電阻。再者，由於接合FETQ1係由常開型之接合FET構成，故，亦可降低接合FETQ1之導通電阻。其結果，根據共射共基放大器接合之開關元件，具有無需閘極驅動電路之設計變更之優勢，且可謀求兼備絕緣耐性之確保與導通電阻之降低，藉此，可謀求提高半導體元件(開關元件)之電性特性。
另，如圖1所示，串疊連接之接合FETQ1係常開型之接合FETQ1，且接合FETQ1之閘極電極Gj與開關元件之源極S電性連接。其結果，接合FETQ1之閘極電極Gj與源極S間之電壓即使在切換時(導通時)仍不會正向偏壓。因此，在串疊連接中，由接合FETQ1之寄生二極體所產生之大電流不流動，故可抑制因過度發熱引起之開關元件之損壞。即，在常關型接合FET中，於切換時(導通時)針對源極S將正電壓施加至閘極電極Gj。此時，由於接合FETQ1之源極區域係由n型半導體區域形成，且閘極電極Gj係由p型半導體區域形成，因此，針對源極S將正電壓施加至閘極電極Gj意為於源極區域與閘極電極Gj之間施加順向電壓(正向偏壓)。因此，在常關型之接合FET中，若使順向電壓過大，則會造成由源極區域與閘極電極Gj構成之寄生二極體導通。其結果，有於閘極電極Gj與源極區域之間流通大電流之情形，從而有接合FET過度發熱以至於損壞之可能性。對此，在串疊連接之開關元件中，使用常開型之接合FETQ1，且閘極電極Gj與開關元件之源極S電性連接。因此，接合FETQ1之閘極電極Gj與源極S間之電壓，即使在切換時(導通時)仍不會正向偏壓。因此，在串疊連接中，由接合FETQ1之寄生二極體所產生之大電流不流動，故可抑制因過度發熱引起之開關元件之損壞。
如此般，串疊連接之開關元件具有上述各種優勢，但，本發明者研究之結果，新發現以下所示之課題。即，本發明者新發現：為實現串疊連接，有必要將形成接合FETQ1 之半導體晶片、與形成低耐壓之MOSFETQ2之半導體晶片以接合導線連接。因此，例如，低耐壓之MOSFETQ2之汲極Dm、與接合FETQ1之源極Sj經由接合導線連接。該情形，會對接合FETQ1之源極Sj附加因接合導線所致之寄生電感。若附加如此之寄生電感，則切換時會產生較大之突波電壓，藉此，將對低耐壓之MOSFETQ2施加耐壓以上之電壓。其結果，低耐壓之MOSFETQ2在雪崩模式下進行動作，有以閘極電極Gm無法控制之大電流於低耐壓之MOSFETQ2中流動而導致元件損壞之風險。以下，關於該機制，詳細地進行說明。
<課題產生之機制>
圖2(a)係顯示將串疊連接之接合FET與MOSFET作為開關元件利用之轉換器之電路圖。圖2(a)所示之轉換器具有與電源VCC串聯連接之上機械臂與下機械臂。上機械臂係由連接於汲極D1與源極S1之間之開關元件構成。構成上機械臂之開關元件係由串疊連接之接合FETQ1a與MOSFETQ2a構成。具體而言，接合FETQ1a之汲極Dj1與開關元件之汲極D1連接，接合FETQ1a之源極Sj1與MOSFETQ2a之汲極Dm1連接。且，MOSFETQ2a之源極Sm1與開關元件之源極S1連接。又，接合FETQ1a之閘極電極Gj1與開關元件之源極S1連接，MOSFETQ2a之閘極電極Gm1、與開關元件之源極S1之間連接有閘極驅動電路(G/D)。
此處，接合FETQ1a之源極Sj1、與MOSFETQ2a之汲極Dm1之間存在基於接合導線之寄生電感Lse1，接合FETQ1a 之閘極電極Gj1、與開關元件之源極S1之間，存在基於接合導線之寄生電感Lgi1。另，在圖2(a)中，將開關元件之源極S1、與開關元件之汲極D1之間之電壓定義為電壓Vdsu，開關元件之源極S1與MOSFETQ2a之汲極Dm1之間之電壓定義為電壓Vdsmu。
同樣，如圖2(a)所示，下機械臂係由連接於汲極D2與源極S2之間之開關元件構成。構成下機械臂之開關元件係由串疊連接之接合FETQ1b與MOSFETQ2b構成。具體而言，接合FETQ1b之汲極Dj2與開關元件之汲極D2連接，接合FETQ1b之源極Sj2與MOSFETQ2b之汲極Dm2連接。且，MOSFETQ2b之源極Sm2與開關元件之源極S2連接。又，接合FETQ1b之閘極電極Gj2與開關元件之源極S2連接，MOSFETQ2b之閘極電極Gm2與開關元件之源極S2之間連接有閘極驅動電路(G/D)。再者，開關元件之源極S2、與開關元件之汲極D2之間連接有負荷電感LL。
此處，接合FETQ1b之源極Sj2、與MOSFETQ2b之汲極Dm2之間存在基於接合導線之寄生電感Lse2，接合FETQ1b之閘極電極Gj2、與開關元件之源極S2之間，存在基於接合導線之寄生電感Lgi2。另，在圖2(a)中，將開關元件之源極S2、與開關元件之汲極D2之間之電壓定義為電壓Vak，開關元件之源極S2與MOSFETQ2b之汲極Dm2之間之電壓定義為Vdsmd。
利用串疊連接之開關元件之變換器係如上述般構成，以下，一方面說明該轉換器之動作，並說明課題產生之機 制。首先，說明將構成上機械臂之開關元件接通之情形。即，說明藉由將構成上機械臂之開關元件導通，另一方面，將構成下機械臂之開關元件斷開，而將電源電壓施加至負荷(包含負荷電感)之情形。
圖2(b)係顯示將構成上機械臂之開關元件接通之情形之波形。具體而言，將構成上機械臂之開關元件接通後，構成上機械臂之接合FETQ1a及MOSFETQ2a導通，故，迴流電流以從接合FETQ1a之汲極Dj1經由MOSFETQ2a之汲極Dm1及源極Sm1，通過負荷電感LL，回到電源VCC之路徑流動。此時，如圖2(b)所示，電壓Vdsmu從特定電壓變化至0 V左右，另一方面，電壓Vak從斷開上機械臂之開關元件時之0 V上升至電源電壓程度之電壓。其結果，下機械臂之MOSFETQ2b之汲極電壓即電壓Vdsmd，上升至將下機械臂之接合FETQ1b切斷之電壓，下機械臂之接合FETQ1b斷開後，維持某個一定的電壓。該電壓Vdsmd之變化係可無視寄生電感之理想狀態之變化，係以圖2(b)之虛線表示。但，若寄生電感Lse2或寄生電感Lgi2增大，則如圖2(b)之實線所示，接通上機械臂之開關元件時，電壓Vdsmd將急劇大幅上升。
另一方面，圖2(c)係顯示將構成上機械臂之開關元件關斷之情形之波形。具體而言，若將構成上機械臂之開關元件關斷，則如圖2(c)所示，電壓Vdsmd從特定電壓變化至0 V左右，另一方面，電壓Vdsu從導通上機械臂之開關元件時之0 V上升至電源電壓程度之電壓。其結果，上機械臂 之MOSFETQ2a之汲極電壓即電壓Vdsmu，上升至切斷上機械臂之接合FETQ1a之電壓，上機械臂之接合FETQ1a斷開後，維持某個一定之電壓。該電壓Vdsmu之變化係可無視寄生電感之理想狀態之變化，係以圖2(c)之虛線表示。但，若寄生電感Lse1或寄生電感Lgi1增大，則如圖2(c)之實線所示，關斷上機械臂之開關元件時，電壓Vdsmu急劇大幅上升。
如此般，獲知：將上機械臂之開關元件接通之情形時，會產生關斷之下機械臂之MOSFETQ2b之汲極電壓即電壓Vdsmd急劇上升之現象，將上機械臂之開關元件關斷之情形時，會產生關斷之上機械臂之MOSFETQ2a之汲極電壓即電壓Vdsmu急劇上升之現象。由於產生該等現象之機制相同，以下，著眼於接通上機械臂之開關元件之情形，說明關斷之下機械臂之MOSFETQ2b之汲極電壓即電壓Vdsmd急劇上升之現象產生之機制。作為產生該現象之機制，可考慮以下所示之3個機制。
第1機制之起因在於構成下機械臂之接合FETQ1b之源極Sj2、與構成下機械臂之MOSFETQ2b之汲極Dm2之間存在之寄生電感Lse2。具體而言，接通上機械臂之開關元件時，下機械臂之MOSFETQ2b被斷開。此時，電壓Vak從0 V左右開始增加，隨著該電壓Vak之增加，下機械臂之MOSFETQ2b之汲極電壓即電壓Vdsmd亦開始增加。但，在電壓Vdsmd增加之初期階段，電壓Vdsmd相比施加至接合FETQ1b之閘極電極Gj2之閘極電壓，未增大至特定值以 上，故，接合FETQ1b不會被切斷，電流從接合FETQ1b之汲極Dj2流向源極Sj2。其結果，電流流入MOSFETQ2b之汲極Dm2，從而累積電荷。因此，MOSFETQ2b之汲極電壓即電壓Vdsmd上升。且，當該電壓Vdsmd持續上升，而相比接合FETQ1b之閘極電壓增大至特定值以上時，接合FETQ1b被切斷，而其以上電流不再流動。即，在電壓Vdsmd增加之初期階段，電流流動於接合FETQ1b之汲極Dj2與源極Sj2之間，而於MOSFETQ2b之汲極Dm2中累積電荷，故，電壓Vdsmd增加。其後，隨著電壓Vdsmd增加，電壓Vdsmd接近相比接合FETQ1b之閘極電壓成為特定值以上之大小之狀態，故，流動於接合FETQ1b之汲極Dj2與源極Sj2中之電流逐漸減少。且，最終，電壓Vdsmd相較於接合FETQ1b之閘極電壓，增大為特定值以上，藉此，接合FETQ1b被切斷。接合FETQ1b被切斷後，由於流入MOSFETQ2b之汲極Dm2中之電荷消失，故，電壓Vdsmd將大致一定。
如此般，接通上機械臂之開關元件時，下機械臂之MOSFETQ2b斷開，但，在該階段，下機械臂之接合FETQ1b不會立即切斷，電流從接合FETQ1b之汲極Dj2流動至源極Sj2。接著，流入接合FETQ1b之汲極Sj2中之電流經由寄生電感Lse2，流入MOSFETQ2b之汲極Dm2。此時，應著眼之點係從下機械臂之接合FETQ1b之汲極Dj2流動至源極Sj2之電流減少此點。該點意味著流向寄生電感Lse2之電流亦隨著時間減少。其結果，在寄生電感Lse2 中，會產生消除電流之減少之電動勢。即，寄生電感Lse2係以使從接合FETQ1b之汲極Dj2流向源極Sj2之電流增加之方式發揮功能。因此，若寄生電感Lse2增大，則會過渡性地從接合FETQ1b之汲極Dj2向源極Sj2流動較大之電流。其結果，流入MOSFETQ2b之汲極Dm2中之電荷急劇增加，藉此，電壓Vdsmd急劇增加。以上為第1機制。
繼而，第2機制係起因於構成下機械臂之接合FETQ1b之閘極電極Gj2、與下機械臂之源極S2之間存在之寄生電感Lgi2。具體而言，接通上機械臂之開關元件時，下機械臂之MOSFETQ2b斷開。此時，電壓Vak從0V左右開始增加，例如圖2(b)所示，在接通上機械臂之開關元件之初期階段，電壓Vak振動至超過電源電壓之範圍。此係基於由連接於變換器之負荷所含之負荷電感LL引起之反電動勢者。因此，電壓Vak在接通上機械臂時之初期階段會變動。此處，若著眼於接合FETQ1b，則接合FETQ1b之汲極Dj2與閘極電極Gj2之間形成有寄生電容，且若電壓Vak變動，則施加於該寄生電容之電壓亦變動。且，由於該寄生電容之靜電電容值成為比較大之值，故，隨著施加於寄生電容之電壓變動而產生之充放電電流亦變大。該充放電電流流通接合FETQ1b之閘極電極Gj2與下機械臂之源極S2之間。此時，充放電電流係隨時間而變化之電流。因此，例如，若接合FETQ1b之閘極電極Gj2與下機械臂之源極S2之間存在寄生電感Lgi2，則隨時間而變化之充放電電流流通寄生電感Lgi2，故，與寄生電感Lgi2之大小與充放電電流 之時間微分之積成比例之電阻成分產生於接合FETQ1b之閘極電極Gj2與下機械臂之源極S2之間。其結果，接合FETQ1b之閘極電極Gj2與下機械臂之源極S2不會成為同電位，而產生接合FETQ1b之閘極電極Gj2相對下機械臂之源極S2於正電壓方向上升之模式。該情形時，接合FETQ1b之閘極電極Gj2成為正電壓，故，可抑制從接合FETQ1b之閘極電極Gj2延伸之空乏層，從而通道區域之寬度變大。因此，從接合FETQ1b之汲極Dj2向源極Sj2流動之電流過渡性地變大。其結果，流入MOSFETQ2b之汲極Dm2之電荷急劇增加，藉此，電壓Vdsmd急劇增加。以上為第2機制。再者，根據第2機制，因對接合FETQ1b之閘極電極Gj2施加正電壓，為切斷接合FETQ1b，必須對接合FETQ1b之源極Sj2施加相比對閘極電極Gj2施加0 V之情形更大之電壓。從該觀點來看，切斷接合FETQ1b之前上升之電壓Vdsmd會變大。
再者，第3機制係起因於構成下機械臂之接合FETQ1b之閘極電極Gj2、與下機械臂之源極S2之間存在之寄生電阻。如第2機制所說明般，接合FETQ1b之閘極電極Gj2與下機械臂之源極S2之間流動充放電電流。因此，若接合FETQ1b之閘極電極Gj2、與下機械臂之源極S2之間存在寄生電阻，則充放電電流流動於該寄生電阻，而產生電壓下降。其結果，接合FETQ1b之閘極電極Gj2與下機械臂之源極S2不會成為同電位，而產生接合FETQ1b之閘極電極Gj2相對下機械臂之源極S2於正電壓方向上升之模式。因此， 在第3機制中，亦與第2機制相同，接合FETQ1b之閘極電極Gj2成為正電壓，故，可抑制從接合FETQ1b之閘極電極Gj2延伸之空乏層，從而通道區域之寬度變大。因此，從接合FETQ1b之汲極Dj2向源極Sj2流動之電流過渡性變大。其結果，流入MOSFETQ2b之汲極Dm2之電荷急劇增加，藉此，電壓Vdsmd急劇增加。
如以上般，獲知因與寄生電感Lse2、寄生電感Lgi2及寄生電阻相關之第1機制至第3機制，電壓Vdsmd急劇增加。如此般，若寄生電感Lse2、寄生電感Lgi2及寄生電阻變大，則下機械臂之MOSFETQ2b之汲極電壓即電壓Vdsmd將上升至MOSFETQ2b之耐壓以上之電壓，藉此，下機械臂之MOSFETQ2b將突崩動作，最終，有下機械臂之MOSFETQ2b被破壞之風險。
具體而言，若對MOSFETQ2b施加耐壓以上之電壓，則於MOSFETQ2b之內部會局部產生電場集中之區域，且在該區域中由碰撞離子化而引起之電洞電子對將大量產生。藉由該大量產生之電洞電子對，由源極區域(n型半導體區域)、通道形成區域(p型半導體區域)及漂移區域(n型半導體區域)所形成之寄生npn雙極電晶體導通。在寄生npn雙極電晶體導通之電池(MOSFETQ2b)中，以MOSFETQ2b之閘極電極Gm2無法控制之大電流流動從而發熱。此時，因由發熱所致之溫度上升而半導體區域之電性電阻變小，故，產生更大之電流流動之正反饋。其結果，大電流局部性流動，而發生MOSFETQ2b之損壞。該現象係突崩破 壞。若發生此類突崩破壞，則會招致半導體裝置之可靠性下降。
因此，在本實施形態1中，為抑制成為突崩破壞原因之對MOSFET施加超過絕緣耐壓之電壓，實施降低寄生電感及寄生電阻之方法。以下，說明實施該方法之本實施形態1之技術思想。在本實施形態1中，特徵在於對半導體裝置之安裝構成下功夫之點，且針對包含該特徵點之半導體裝置之安裝構成進行說明。
<本實施形態1之半導體裝置之安裝構成>
圖3係顯示本實施形態1之封裝(半導體裝置)PKG1之安裝構成圖。如圖3所示，本實施形態1之封裝PKG1具有相互電性絕緣之2個晶片搭載部PLT1與晶片搭載部PLT2。在圖3中，配置於右側之金屬板構成晶片搭載部PLT1，配置於左側之金屬板構成晶片搭載部PLT2。晶片搭載部PLT1係以與汲極引線DL連結之方式一體化形成，且晶片搭載部PLT1與汲極引線DL電性連接。再者，以分離包夾該汲極引線DL之方式，配置有源極引線SL與閘極引線GL。具體而言，如圖3所示，於汲極引線DL之右側配置有源極引線SL，於汲極引線DL之左側配置有閘極引線GL。該等汲極引線DL、源極引線SL、及閘極引線GL係互相電性絕緣。且，於源極引線SL之前端部中，形成有包含寬廣區域之源極引線接線柱部SPST，於閘極引線GL之前端部中，形成有包含寬廣區域之閘極引線接線柱部GPST。
再者，於晶片搭載部PLT1上，例如介隔包含銀漿或焊錫 之導電性接著材料，而搭載有半導體晶片CHP1。於該半導體晶片CHP1上，例如形成有以SiC為材料之接合FET。且，半導體晶片CHP1之背面成為汲極電極，且於半導體晶片CHP1之表面(主面)上形成有源極焊墊SPj與閘極焊墊GPj。即，於半導體晶片CHP1上，形成有構成串疊連接方式之開關元件之一部分之接合FET，於半導體晶片CHP1之背面形成有與該接合FET之汲極電性連接之汲極電極，於半導體晶片CHP1之表面形成有與接合FET之源極電性連接之源極焊墊SPj、及與接合FET之閘極電極電性連接之閘極焊墊GPj。
繼而，於晶片搭載部PLT2上，例如介隔包含銀漿或焊錫之導電性接著材料，而搭載有半導體晶片CHP2。於該半導體晶片CHP2上，例如形成有以Si作為材料之MOSFET。此時，半導體晶片CHP2之背面成為汲極電極，於半導體晶片CHP1之表面(主面)上形成有源極焊墊SPm與閘極焊墊GPm。即，於半導體晶片CHP2上，形成有構成串疊連接方式之開關元件之一部分之MOSFET，且於半導體晶片CHP2之背面形成有與該MOSFET之汲極電性連接之汲極電極，於半導體晶片CHP2之表面形成有與MOSFET之源極電性連接之源極焊墊SPm、及與MOSFET之閘極電極電性連接之閘極焊墊GPm。
再者，藉由將晶片搭載部PLT1上所搭載之半導體晶片CHP1、與晶片搭載部PLT2上所搭載之半導體晶片CHP2以接合導線連接，可構成串疊連接之開關元件。具體而言， 如圖3所示，形成於半導體晶片CHP1之表面之閘極焊墊GPj、與形成於源極引線SL之前端部之源極引線接線柱部SPST以導線Wgj電性連接。又，形成於半導體晶片CHP1之表面之源極焊墊SPj、與晶片搭載部PLT2以導線Wds電性連接。再者，形成於半導體晶片CHP2之表面之源極焊墊SPm、與形成於源極引線SL之前端部之源極引線接線柱部SPST以導線Wsm電性連接。此外，形成於半導體晶片CHP2之表面之閘極焊墊GPm、與形成於閘極引線GL之前端部之閘極引線接線柱部GPST以導線Wgm電性連接。此處，源極引線接線柱部SPST之連接有導線Wgj及導線Wsm之區域、與閘極引線接線柱部GPST之連接有導線Wgm之區域，係以位於比晶片搭載部PLT1之上表面或晶片搭載部PLT2之上表面更高之位置之方式構成。
另，因半導體晶片CHP1介隔導電性接著材料而搭載於晶片搭載部PLT1上，故形成於半導體晶片CHP1之背面之汲極電極與晶片搭載部PLT1電性連接。此外，半導體晶片CHP2係介隔導電性接著材料而搭載於晶片搭載部PLT2上，故形成於半導體晶片CHP2之背面之汲極電極與晶片搭載部PLT2電性連接。
在如此般構成之封裝PKG1中，至少以密封體密封半導體晶片CHP1、半導體晶片CHP2、晶片搭載部PLT1之一部分、晶片搭載部PLT2之一部分、汲極引線DL之一部分、源極引線SL之一部分、閘極引線GL之一部分、及導線Wgj、Wds、Wgm、Wsm。因此，藉由於晶片搭載部PLT1 與晶片搭載部PLT2之間配置有密封體之一部分，藉此，晶片搭載部PLT1與晶片搭載部PLT2藉由密封體而電性絕緣。另，晶片搭載部PLT1之下表面、及晶片搭載部PLT2之下表面亦可以從密封體露出之方式構成。該情形時，可使半導體晶片CHP1或半導體晶片CHP2所產生之熱從晶片搭載部PLT1之下表面或晶片搭載部PLT2之下表面有效散熱。
該密封體係例如呈長方體形狀，且具有第1側面、及與該第1側面對向之第2側面。該情形時，例如從密封體之第1側面，汲極引線DL之一部分、源極引線SL之一部分、及閘極引線GL之一部分突出。該等突出之汲極引線DL之一部分、源極引線SL之一部分、及閘極引線GL之一部分將作為外部連接端子發揮功能。
此處，在串疊連接之開關元件中，由於搭載半導體晶片CHP1與半導體晶片CHP2此2個半導體晶片，故，無法將封裝內只具有1個晶片搭載部之現有之通用封裝照搬挪用。例如亦考慮在數A以上之較大額定電流下之使用，形成於半導體晶片CHP1之接合FET、或形成於半導體晶片CHP2之MOSFET，採用所謂於半導體晶片之背面具有汲極電極之縱型構造。該情形時，在串疊連接方式之開關元件中，形成於半導體晶片CHP1之背面之汲極電極、與形成於半導體晶片CHP2之背面之汲極電極無法電性連接。因此，在封裝內只具有1個晶片搭載部之現有之通用封裝中，若於該1個晶片搭載部中配置半導體晶片CHP1與半導體晶片 CHP2，則無法實現將形成於半導體晶片CHP1之背面之汲極電極、與形成於半導體晶片CHP2之背面之汲極電極電性連接之串疊連接方式。
因此，在本實施形態1中，如圖3所示，將外形形狀與通用封裝同等之點作為前提，以於密封體之內部設置相互電性絕緣之2個之晶片搭載部PLT1及晶片搭載部PLT2之方式構成封裝PKG1。接著，以於晶片搭載部PLT1上搭載半導體晶片CHP1且於晶片搭載部PLT2上搭載半導體晶片CHP2之方式構成封裝PKG1。即，將電性絕緣之2個之晶片搭載部PLT1及晶片搭載部PLT2設置於封裝PKG1內，且將半導體晶片CHP1與半導體晶片CHP2平面性地配置，並將經平面性配置之半導體晶片CHP1與半導體晶片CHP2以導線連接，藉此實現串疊連接。
因此，根據本實施形態1之封裝PKG1，例如，可將安裝利用於電源電路等之開關元件之現有之通用封裝替換成外形尺寸同等之本實施形態1之封裝PKG1。特別是，根據本實施形態1之封裝PKG1，汲極引線DL、源極引線SL、及閘極引線GL之配置與通用封裝相同，故，可將通用封裝替換為本實施形態1之封裝PKG1，而無需設計變更其他驅動電路或印刷基板之配線等。因此，根據本實施形態1，容易從利用通用封裝之開關元件，變更為利用本實施形態1之封裝PKG1之高性能之串疊連接方式之開關元件，具有無需進行大幅之設計變更而可提供高性能之電源系統之優勢。
以下，說明本實施形態1之封裝PKG1之特徵點。首先，本實施形態1之第1特徵點係如圖3所示般，以使設置於形成接合FET之半導體晶片CHP1之表面之閘極焊墊GPj、與源極引線SL儘可能靠近之方式配置之點。具體而言，在本實施形態1中，將搭載半導體晶片CHP1之晶片搭載部PLT1，配置於與相對汲極引線DL配置有源極引線SL之側相同側。藉此，可使晶片搭載部PTL1靠近源極引線SL。該點意味著可將晶片搭載部PTL1上所搭載之半導體晶片CHP1以靠近源極引線SL之方式配置。且，在本實施形態1中，並非將晶片搭載部PLT1上所搭載之半導體晶片CHP1配置於晶片搭載部PLT1之中央部，而是將半導體晶片CHP1以向最靠近晶片搭載部PLT1之源極引線SL之邊靠近之方式配置。藉此，可將半導體晶片CHP1以最靠近源極引線SL之方式配置。再者，在本實施形態1中，將半導體晶片CHP1以儘可能靠近源極引線SL之方式配置，且以使形成於半導體晶片CHP1之表面之閘極焊墊GPj靠近源極引線SL之方式進行配置。如此般，在本實施形態1中，首先，將搭載形成有接合FET之半導體晶片CHP1之晶片搭載部PLT1配置於靠近源極引線SL之位置，進而，於晶片搭載部PLT1內之內部區域中、靠近源極引線SL之區域中，搭載有半導體晶片CHP1。在此基礎上，本實施形態1中，以使形成於半導體晶片CHP1之表面之閘極焊墊GPj靠近源極引線SL之方式，配置有閘極焊墊GPj。藉此，形成於半導體晶片CHP1之表面之閘極焊墊GPj、與源極引線SL靠 近。換言之，在本實施形態1中，形成於半導體晶片CHP1之表面之閘極焊墊GPj以相比其他引線(汲極引線DL或閘極引線GL)更靠近源極引線SL之方式配置。其結果，根據本實施形態1，由於可縮短閘極焊墊GPj與源極引線SL間之距離，故可縮短連接閘極焊墊GPj與源極引線SL之導線Wgj之長度。特別是，在本實施形態1中，採取以源極引線SL中、靠近閘極焊墊GPj之前端部中存在之寬廣之源極引線接線柱部SPST連接導線Wgj之構成，故，進而可縮短導線Wgj之長度。可縮短導線Wgj之長度，意為可降低導線Wgj中存在之寄生電感(圖2之Lgi1或Lgi2)。即，根據本實施形態1，可充分降低導線Wgj中存在之寄生電感。因此，可抑制由上述之第2機制引起之對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本實施形態1，可謀求半導體裝置之可靠性提高。
繼而，說明本實施形態1之第2特徵點。本實施形態1之第2特徵點係如圖3所示般，將設置於形成MOSFET之半導體晶片CHP2之表面之閘極焊墊GPm、與閘極引線GL以儘可能靠近之方式配置之點。具體而言，在本實施形態1中，將搭載半導體晶片CHP2之晶片搭載部PLT2配置於與相對汲極引線DL配置有閘極引線GL之側相同之側。藉此，可使晶片搭載部PLT2靠近閘極引線GL。該點意味著可將搭載於晶片搭載部PLT2上之半導體晶片CHP2以靠近閘極引線GL之方式配置。且，在本實施形態1中，並非將 搭載於晶片搭載部PLT2上之半導體晶片CHP2配置於晶片搭載部PLT2之中央部，而是將半導體晶片CHP2以向最靠近晶片搭載部PLT2之閘極引線GL之邊靠近之方式配置。藉此，可將半導體晶片CHP2以最靠近閘極引線GL之方式配置。進而，在本實施形態1中，將半導體晶片CHP2以儘可能靠近閘極引線GL之方式配置，且以使形成於半導體晶片CHP2之表面之閘極焊墊GPm靠近閘極引線GL之方式進行配置。如此般，在本實施形態1中，首先，將搭載形成有MOSFET之半導體晶片CHP2之晶片搭載部PLT2配置於靠近閘極引線GL之位置，進而於晶片搭載部PLT2內之內部區域中、靠近閘極引線GL之區域搭載有半導體晶片CHP2。在此基礎上，本實施形態1中，以使形成於半導體晶片CHP2之表面之閘極焊墊GPm靠近閘極引線GL之方式配置有閘極焊墊GPm。藉此，形成於半導體晶片CHP2之表面之閘極焊墊GPm、與閘極引線GL靠近。換言之，在本實施形態1中，形成於半導體晶片CHP2之表面之閘極焊墊GPm以相較於其他引線(汲極引線DL或源極引線SL)更靠近閘極引線GL之方式配置。其結果，根據本實施形態1，由於可縮短閘極焊墊GPm與閘極引線GL間之距離，故可縮短連接閘極焊墊GPm與閘極引線GL之導線Wgm之長度。特別是，在本實施形態1中，由於採取以閘極引線GL之中、靠近閘極焊墊GPm之前端部中存在之寬廣之閘極引線接線柱部GPST連接導線Wgm之構成，故，進而可縮短導線Wgm之長度。藉此，根據本實施形態1，可降低導線Wgm 之寄生電感。可降低該導線Wgm之寄生電感，雖有助於串疊連接之開關元件之電性特性之提高，但與抑制對MOSFET施加超過絕緣耐壓之電壓無直接關聯。根據本實施形態1之第2特徵點之構成，並非直接而是間接地可抑制對MOSFET施加超過絕緣耐壓之電壓。
以下，關於該點進行說明。如圖3所示，本實施形態1之第2特徵點係將形成有MOSFET之半導體晶片CHP2以儘可能靠近閘極引線GL之方式配置之點。該點係如圖3所示，意為偏向晶片搭載部PLT2之近前側而配置半導體晶片CHP2，換言之，意為可於晶片搭載部PLT2之內側出現未搭載半導體晶片CHP2之較大之空間。如此般，在本實施形態1中，間接之特徵在於可於晶片搭載部PLT2中確保未搭載半導體晶片CHP2之較大之空間。具體而言，根據該特徵，如圖3所示，可充分確保將搭載於晶片搭載部PLT1上之半導體晶片CHP1之表面上所形成之源極焊墊SPj、與晶片搭載部PLT2電性連接之導線連接區域。其結果，如圖3所示，可將源極焊墊SPj與晶片搭載部PLT2以複數條導線Wds連接。此處，由於晶片搭載部PLT2與形成於所搭載之半導體晶片CHP2之背面之汲極電極電性連接，故，根據本實施形態1，利用複數條導線Wds，連接MOSFET之汲極與接合FET之源極。該點意味著能夠降低連接MOSFET之汲極與接合FET之源極之導線Wds之寄生電感(圖2之Lse1、Lse2)。即，根據本實施形態1，藉由使用複數條之導線Wds，能夠充分降低MOSFET之汲極與接合FET之源 極間之寄生電感。
再者，如圖3所示，期望將形成於半導體晶片CHP1之表面之源極焊墊SPj之形成位置以儘量靠近晶片搭載部PLT2之方式配置。其理由，藉由將源極焊墊SPj以如此之方式配置，可儘可能地將連接源極焊墊SPj與晶片搭載部PLT2之導線Wds之長度縮短。藉此亦可降低連接MOSFET之汲極與接合FET之源極之導線Wds之寄生電感(圖2之Lse1、Lse2)。
基於以上之點，根據本實施形態1之第2特徵點，可抑制由上述之第1機制引起之對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本實施形態1，可謀求提高半導體裝置之可靠性。
另，在本實施形態1中，如圖3所示，閘極焊墊GPj係藉由導線Wgj與源極引線SL電性連接，且，閘極焊墊GPm係藉由導線Wgm與閘極引線GL電性連接。此時，期望導線Wgj之粗細(寬度)比導線Wgm之粗細(寬度)更粗地構成。其理由，若存在於導線Wgj中之寄生電阻較大，則基於第3機制，會造成對MOSFET施加絕緣耐壓以上之電壓。因此，從降低存在於導線Wgj中之寄生電阻之觀點來看，期望採取使導線Wgj之粗細比其他導線更粗之構成。藉此，由於可降低接合FET之閘極電極與開關元件之源極(亦可稱為MOSFET之源極)間之寄生電阻，故可抑制由上述之第3機制引起之對MOSFET施加超過絕緣耐壓之電壓，藉此，可 有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本實施形態1，可謀求提高半導體裝置之可靠性。
接著，說明本實施形態1之第3特徵點。本實施形態1之第3特徵點係如圖3所示般，將設置於形成MOSFET之半導體晶片CHP2之表面之源極焊墊SPm、與源極引線SL(源極引線接線柱部SPST)以複數條導線Wsm連接之點。藉此，可降低MOSFET之源極與源極引線SL之間之寄生電阻及寄生電感。其結果，可抑制MOSFET之源極之電位從自源極引線SL供給之GND電位(基準電位)變動，而可使MOSFET之源極確實固定於GND電位。進而，由於可降低MOSFET之源極與源極引線SL之間之寄生電阻，故，亦可降低串疊連接之開關元件之導通電阻。如此般，根據本實施形態1之第3特徵點，可謀求提高形成於封裝PKG1中之串疊連接之開關元件之電性特性。
如以上般，根據本實施形態1之封裝PKG1(半導體裝置)，藉由具備上述之第1特徵點與第2特徵點，可抑制對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，可謀求提高半導體裝置之可靠性。進而，本實施形態1之封裝PKG1(半導體裝置)藉由具備上述之第3特徵點，亦可謀求降低寄生電阻及寄生電感，故，可謀求提高半導體裝置之電性特性。
另，作為本實施形態1之封裝PKG1所帶來之具體效果，本實施形態1之封裝PKG1係採用將形成接合FET之半導體晶片CHP1、與形成MOSFET之半導體晶片CHP2平面性地 配置之構成，故，可自由設計半導體晶片CHP1或半導體晶片CHP2之晶片面積。因此，低導通電阻之設計或導通電流密度之設計亦較容易，從而可實現各種樣式之開關元件。
繼而，說明本實施形態1之開關元件之其他安裝形態之一例。圖4係顯示本實施形態1之封裝PKG2之安裝構成圖。圖4所示之封裝PKG2、與圖3所示之封裝PKG1之不同點係源極引線SL與汲極引線DL之形成位置不同之點。具體而言，在圖3所示之封裝PKG1中，於最左側配置有閘極引線GL，於正中間配置有汲極引線DL，於最右側配置有源極引線SL。與此相對，在如圖4所示之封裝PKG2中，於最左側配置有閘極引線GL，於正中間配置有源極引線SL，於最右側配置有汲極引線DL。該情形時，如圖4所示，隨著源極引線SL之配置位置變更，形成於半導體晶片CHP1之表面之閘極焊墊GPj之形成位置亦以相較於其他引線更靠近源極引線SL之方式變更。其結果，在圖4所示之封裝PKG2中，亦可縮短閘極焊墊GPj與源極引線SL之間之距離。因此，可縮短連接閘極焊墊GPj與源極引線SL之導線Wgj之長度。即，在圖4所示之封裝PKG2中，亦可充分降低存在於導線Wgj中之寄生電感。因此，可抑制由上述第2機制引起之對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，在圖4所示之封裝PKG2中，亦可謀求提高半導體裝置之可靠性。
再者，作為圖4所示之封裝PKG2所特有之特徵點係，與圖3所示之封裝PKG1相比，可充分縮短將形成於半導體晶片CHP2之表面之源極焊墊SPm、與源極引線SL電性連接之導線Wsm之長度之點。因此，根據圖4所示之封裝PKG2，由於可降低導線Wsm之寄生電阻及寄生電感，故可提高本實施形態1之開關元件之電性特性。特別是，由縮短導線Wsm之長度而引起之效果在縮小本實施形態1之開關元件之導通電阻之點上顯著。
<變化例1>
接著，說明本變化例1之封裝PKG3之安裝構成。在本變化例1中，關於將形成有接合FET之半導體晶片、與形成有MOSFET之半導體晶片疊層之構成。
圖5係顯示本變化例1之封裝PKG3之安裝構成圖。在圖3中，本變化例1之封裝PKG3具有例如包含成矩形形狀之金屬板之晶片搭載部PLT。該晶片搭載部PLT係以與汲極引線DL連結之方式一體化形成，且晶片搭載部PLT與汲極引線DL電性連接。接著，以將該汲極引線DL分離包夾之方式配置有源極引線SL與閘極引線GL。具體而言，如圖5所示，於汲極引線DL之右側配置有源極引線SL，於汲極引線DL之左側配置有閘極引線GL。該等汲極引線DL、源極引線SL、及閘極引線GL互相電性絕緣。且，於源極引線SL之前端部中，形成有包含寬廣區域之源極引線接線柱部SPST，於閘極引線GL之前端部中，形成有包含寬廣區域之閘極引線接線柱部GPST。
接著，於晶片搭載部PLT上，介隔例如包含銀漿或焊錫之導電性接著材料，而搭載有半導體晶片CHP1。於該半導體晶片CHP1中，例如形成有以SiC為材料之接合FET。且，半導體晶片CHP1之背面成為汲極電極，且於半導體晶片CHP1之表面(主面)中形成有源極焊墊SPj與閘極焊墊GPj。即，半導體晶片CHP1中，形成有構成串疊連接方式之開關元件之一部分之接合FET，且於半導體晶片CHP1之背面形成有與該接合FET之汲極電性連接之汲極電極，於半導體晶片CHP1之表面形成有與接合FET之源極電性連接之源極焊墊SPj、及與接合FET之閘極電極電性連接之閘極焊墊GPj。
接著，於該半導體晶片CHP1上，介隔例如包含銀漿或焊錫之導電性接著材料，而搭載有半導體晶片CHP2。於該半導體晶片CHP2中，形成有例如以Si為材料之MOSFET。此時，半導體晶片CHP2之背面成為汲極電極，且半導體晶片CHP1之表面(主面)中形成有源極焊墊SPm與閘極焊墊GPm。即，半導體晶片CHP2中，形成有構成串疊連接方式之開關元件之一部分之MOSFET，且於半導體晶片CHP2之背面形成有與該MOSFET之汲極電性連接之汲極電極，於半導體晶片CHP2之表面形成有與MOSFET之源極電性連接之源極焊墊SPm、及與MOSFET之閘極電極電性連接之閘極焊墊GPm。
如此般，在本變化例1中，半導體晶片CHP1上搭載有半導體晶片CHP2，特別是，形成於半導體晶片CHP1之表面 之源極焊墊SPj上搭載有半導體晶片CHP2。藉此，將形成於半導體晶片CHP2之背面之汲極電極、與形成於半導體晶片CHP1之表面之源極焊墊SPj電性連接。其結果，形成於半導體晶片CHP1上之接合FET之源極、與形成於半導體晶片CHP2上之MOSFET之汲極電性連接。因此，半導體晶片CHP2有必要在俯視下，以內包於形成於半導體晶片CHP1之表面之源極焊墊SPj之方式形成。即，在本變化例1中，半導體晶片CHP2之尺寸有必要比半導體晶片CHP1之尺寸更小，進而言之，半導體晶片CHP2之尺寸有必要比源極焊墊SPj之尺寸更小。
接著，如圖5所示，將形成於半導體晶片CHP1之表面之閘極焊墊GPj、與形成於源極引線SL之前端部之源極引線接線柱部SPST以導線Wgj電性連接。且，將形成於半導體晶片CHP2之表面之源極焊墊SPm、與形成於源極引線SL之前端部之源極引線接線柱部SPST以導線Wsm電性連接。又，將形成於半導體晶片CHP2之表面之閘極焊墊GPm、與形成於閘極引線GL之前端部之閘極引線接線柱部GPST以導線Wgm電性連接。此處，源極引線接線柱部SPST之連接有導線Wgj及導線Wsm之區域、與閘極引線接線柱部GPST之連接有導線Wgm之區域係以位於比晶片搭載部PLT1之上表面或晶片搭載部PLT2之上表面更高之位置之方式構成。
在如此般構成之封裝PKG3中，至少以密封體密封半導體晶片CHP1、半導體晶片CHP2、晶片搭載部PLT之一部 分、汲極引線DL之一部分、源極引線SL之一部分、閘極引線GL之一部分、及導線Wgj、Wgm、Wsm。另，晶片搭載部PLT之下表面亦可以從密封體露出之方式構成。該情形時，可使半導體晶片CHP1或半導體晶片CHP2所產生之熱從晶片搭載部PLT之下表面有效散熱。
該密封體係例如呈長方體形狀，且具有第1側面、及與該第1側面對向之第2側面。該情形時，例如從密封體之第1側面，汲極引線DL之一部分、源極引線SL之一部分、及閘極引線GL之一部分突出。該等突出之汲極引線DL之一部分、源極引線SL之一部分、及閘極引線GL之一部分將作為外部連接端子發揮功能。
本變化例1之封裝PKG3係如上述般構成，以下，說明本變化例1之封裝PKG3之特徵點。首先，本變化例1之特徵點係如圖5所示般，以使設置於形成有接合FET之半導體晶片CHP1之表面上之閘極焊墊GPj、與源極引線SL儘可能靠近之方式進行配置之點。具體而言，在本變化例1中，將半導體晶片CHP1配置於與相對汲極引線DL而配置有源極引線SL之側相同之側。即，半導體晶片CHP1係相對圖5所示之中心線a-a'偏向右側而配置。藉此，可使半導體晶片CHP1靠近源極引線SL。且，在本變化例1中，並非將半導體晶片CHP1配置於晶片搭載部PLT之中央部，而是以向最靠近晶片搭載部PLT之源極引線SL之邊靠近之方式配置半導體晶片CHP1。即，半導體晶片CHP1係相對圖5所示之中心線b-b'偏向近前側(下側)而配置。藉此，可將半導體晶 片CHP1以最靠近源極引線SL之方式配置。換言之，在本變化例1中，形成於半導體晶片CHP1之表面之閘極焊墊GPj以相較於其他引線(汲極引線DL或閘極引線GL)更靠近源極引線SL之方式配置。其結果，根據本變化例1，由於可縮短閘極焊墊GPj與源極引線SL之間之距離，故可縮短連接閘極焊墊GPj與源極引線SL之導線Wgj之長度。特別是，在本變化例1中，由於採取以源極引線SL中、靠近閘極焊墊GPj之前端部中存在之寬廣之源極引線接線柱部SPST連接導線Wgj之構成，故，進而可縮短導線Wgj之長度。縮短導線Wgj之長度，意為可降低存在於導線Wgj中之寄生電感(圖2之Lgi1或Lgi2)。即，根據本變化例1，可充分降低存在於導線Wgj中之寄生電感。因此，可抑制由上述第2機制引起之對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本變化例1，可謀求提高半導體裝置之可靠性。
此處，從縮短連接閘極焊墊GPj與源極引線SL之導線Wgj之長度觀點來看，可考慮於最靠近半導體晶片CHP1之源極引線SL之邊側，將閘極焊墊GPj偏向配置。但，在本變形例1中，如圖5所示，以沿著半導體晶片CHP1之右邊側且相對右邊中央部成為對稱之方式配置有閘極焊墊GPj。其係根據以下所示之理由。即，閘極焊墊GPj係藉由形成於半導體晶片CHP1之內部之複數個接合FET之各閘極電極與閘極配線連接。因此，例如藉由將閘極焊墊GPj以 相對右邊中央部成為對稱之方式配置，可抑制連接複數個接合FET之各閘極電極與閘極焊墊GPj之閘極配線之距離之偏差。該點意為可統一形成於半導體晶片CHP1內之複數個接合FET之特性而進行利用。根據如此之理由，在本變化例1中，以相對半導體晶片CHP1之右邊中央部成為對稱之方式配置有閘極焊墊GPj。
另，在本變化例1中，如圖5所示，閘極焊墊GPj係藉由導線Wgj，與源極引線SL電性連接，且閘極焊墊GPm係藉由導線Wgm與閘極引線GL電性連接。此時，期望導線Wgj之粗細(寬度)比導線Wgm之粗細(寬度)更粗地構成。其理由，若存在於導線Wgj中之寄生電阻較大，則根據第3機制，會造成對MOSFET施加絕緣耐壓以上之電壓。因此，從降低存在於導線Wgj中之寄生電阻之觀點來看，期望採取使導線Wgj之粗細比其他導線更粗之構成。藉此，由於可降低接合FET之閘極電極與開關元件之源極(亦可稱為MOSFET之源極)間之寄生電阻，因此，可抑制由上述之第3機制引起之對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本變化例1，可謀求提高半導體裝置之可靠性。
接著，進一步說明本變化例1之特徵點。本變化例1進一步之特徵點係如圖5所示般，將設置於形成有MOSFET之半導體晶片CHP2之表面上之源極焊墊SPm、與源極引線SL(源極引線接線柱部SPST)以複數條導線Wsm連接之點。藉此，可降低MOSFET之源極與源極引線SL之間之寄生電 阻及寄生電感。其結果，可抑制MOSFET之源極之電位從自源極引線SL供給之GND電位(基準電位)變動，從而可將MOSFET之源極確實固定於GND電位。進而，由於可降低MOSFET之源極與源極引線SL之間之寄生電阻，故亦可降低串疊連接之開關元件之導通電阻。如此般，根據本變化例1之進一步之特徵點，可謀求提高形成於封裝PKG3中之串疊連接之開關元件之電性特性。
接著，說明本變化例1所特有之特徵點。本變化例1所特有之特徵點係如圖5所示般，於形成有接合FET之半導體晶片CHP1上搭載有形成有MOSFET之半導體晶片CHP2之點。藉此，可將形成於半導體晶片CHP1之表面之源極焊墊SPj、與形成於半導體晶片CHP2之背面之汲極電極直接連接。即，根據本變化例1，可不使用導線而直接連接接合FET之源極、與MOSFET之汲極。該點意為可大致完全消除介存於接合FET之源極、與MOSFET之汲極之間之寄生電感。即，本變化例1所特有之特徵點係半導體晶片CHP1上直接搭載有半導體晶片CHP2之點，藉由該構成，連接接合FET之源極、與MOSFET之汲極而無需導線。使用導線之情形，存在於導線中之寄生電感會成為問題，但根據本變化例1，由於不使用導線而可直接連接接合FET之源極、與MOSFET之汲極，故，可大致完全消除MOSFET之汲極與接合FET之源極之間之寄生電感(圖2之Lse1、Lse2)。從以上之點來看，根據本變化例1所特有之特徵點，可抑制由上述之第1機制引起之對MOSFET施加超過絕緣耐壓之電壓， 藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本變化例1，可謀求提高半導體裝置之可靠性。
根據本變化例1之封裝PKG3，於晶片搭載部PLT上疊層配置半導體晶片CHP1與半導體晶片CHP2。因此，在本變化例1之封裝PKG3中，可為封裝內具有1個晶片搭載部PLT之構造，因此，可直接挪用封裝內只有1個晶片搭載部之現有之通用封裝。即，根據本變化例1之封裝PKG3，由於可直接挪用所謂廉價之通用封裝，故可廉價地提供串疊連接之高性能之開關元件。換言之，根據本變化例1，可謀求削減形成串疊連接之高性能之開關元件之封裝PKG3之成本。
另，根據本變化例1，由於將形成有接合FET之半導體晶片CHP1、與形成有MOSFET之半導體晶片CHP2疊層，故亦可獲得可降低半導體晶片之安裝面積之優勢。特別是，該情形時，如圖5所示，由於可於晶片搭載部PLT中確保較大空間，故可使半導體晶片CHP1或半導體晶片CHP2所產生之熱有效散熱。進而，根據本變化例1，由於可降低開關元件之安裝面積，故，亦可獲得將先前配置於封裝外部之印刷基板上之自由電力隔通二極體(迴流二極體)與開關元件安裝於同一封裝中之優勢。其結果，根據本變化例1，可亦有助於削減印刷基板之安裝面積，藉此，可謀求削減電源系統所代表之系統整體之成本。
繼而，說明本變化例1之開關元件之其他安裝形態之一例。圖6係顯示本變化例1之封裝PKG4之安裝構成圖。圖6 所示之封裝PKG4、與圖5所示之封裝PKG3之不同點係形成於半導體晶片CHP1之表面之閘極焊墊GPj之配置位置不同之點。具體而言，在圖5所示之封裝PKG3中，以沿著半導體晶片CHP1之右邊側且相對右邊中央部成為對稱之方式配置有閘極焊墊GPj。與此相對，在圖6所示之封裝PKG4中，於最靠近半導體晶片CHP1之源極引線SL之邊側，偏向配置有閘極焊墊GPj。該情形時，可使閘極焊墊GPj至源極引線SL之距離最短。因此，根據圖6所示之封裝PKG4，可使連接閘極焊墊GPj與源極引線SL之導線Wgj之長度最短，藉此，可使存在於導線Wgj中之寄生電感最小化。因此，可抑制由上述之第2機制引起之對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，在圖6所示之封裝PKG4中，亦可謀求提高半導體裝置之可靠性。
說明本變化例1之開關元件之其他安裝形態之一例。圖7係顯示本變化例1之封裝PKG5之安裝構成圖。在圖7所示之封裝PKG5中，對閘極焊墊GPj與源極引線SL之連接、及源極焊墊SPm與源極引線SL之連接，使用例如包含銅板(金屬板)之夾片CLP。如此般，藉由使用銅板，導體電阻相比導線更小，故可謀求降低寄生電感。即，藉由使用金屬板構造之夾片CLP，可降低存在於閘極焊墊GPj與源極引線SL之間之寄生電感、及存在於源極焊墊SPm與源極引線SL之間之寄生電感。
特別是，根據圖7所示之封裝PKG5，由於可降低存在於 閘極焊墊GPj與源極引線SL之間之寄生電感，故可抑制由上述之第2機制引起之對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據圖7所示之封裝PKG5，可謀求提高半導體裝置之可靠性。再者，根據圖7所示之封裝PKG5，由於亦可降低存在於源極焊墊SPm與源極引線SL之間之寄生電感，故亦可謀求提高半導體裝置之電性特性。
另，圖8係顯示本變化例1之封裝PKG5之一剖面圖。如圖8所示，於晶片搭載部PLT上，介隔導電性接著材料PST而搭載有半導體晶片CHP1，且於該半導體晶片CHP1上介隔導電性接著材料(未圖示)，而搭載有半導體晶片CHP2。且，半導體晶片CHP1(閘極焊墊)與源極引線SL、及半導體晶片CHP2(源極焊墊)與源極引線SL藉由夾片CLP電性連接。另，虛線部係顯示以密封體覆蓋之部分。
繼而，說明本變化例1之開關元件之其他安裝形態之一例。圖9係顯示本變化例1之封裝PKG6之安裝構成圖。圖9所示之封裝PKG6、與圖5所示之封裝PKG3之不同點係，源極引線SL與汲極引線DL之形成位置不同之點。具體而言，在圖5所示之封裝PKG3中，於最左側配置有閘極引線GL，於正中央配置有汲極引線DL，於最右側配置有源極引線SL。與此相對，在圖9所示之封裝PKG6中，於最左側配置有閘極引線GL，於正中央配置有源極引線SL，於最右側配置有汲極引線DL。該情形時，如圖9所示，隨著源極引線SL之配置位置變更，搭載於晶片搭載部PLT之半導 體晶片CHP1之搭載位置變更。即，半導體晶片CHP1之配置位置係以相較於其他引線更靠近源極引線SL之方式變更。具體而言，半導體晶片CHP1係以相對圖9所示之中心線a-a'成為對稱之方式配置，且，以相對中心線b-b'偏向近前側(下側)之方式配置。其結果，在圖9所示之封裝PKG6中，亦可縮短閘極焊墊GPj與源極引線SL之間之距離。因此，可縮短連接閘極焊墊GPj與源極引線SL之導線Wgj之長度。即，在圖9所示之封裝PKG6中，亦可充分降低存在於導線Wgj中之寄生電感。因此，可抑制由上述之第2機制引起之對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，在圖9所示之封裝PKG6中，亦可謀求提高半導體裝置之可靠性。
進而，作為圖9所示之封裝PKG6所特有之特徵點，係可使將形成於半導體晶片CHP2之表面之閘極焊墊GPm、與閘極引線GL電性連接之導線Wgm之長度與圖5所示之封裝PKG3相比充分縮短之點。因此，根據圖9所示之封裝PKG6，因可降低導線Wgm之寄生電阻及寄生電感，故可提高本變化例1之開關元件之電性特性。
另，圖10係顯示本變化例1之封裝PKG6之一剖面圖。如圖10所示，於晶片搭載部PLT上，介隔導電性接著材料PST，而搭載有半導體晶片CHP1，且於該半導體晶片CHP1上，介隔導電性接著材料(未圖示)，而搭載有半導體晶片CHP2。且，半導體晶片CHP2(源極焊墊)與源極引線 SL藉由導線Wsm電性連接。另，虛線部係顯示以密封體覆蓋之部分。
接著，說明本變化例1之開關元件之其他安裝形態之一例。圖11係顯示本變化例1之封裝PKG7之安裝構成之圖。圖11所示之封裝PKG7、與圖9所示之封裝PKG6之不同點係形成於半導體晶片CHP1之表面之閘極焊墊GPj之配置位置不同之點。具體而言，在圖9所示之封裝PKG6中，以沿著半導體晶片CHP1之右邊側且相對右邊中央部成為對稱之方式配置有閘極焊墊GPj。與此相對，在圖11所示之封裝PKG7中，偏向於最靠近半導體晶片CHP1之源極引線SL之邊側而配置有閘極焊墊GPj。該情形時，可使閘極焊墊GPj至源極引線SL之距離為最短。因此，根據圖11所示之封裝PKG7，可使連接閘極焊墊GPj與源極引線SL之導線Wgj之長度最短，藉此，可使存在於導線Wgj中之寄生電感最小化。因此，可抑制由上述之第2機制引起之對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，在圖11所示之封裝PKG7中，亦可謀求提高半導體裝置之可靠性。
繼而，關於本實施形態1之開關元件、及本變化例之開關元件中存在之寄生電感，與先前技術之開關元件中存在之寄生電感對比進行說明。圖12係將串疊連接之開關元件之電路圖連同寄生電感一併顯示之圖。具體而言，圖12(a)係顯示先前技術之開關元件及寄生電感之存在位置之電路圖，圖12(b)係顯示本實施形態1之開關元件及寄生電感之 存在位置之電路圖。另，圖12(c)係顯示本變化例1之開關元件及寄生電感之存在位置之電路圖。
首先，從圖12(a)獲知，在先前技術之串疊連接之開關元件中，於連接接合FETQ1之源極與MOSFETQ2之汲極之中間節點Se存在寄生電感Lse，於MOSFETQ2之源極與開關元件之源極S之間存在寄生電感Ls。另，於接合FET之閘極電極、與開關元件之源極S之間存在寄生電感Lgi，於MOSFET之閘極電極Gm中存在寄生電感。
與此相對，如圖12(b)所示，在本實施形態1之串疊連接之開關元件中，寄生電感Lse、寄生電感Ls、及寄生電感Lgi與圖12(a)所示之先前技術之串疊連接之開關元件相比降低。此係例如圖3所示般，在本實施形態1中，基於採取藉由對晶片搭載部PLT1之配置位置、半導體晶片CHP1之配置位置與閘極焊墊GPj之配置位置下功夫，而縮短連接閘極焊墊GPj與源極引線SL之導線Wgj之構成之點，及將連接源極焊墊SPj與晶片搭載部PLT2之導線Wds以複數條構成之點者。藉此，根據本實施形態1，可抑制對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本實施形態1，可謀求提高半導體裝置之可靠性。
另，如圖12(c)所示，在本變化例1之串疊連接之開關元件中，與本實施形態1相同，可使寄生電感Ls及寄生電感Lgi與圖12(a)所示之先前技術之串疊連接之開關元件相比降低。進而，在本變化例1中，可將連接接合FETQ1之源 極、與MOSFETQ2之汲極之中間節點Se中存在之寄生電感Lse大致完全消除。其理由，例如圖5所示，於形成有接合FET之半導體晶片CHP1上，搭載有形成有MOSFET之半導體晶片CHP2。藉此，可直接連接形成於半導體晶片CHP1之表面之源極焊墊SPj、與形成於半導體晶片CHP2之背面之汲極電極。即，根據本變化例1，可不使用導線而直接連接接合FET之源極、與MOSFET之汲極。因此，根據本變化例1，可大致完全消除介存於接合FET之源極、與MOSFET之汲極之間之寄生電感。藉此，根據本變化例1，可抑制對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本變化例1，可謀求提高半導體裝置之可靠性。
<變化例2>
接著，說明本變化例2之封裝PKG8之安裝構成。圖13係顯示本變化例2之封裝PKG8之安裝構成圖。圖13所示之封裝PKG8之構成與圖3所示之封裝PKG1之構成大致相同。不同之點係封裝之外形形狀。如此般，本發明之技術思想不僅可適用於圖3所示之封裝PKG1，亦可適用於如圖13所示之封裝PKG8。即，將開關元件安裝構成之封裝中，有各個種類的通用封裝，本發明之技術思想可改良實現例如以圖3所示之封裝PKG1或圖13所示之封裝PKG8為代表之多種通用封裝。具體而言，在圖13所示之封裝PKG8中，亦可例如縮短閘極焊墊GPj與源極引線SL之間之距離，故，可縮短連接閘極焊墊GPj與源極引線SL之導線Wgj之 長度。因此，在圖13所示之封裝PKG8中，亦可充分降低存在於導線Wgj中之寄生電感。因此，可抑制對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，在圖13所示之封裝PKG8中，亦可謀求提高半導體裝置之可靠性。
此外，圖14係顯示本變化例2之封裝PKG8之一剖面圖。如圖14所示，於晶片搭載部PLT2上，介隔導電性接著材料PST，而搭載有半導體晶片CHP2。再者，例如半導體晶片CHP2(閘極焊墊)與閘極引線GL(閘極引線接線柱部GPST)藉由導線Wgm電性連接。此外，虛線部係顯示以密封體覆蓋之部分。
接著，說明本變化例2之開關元件之其他安裝形態之一例。圖15係顯示本變化例2之封裝PKG9之安裝構成圖。圖15所示之封裝PKG9之構成與圖5所示之封裝PKG3之構成大致相同。不同點係封裝之外形形狀。如此般，本發明之技術思想不僅可適用於圖5所示之封裝PKG3，亦可適用於如圖15所示之封裝PKG9。即，將開關元件安裝構成之封裝中有各個種類之通用封裝，且本發明之技術思想可適用於例如以圖5所示之封裝PKG3或圖15所示之封裝PKG9為代表之多種通用封裝。具體而言，藉由圖15所示之封裝PKG9，亦可於形成有接合FET之半導體晶片CHP1上，搭載有形成有MOSFET之半導體晶片CHP2，故，可將形成於源極焊墊SPj與半導體晶片CHP2之背面之汲極電極直接連接。因此，藉由圖15所示之封裝PKG9，亦可不使用導 線，而直接連接接合FET之源極與MOSFET之汲極，故，可將MOSFET之汲極與接合FET之源極之間之寄生電感(圖2之Lse1、Lse2)大致完全消除。因此，藉由圖15所示之封裝PKG9，亦可抑制對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本變化例2，可謀求提高半導體裝置之可靠性。
另，圖16係顯示本變化例2之封裝PKG9之一剖面之圖。如圖16所示，於晶片搭載部PLT上介隔導電性接著材料PST，而搭載有半導體晶片CHP1，且於該半導體晶片CHP1上介隔導電性接著材料(未圖示)，而搭載有半導體晶片CHP2。再者，例如半導體晶片CHP2(閘極焊墊)與閘極引線GL(閘極引線接線柱部GPST)藉由導線Wgm電性連接。另，虛線部係顯示以密封體覆蓋之部分。
<變化例3>
接著，說明本變化例3之封裝PKG10之安裝構成。圖17係顯示本變化例3之封裝PKG10之安裝構成圖。圖17所示之封裝PKG10之構成與圖3所示之封裝PKG1之構成大致相同。不同之點係封裝之外形形狀。如此般，本發明之技術思想不僅可適用於圖3所示之封裝PKG1，亦可適用於如圖17所示之封裝PKG10。即，將開關元件安裝構成之封裝中有各個種類之通用封裝，且本發明之技術思想可改良實現例如以圖3所示之封裝PKG1或圖17所示之封裝PKG10為代表之多種之通用封裝。具體而言，在圖17所示之封裝PKG10中，亦可例如縮短閘極焊墊GPj與源極引線SL之間 之距離，故可縮短連接閘極焊墊GPj與源極引線SL之導線Wgj之長度。因此，在圖17所示之封裝PKG10中，亦可充分降低存在於導線Wgj中之寄生電感。因此，可抑制對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，在圖17所示之封裝PKG10中，亦可謀求提高半導體裝置之可靠性。
另，圖18係顯示本變化例3之封裝PKG10之一剖面圖。如圖18所示，於晶片搭載部PLT1上介隔導電性接著材料PST，而搭載有半導體晶片CHP1。且，例如半導體晶片CHP1(閘極焊墊GPj)與源極引線SL(源極引線接線柱部SPST)藉由導線Wgj電性連接。此外，虛線部係顯示以密封體覆蓋之部分。
繼而，說明本變化例3之開關元件之其他安裝形態之一例。圖19係顯示本變化例3之封裝PKG11之安裝構成圖。圖19所示之封裝PKG11之構成與圖5所示之封裝PKG3之構成大致相同。不同之點係封裝之外形形狀。如此般，本發明之技術思想不僅可適用於圖5所示之封裝PKG3，亦可適用於如圖19所示之封裝PKG11。即，將開關元件安裝構成之封裝中，有各個種類之通用封裝，且本發明之技術思想可適用於例如以圖5所示之封裝PKG3或圖19所示之封裝PKG11為代表之多種之通用封裝。具體而言，藉由圖19所示之封裝PKG11，亦可於形成有接合FET之半導體晶片CHP1上，搭載有形成有MOSFET之半導體晶片CHP2，故，可將源極焊墊SPj與形成於半導體晶片CHP2之背面之 汲極電極直接連接。因此，藉由圖19所示之封裝PKG11，亦可不使用導線，而直接連接接合FET之源極與MOSFET之汲極，故，可將MOSFET之汲極與接合FET之源極之間之寄生電感(圖2之Lse1、Lse2)大致完全消除。因此，藉由圖19所示之封裝PKG11，亦可抑制對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本變化例3，可謀求提高半導體裝置之可靠性。
另，圖20係顯示本變化例3之封裝PKG11之一剖面之圖。如圖20所示，於晶片搭載部PLT上，介隔導電性接著材料PST，而搭載有半導體晶片CHP1，且於該半導體晶片CHP1上介隔導電性接著材料(未圖示)，而搭載有半導體晶片CHP2。且，例如半導體晶片CHP2(閘極焊墊)與閘極引線GL(閘極引線接線柱部GPST)藉由導線Wsm電性連接。另，虛線部顯示以密封體覆蓋之部分。
<變化例4>
接著，說明本變化例4之封裝PKG12之安裝構成。圖21係顯示本變化例4之封裝PKG12之安裝構成圖。圖21所示之封裝PKG12之構成與圖3所示之封裝PKG1之構成大致相同。不同之點係封裝之外形形狀。具體而言，本變化例4之封裝PKG12之封裝形態為SOP(Small Outline Package：小輪廓封裝)。如此般，本發明之技術思想不僅可適用於圖3所示之封裝PKG1，亦可適用於如圖21所示之封裝PKG12。即，將開關元件安裝構成之封裝中，有各個種類 之通用封裝，且本發明之技術思想可改良實現例如以圖3所示之封裝PKG1或圖21所示之封裝PKG12為代表之多種通用封裝。具體而言，在圖21所示之封裝PKG12中，亦可例如縮短閘極焊墊GPj與源極引線SL之間之距離，故可縮短連接閘極焊墊GPj與源極引線SL之導線Wgj之長度。因此，在圖21所示之封裝PKG12中，亦可充分降低存在於導線Wgj中之寄生電感。因此，可抑制對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，在圖21所示之封裝PKG12中，亦可謀求提高半導體裝置之可靠性。
另，圖22係顯示本變化例4之封裝PKG12之一剖面圖。如圖22所示，於晶片搭載部PLT1上介隔導電性接著材料(未圖示)，而搭載有半導體晶片CHP1。且，例如，半導體晶片CHP1(閘極焊墊GPj)與源極引線SL(源極引線接線柱部SPST)藉由導線Wgj電性連接。另，在本變化例4中，例如圖22所示，晶片搭載部PLT1、半導體晶片CHP1、導線Wgj或引線之一部分等，藉由包含樹脂之密封體MR密封。此時，可從圖21與圖22類推，在封裝PKG12(SOP封裝)中，密封體MR係大體呈長方體形狀，且具有第1側面、及與該第1側面對向之第2側面。再者，閘極引線GL、及源極引線SL係以從密封體MR之第1側面突出之方式構成，汲極引線DL係以從密封體MR之第2側面突出之方式構成。
繼而，說明本變化例4之開關元件之其他安裝形態之一例。圖23係顯示本變化例4之封裝PKG13之安裝構成圖。 圖23所示之封裝PKG13之構成與圖5所示之封裝PKG3之構成大致相同。不同之點係封裝之外形形狀。具體而言，本變化例4之封裝PKG12之封裝形態為SOP(Small Outline Package：小輪廓封裝)。如此般，本發明之技術思想不僅可適用於圖5所示之封裝PKG3，亦可適用於如圖23所示之封裝PKG13。即，將開關元件安裝構成之封裝中，有各個種類之通用封裝，且本發明之技術思想可適用於例如以圖5所示之封裝PKG3或圖23所示之封裝PKG13為代表之多種通用封裝。具體而言，藉由圖23所示之封裝PKG13，亦可於形成有接合FET之半導體晶片CHP1上，搭載有形成有MOSFET之半導體晶片CHP2，故，可直接連接源極焊墊SPj、與形成於半導體晶片CHP2之背面之汲極電極。因此，藉由圖23所示之封裝PKG13，亦可不使用導線，而直接連接接合FET之源極、與MOSFET之汲極，故，可大致完全消除MOSFET之汲極與接合FET之源極之間之寄生電感(圖2之Lse1、Lse2)。因此，藉由圖23所示之封裝PKG13，亦可抑制對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本變化例4，可謀求提高半導體裝置之可靠性。
另，圖24係顯示本變化例4之封裝PKG13之一剖面圖。如圖24所示，於晶片搭載部PLT上介隔導電性接著材料(未圖示)，而搭載有半導體晶片CHP1，且於該半導體晶片CHP1上，介隔導電性接著材料(未圖示)，而搭載有半導體晶片CHP2。且，例如半導體晶片CHP1(閘極焊墊GPj)與源 極引線SL(源極引線接線柱部SPST)藉由導線Wgj電性連接。另，在本變化例4中，例如，如圖22所示，晶片搭載部PLT、半導體晶片CHP1、半導體晶片CHP2、導線Wgj或引線之一部分等，藉由包含樹脂之密封體MR密封。此時，引線之一部分從密封體MR之兩側之側面突出。
(實施形態2)
在上述實施形態1中，已說明關於封裝構造之設計點，在本實施形態2中，說明關於裝置構造之設計點。
<疊層半導體晶片之佈局構成>
圖25係顯示本實施形態2之半導體晶片之佈局構成圖。以下所示之半導體晶片之佈局構成係顯示例如於形成將相比以碳化矽(SiC)為代表之矽(Si)能帶隙更大之物質作為材料之接合FET之半導體晶片CHP1上，疊層搭載形成有以矽(Si)為材料之MOSFET之半導體晶片CHP2之例。在圖25中，半導體晶片CHP1係呈矩形形狀，且於該呈矩形形狀之半導體晶片CHP1之外周區域中形成有終端區域TMj。該終端區域TMj係為確保耐壓而設置之區域。且，終端區域TMj之內側區域為主動區域ACTj。於該主動區域ACTj中形成有複數個接合FET。
半導體晶片CHP1之外周區域中設置有終端區域TMj，終端區域TMj之一部分進入內部，且在該區域中形成有閘極焊墊GPj。該閘極焊墊GPj經由閘極配線與形成於主動區域ACTj之複數個接合FET之各閘極電極連接。此處，在圖25中，閘極焊墊GPj配置於半導體晶片CHP1之右邊中央部。 換言之，閘極焊墊GPj係偏向右邊配置，且以相對左右延伸之中心線成為對稱之方式配置。藉此，可抑制連接複數個接合FET之各閘極電極與閘極焊墊GPj之閘極配線之距離之偏差。因此，根據圖25所示之佈局構成，可獲得可統一利用形成於半導體晶片CHP1內之複數個接合FET之特性之優勢。
於半導體晶片CHP1之主動區域ACTj上，形成有源極焊墊SPj。該源極焊墊SPj與形成於主動區域ACTj之接合FET之源極區域電性連接。且，於該源極焊墊SPj上，搭載有呈矩形形狀之半導體晶片CHP2。於該半導體晶片CHP2中，形成有複數個MOSFET，且於半導體晶片CHP2之主面中形成有源極焊墊SPm、與閘極焊墊GPm。源極焊墊SPm與MOSFET之源極區域電性連接，閘極焊墊GPj與MOSFET之閘極電極電性連接。
圖26係顯示本實施形態2之疊層半導體晶片之其他佈局構成圖。圖26所示之佈局構成與圖25所示之佈局構成大致相同。圖26與圖25之不同之點係如下之點：在圖25所示之佈局構成中，閘極焊墊GPj配置於右邊中央部，與此相對，在圖26所示之佈局構成中，閘極焊墊GPj偏向配置於半導體晶片CHP1之右下角部。如此般，在圖26中，藉由配置於半導體晶片CHP1之右下角部，例如圖6所示，可使閘極焊墊GPj至源極引線SL之距離最短。即，藉由採用圖26所示之佈局構成，可使連接閘極焊墊GPj與源極引線SL之導線Wgj之長度最短，藉此，可使存在於導線Wgj中之 寄生電感最小化。
繼而，圖27係以圖25及圖26之A-A線切斷之剖面圖。如圖27所示，於半導體基板SUBj之背面形成有汲極電極DEj，且於半導體基板SUB之主面(表面)中形成有漂移層DFTj。且，於漂移層DFTj上形成有主動區域ACTj，於該主動區域ACTj中形成有接合FET之閘極電極及源極區域。於主動區域ACTj之端部，形成有用以確保耐壓之終端區域TMj，且於主動區域ACTj上形成有源極焊墊SPj。以覆蓋該源極焊墊SPj之端部之方式，形成有例如包含氧化矽膜之絕緣膜IL1。至此之構成係形成有接合FET之半導體晶片CHP1之構造，且於形成有該接合FET之半導體晶片CHP1上，搭載有形成有MOSFET之半導體晶片CHP2。
具體而言，於露出之源極焊墊SPj上，例如，介隔導電性接著材料(未圖示)而接觸有汲極電極DEm。該汲極電極DEm形成於半導體基板SUBm之背面，且與半導體基板SUBm之背面相反側之主面(表面)上，形成有漂移層DFTm。再者，於漂移層DFm中形成有主動區域ACTm，且於主動區域ACTm之兩端部形成有用以確保耐壓之終端區域TMm。於該主動區域ACTm中，形成有MOSFET之閘極電極及源極區域。以跨越至主動區域ACTm與終端區域TMm之方式形成有源極焊墊SPm。雖以覆蓋該源極焊墊SPm之端部之方式形成有絕緣膜IL2，但源極焊墊SPm之大部分之表面區域係從絕緣膜IL2露出。藉此，於形成有接合FET之半導體晶片CHP1上搭載有形成有MOSFET之半導 體晶片CHP2。
如圖27所示，以內包於源極焊墊SPj之方式，半導體晶片CHP2搭載於半導體晶片CHP1上。因此，形成於半導體晶片CHP2之背面之汲極電極Dem，不經由導線而以導電性接著材料(未圖示)，與形成於半導體晶片CHP1之表面之源極焊墊SPj直接接觸。該點意為可大致完全消除介存於接合FET之源極、與MOSFET之汲極之間之寄生電感。即，如圖27所示，藉由於半導體晶片CHP1上直接搭載半導體晶片CHP2之構成，為連接接合FET之源極、與MOSFET之汲極而無需導線。使用導線之情形，存在於導線中之寄生電感會成為問題，而根據本實施形態2之佈局構成，可不使用導線而直接連接接合FET之源極、與MOSFET之汲極。因此，可大致完全消除MOSFET之汲極與接合FET之源極之間之寄生電感(圖2之Lse1、Lse2)。自以上之點，根據本實施形態2，可抑制對MOSFET施加超過絕緣耐壓之電壓，藉此，可有效抑制串疊連接之MOSFET之突崩破壞。其結果，根據本實施形態2，可謀求提高半導體裝置之可靠性。
另，如圖27所示，根據本實施形態2之佈局構成，由於主動區域ASCTj上配置有源極焊墊SPj，故可增大流通接合FET之電流。且，該情形時，源極焊墊SPj亦可大面積化，故，亦可增大源極焊墊SPj上所搭載之半導體晶片CHP2之面積。即，所謂可增大半導體晶片CHP2之面積，意為可增加形成於半導體晶片CHP2內之MOSFET之數量，其結 果，可增大流通複數個MOSFET整體之電流。如此般，根據本實施形態2之佈局構成，由於可增大流通複數個接合FET整體之電流、及流通複數個MOSFET整體之電流，故可容易實現將接合FET與MOSFET進行串疊連接之開關元件之大電流化。再者，根據本實施形態2，由於使用利用與矽相比較原理上可實現高耐壓及低導通電阻之碳化矽之接合FET，故可提供可兼備大電流化、高耐壓化、及低導通電阻化之開關元件。
<佈局構成之變化例>
繼而，說明本實施形態2之疊層半導體晶片之其他佈局構成。圖28係顯示本變化例之疊層半導體晶片之佈局構成圖。如圖28所示，半導體晶片CHP1呈矩形形狀，於該呈矩形形狀之半導體晶片CHP1之外周區域中形成有終端區域TMj。且，終端區域TMj之內側區域中，形成有主動區域ACTj、閘極焊墊GPj、及源極焊墊SPj。此處，本變化例之特徵係以不平面性重疊之方式配置有主動區域ACTj、閘極焊墊GPj、及源極焊墊SPj之點。即，如圖28所示，形成接合FET之主動區域ACTj係以避開閘極焊墊GPj或源極焊墊SPj之方式配置。且，源極焊墊SPj上搭載有半導體晶片CHP2。
另，圖29係顯示本變化例之疊層半導體晶片之其他佈局構成圖。圖29所示之佈局構成與圖28所示之佈局構成大致相同。圖29與圖28之不同之點係如下之點：在圖28所示之佈局構成中，閘極焊墊GPj配置於右邊中央部，與此相 對，在圖29所示之佈局構成中，閘極焊墊GPj偏向配置於半導體晶片CHP1之右下角部。
接著，圖30係以圖28及圖29之A-A線切斷之剖面圖。如圖30所示，於半導體基板SUBj之背面形成有汲極電極DEj，且於半導體基板SUBj之主面(表面)上形成有漂移層DFTj。該漂移層DFTj中形成有主動區域ACTj，且主動區域ACTj之外側區域中形成有終端區域TMj。主動區域ACTj中，形成有接合FET之閘極電極GE或源極區域SR。且，主動區域ACTj上及終端區域TMj上形成有絕緣膜IL1，且該絕緣膜IL1上形成有源極焊墊SPj。此處，在本變化例中，重點係源極焊墊SPj未形成於主動區域ACTj中，而形成於終端區域TMj上之點。即，在本變化例中，在俯視下，主動區域ACTj與源極焊墊SPj以不重疊之方式配置，且源極焊墊SPj係配置於終端區域TMj上。另，在圖30中，省略配置於源極焊墊SPj上之半導體晶片CHP2之圖示。即，在圖30中，亦與圖27相同，於源極焊墊SPj上搭載半導體晶片CHP2，由於該構成相同，故在圖30中省略配置於源極焊墊SPj上之半導體晶片CHP2之圖示。
根據如此般構成之本變化例，可獲得以下所示之效果。即，於源極焊墊SPj上搭載半導體晶片CHP2。該情形時，對源極焊墊SPj施加應力。但，在本變化例中，該源極焊墊SPj之正下方區域中，由於未形成形成有接合FET之主動區域ACTj，故可防止對主動區域ACTj施加應力。即，根據本變化例，可防止對主動區域ACTj施加不必要之應力， 故可防止形成於主動區域ACTj中之接合FET之機械性損壞。
另，搭載於源極焊墊SPj上之半導體晶片CHP2之表面中，形成有閘極焊墊GPm或源極焊墊SPm，且對該等焊墊，藉由導線接合而連接導線。在該導線接合工序中亦產生應力，但在本變化例中，由於半導體晶片CHP2與主動區域ACTj係以不平面性重疊之方式配置，故可防止導線接合工序中所產生之應力直接傳達至主動區域ACTj。其結果，根據本變化例之疊層半導體晶片之佈局構成，可抑制半導體晶片CHP2之搭載時或導線接合時產生之應力對形成於半導體晶片CHP1之主動區域ACTj之接合FET之特性造成影響。即，根據本變化例，可提供裝配良率較高、可靠性較高之半導體裝置。
<MOSFET之裝置構造>
接著，說明形成於半導體晶片CHP2上之MOSFET之裝置構造之一例。圖31係顯示本實施形態2之MOSFET之裝置構造之一例之剖面圖。如圖31所示，例如包含導入有n型雜質之矽之半導體基板SUBm之背面，形成有例如包含金膜之汲極電極DEm，另一方面，於半導體基板SUBm之主面側，形成有包含n型半導體區域之漂移層DFTm。漂移層DFTm中形成有包含p型半導體區域之本體區域PR，且以內包於該本體區域PR之方式，形成有包含n型半導體區域之源極區域SR。該源極區域SR與漂移層DFTm所包夾之本體區域PR之表面區域係作為通道形成區域發揮功能。且，以 電性連接於源極區域SR與本體區域PR之雙方之方式形成有源極電極SE。進而，包含通道形成區域上之漂移層DFTm之表面中，形成有例如包含氧化矽膜之閘極絕緣膜GOX，且該閘極絕緣膜GOX上形成有閘極電極G。
在如此般構成之MOSFET中，例如自源極區域SR通過形成於本體區域PR之表面之通道形成區域，以使電子自漂移層DFTm流至形成於半導體基板SUBm之背面之汲極電極DEm之方式構成，係所謂稱為縱型MOSFET之構造。該縱型MOSFET之優勢係，由於可高密度地形成於半導體晶片CHP2，故成為電流密度較大之MOSFET之點。因此，藉由將縱型MOSFET利用於本發明之開關元件，可實現電流密度較大之開關元件。
例如，圖28或圖29所示之佈局構成之情形，雖可有效防止基於對形成於主動區域ACTj之接合FET之應力之特性劣化，但另一方面，源極焊墊SPj之面積相對縮小。該情形時，形成有配置於源極焊墊SPj上之MOSFET之半導體晶片CHP2之面積雖亦相對縮小，但作為形成於半導體晶片CHP2上之MOSFET，若使用圖31所示之縱型MOSFET，則即便是較小之晶片面積，仍可實現比較大之電流密度之MOSFET。其結果，可增大串疊連接之開關元件整體之電流密度。即，特別是藉由採取圖28或圖29所示之佈局構成，形成有MOSFET之半導體晶片CHP2之面積縮小之情形，藉由使用圖31所示之縱型MOSFET，仍可提供一方面有效防止基於對形成於主動區域ACTj中之接合FET之應力 之特性劣化並可確保大電流之高性能之開關元件。
<本發明者發現之課題>
接著，說明本發明者發現之新課題。圖32係顯示串疊連接之開關元件之電流路徑圖。圖32(a)係顯示導通時之電流路徑圖，圖32(b)係顯示斷開時流通之洩漏電流之電流路徑圖。如圖32(a)所示，在導通時，額定電流Id從接合FETQ1之汲極流至MOSFETQ2之源極。即，額定電流Id從串疊連接之開關元件之汲極D流向源極S。此時，MOSFETQ2被切斷前之MOSFETQ2之汲極電壓(中間節點Se之電壓)可根據MOSFETQ2之導通電阻與額定電流Id之積求出。例如，若導通電阻為10 mΩ，額定電流Id為40 A，即中間節點Se之電壓為0.4 V。該中間節點Se之電壓係MOSFETQ2之汲極電壓，且亦為接合FETQ1之源極電壓，故，以接合FETQ1之源極電壓為基準之接合FETQ1之閘極電壓即電壓Vgs係-0.4 V。
使串疊連接之開關元件從導通狀態轉變至斷開狀態之情形時，如圖32(a)所示，從對MOSFETQ2之閘極電極Gm施加15 V之狀態，如圖32(b)所示般，對MOSFETQ2之閘極電極Gm施加0 V。MOSFETQ2因係常關型MOSFET，故而對閘極電極Gm施加0 V後切斷。
將MOSFETQ2切斷之過程中，在初期階段，通道逐漸消失，故，MOSFETQ2之汲極與源極間之導通電阻逐漸上升。使用於串疊連接之開關元件之接合FETQ1係常開型，且在將MOSFETQ2切斷之初期階段，接合FETQ1之電壓 Vgs係-0.4 V，故，接合FETQ1維持導通狀態。因此，電流從接合FETQ1之汲極(例如在電源電壓300 V之應用程式中，汲極電壓為300 V左右)向接合FETQ1之源極流動。因此，MOSFETQ2之汲極電壓(中間節點Se之電壓)成為隨著通道之消失而增加之導通電阻、與從接合FETQ1之汲極流入之汲極電流之積，故，MOSFETQ2之汲極電壓(中間節點Se之電壓)從0.4 V逐漸上升。
其後，MOSFETQ2之通道完全消失，而MOSFETQ2完全切斷後，藉由自接合FETQ1流入之電流，電荷累積於中間節點Se，故，MOSFETQ2之汲極電壓(中間節點Se之電壓)進而上升，且上升至接合FETQ1之切斷電壓(例如5 V至15 V左右)。成為該狀態後，接合FETQ1斷開，接合FETQ1之汲極電流不再流動。即，MOSFETQ2之汲極電壓(中間節點Se之電壓)之上升停止，且維持該狀態。
但，本發明者發現在串疊連接之開關元件中，即便接合FETQ1之電壓Vgs成為-5 V至-15 V左右之情形時，仍有於接合FETQ1之汲極與源極之間流動洩漏電流Id1之情形。該洩漏電流Id1流動後，於中間節點Se中累積電荷，故，MOSFETQ2之汲極電壓(中間節點Se之電壓)上升。因此，若上述之洩漏電流Id1增大，則會產生MOSFETQ2之汲極電壓(中間節點Se之電壓)成為MOSFETQ2之耐壓以上(例如，30 V以上)之電壓之風險。其結果，MOSFETQ2將進行突崩動作，最終，產生MOSFETQ2被破壞之風險。作為其對策，若使用耐壓較高之高耐壓之MOSFET，則可防止 上述之MOSFET之突崩破壞之可能性增高，但，使用高耐壓之MOSFET之情形時，為確保耐壓，有必要較厚地設計漂移層。如此般，若低濃度之漂移層之厚度增厚，則會導致MOSFET之導通電阻增加，故，會產生增加串疊連接之開關元件導通時之導通損失之問題點。即，為一方面確保串疊連接之開關元件之高性能化，並防止MOSFET之突崩破壞，有必要實施使低濃度之漂移層增厚之構成以外之方法。因此，在本實施形態2中，為一方面確保串疊連接之開關元件之高性能化，並防止MOSFET之突崩破壞，對接合FET之裝置構造實施方法。以下，說明實施該方法之本實施形態2之接合FET之裝置構造。
<接合FET之裝置構造>
圖33係顯示本實施形態2之接合FET之裝置構造之剖面圖。如圖33所示，本實施形態2之接合FET具有半導體基板SUBj，該半導體基板SUBj之背面形成有汲極電極DEj。另一方面，與半導體基板SUBj之背面相反側之主面側，形成有漂移層DFTj，且該漂移層DFTj中，形成有複數個溝槽TR。且，複數個溝槽TR之各個側面及底面中，形成有閘極電極GE(亦稱為閘極區域)，且以包夾於鄰接之溝槽TR之側面及底面上所形成之閘極電極GE中之方式形成有通道形成區域。該通道形成區域之上部形成有源極區域SR。在如此般構成之接合FET中，藉由控制對閘極電極GE施加之電壓，而控制來自閘極電極GE之空乏層之延伸。藉此，若自相互鄰接之閘極電極GE延伸之空乏層連接，則通道 形成區域消失而實現斷開狀態，另一方面，自相互鄰接之閘極電極GE延伸之空乏層不連接之情形時，形成通道形成區域而實現導通狀態。
此處，本實施形態2之接合FET之特徵點係通道形成區域之通道長度CL為1 μm以上之點。換言之，本實施形態2之特徵點在於源極區域SR之底部、與閘極電極GE之底部之間之距離為1 μm以上之點。藉此，由於可延長通道形成區域之通道長度，故可提高接合FET斷開時之通道形成區域內之靜電電勢。因此，根據本實施形態2，相比使用通道長度為0.5 μm左右之裝置構造之情形，可較小地抑制接合FET之汲極與源極之間流動之洩漏電流。如此般，將通道長度CL設為1 μm以上之優勢在於，基於可提高斷開時之通道形成區域內之靜電電勢之點，而可降低洩漏電流之點，再者，可認為通道長度CL自身延長之點亦有助於降低洩漏電流。
進而，圖33所示之接合FET之裝置構造之情形，相比成為汲極之半導體基板SUBj與源極區域SR之間之距離，半導體基板SUBj與閘極電極GE之間之距離較小。且，在接合FET斷開之狀態下，於閘極電極GE與漂移層DFTj之間施加反向電壓(逆向偏壓)。其結果，斷開時流通接合FET之洩漏電流，相比流動於距離較遠離之半導體基板SUBj與源極區域SR之間，可認為主要作為距離較短之半導體基板SUBj與閘極電極GE之間之反向電流(洩漏電流)流動者。因此，根據本實施形態2，接合FET切斷後，可大幅降低流動 於接合FET之汲極與源極間之洩漏電流。因此，根據本實施形態2，可抑制以流動於斷開時之接合FET之汲極與源極間之洩漏電流為起因，而MOSFET之汲極電壓上升至耐壓以上之電壓，藉此，可有效防止MOSFET突崩動作而最終MOSFET損壞。另，根據圖33所示之溝槽構造之接合FET，由於可高密度地形成接合FET，故，無需說明，可實現電流密度較大之開關元件。
接著，圖34係顯示本實施形態2之接合FET之其他裝置構造之剖面圖。如圖34所示，本實施形態2之其他接合FET具有半導體基板SUBj，且該半導體基板SUBj之背面形成有汲極電極DEj。另一方面，與半導體基板SUBj之背面相反側之主面側，形成有漂移層DFTj，且該漂移層DFTj中，以分離嵌入之方式形成有複數個閘極電極GE。且，鄰接之閘極電極GE間之漂移層DFTj之表面上形成有源極區域SR。如此般構成之圖34所示之接合FET係不具有所謂溝槽構造之縱型接合FET。
在具有如此之構造之接合FET中，特徵點亦在於通道形成區域之通道長度CL為1 μm以上之點。換言之，特徵點在於源極區域SR之底部、與閘極電極GE之底部之間之距離(通道長度CL)為1 μm以上之點。藉此，由於可延長通道形成區域之通道長度，故，即使圖34所示之接合FET，亦可提高斷開時之通道形成區域內之靜電電勢。因此，即便是圖34所示之接合FET，相比使用通道長度為0.5 μm左右之裝置構造之情形，亦可較小地抑制流動於接合FET之汲 極與源極之間之洩漏電流。如此般，將通道長度CL設為1 μm以上之優勢在於，基於可提高斷開時之通道形成區域內之靜電電勢之點而可降低洩漏電流之點，再者，通道長度CL自身延長之點亦有助於降低洩漏電流。
圖34所示之接合FET之優勢在於裝置構造簡單而可降低製造成本之點。進而，具有如下之優勢：在圖33所示之接合FET中，有必要以高度傾斜離子佈值技術等之步驟，於溝槽TR之側面形成導電型雜質(p型雜質)，與此相對，在圖34所示之接合FET中，為形成閘極電極GE，無需使用高度傾斜離子佈值技術，而導入閘極電極GE中之雜質分布公佈之精度較高。即，根據圖34所示之接合FET，可獲得可容易形成特性統一之接合FET之優勢。
以上，雖已基於實施形態具體說明由本發明者所完成之發明，但本發明並非限定於上述實施形態，不言而喻，在不脫離其要點之範圍內，可做各種變更。
例如，在上述實施形態中，雖已說明將MOSFET之閘極電極以閘極驅動電路(閘極驅動器)驅動之例，但接合FET之閘極電極亦可以閘極驅動電路驅動。該情形時，藉由以閘極驅動電路控制接合FET之閘極電極，可將接合FET之源極電壓控制於所期望之位準，故可獲得可抑制中間節點之突波電壓之效果。該構成之情形，雖會導致端子數量增加，但可獲得可提供更低損失之開關元件之優勢。
另，關於上述實施形態1所說明之封裝形態，引線配置亦並非限定於該等。即，閘極引線、汲極引線、及源極引 線之配置位置可做各種變更。例如，將封裝安裝於安裝基板時，可以可挪用現有之引線配置之方式，決定封裝之引線配置。該情形時，無需變更安裝基板，亦可抑制隨著設計變更之成本之增加。
再者，疊層半導體晶片之佈局構成亦並非特別限定於說明書所說明之佈局構成，各半導體晶片之形狀、焊墊之形狀、終端區域之形狀等亦並非特別限定。另，接合FET或MOSFET之構造亦並非受限定者，而可應用各種現有之構造。進而，裝置之雜質分布公佈亦可自由變更。例如，在MOSFET中，可以使表面之雜質濃度較稀以防穿透且於深度方向使雜質濃度逐漸加深之方式注入雜質。
另，設想上述之MOSFET並非限定於由氧化膜形成閘極絕緣膜之情形，而係亦包含將閘極絕緣膜較廣地由絕緣膜形成之MISFET(Metal Insulator Semiconductor Field Effect Transistor：金屬絕緣半導體場效電晶體)者。即，在本說明書中，方便起見使用MOSFET此用語，但該MOSFET係作為亦包含MISFET之意圖之用語而在本說明書中使用。
另，作為上述之各導線之金屬材料，可使用金(Au)、金合金、銅(Cu)、銅合金、鋁(Al)、鋁合金等。
本發明之開關元件雖可應用於例如電源電路，但並非限定於此，例如，可應用於空調用之變換器、太陽光發電系統之電力調節器、混合動力汽車或電動汽車之變換器、電腦之電源模組、白色LED之變換器等之各種機器。
[產業上之可利用性]
本發明可廣泛利用於製造半導體裝置之製造業。
ACTj‧‧‧主動區域
ACTm‧‧‧主動區域
CHP1‧‧‧半導體晶片
CHP2‧‧‧半導體晶片
CL‧‧‧通道長度
CLP‧‧‧夾片
D‧‧‧汲極
D1‧‧‧汲極
D2‧‧‧汲極
DEj‧‧‧汲極電極
DEm‧‧‧汲極電極
DFTj‧‧‧漂移層
DFTm‧‧‧漂移層
Dj1‧‧‧汲極
Dj2‧‧‧汲極
DL‧‧‧汲極引線
Dm‧‧‧汲極
Dm1‧‧‧汲極
Dm2‧‧‧汲極
G‧‧‧閘極電極
GE‧‧‧閘極電極
Gj‧‧‧閘極電極
Gj1‧‧‧閘極電極
Gj2‧‧‧閘極電極
GL‧‧‧閘極引線
Gm‧‧‧閘極電極
Gm1‧‧‧閘極電極
Gm2‧‧‧閘極電極
GOX‧‧‧閘極絕緣膜
GPj‧‧‧閘極焊墊
GPm‧‧‧閘極焊墊
GPST‧‧‧閘極引線接線柱部
Id‧‧‧額定電流
Id1‧‧‧洩漏電流
IL1‧‧‧絕緣膜
IL2‧‧‧絕緣膜
Lgi1‧‧‧寄生電感
Lgi2‧‧‧寄生電感
LL‧‧‧負荷電感
Ls‧‧‧寄生電感
Lse1‧‧‧寄生電感
Lse2‧‧‧寄生電感
MR‧‧‧密封體
PKG1‧‧‧封裝
PKG2‧‧‧封裝
PKG3‧‧‧封裝
PKG4‧‧‧封裝
PKG5‧‧‧封裝
PKG6‧‧‧封裝
PKG7‧‧‧封裝
PKG8‧‧‧封裝
PKG9‧‧‧封裝
PKG10‧‧‧封裝
PKG11‧‧‧封裝
PKG12‧‧‧封裝
PKG13‧‧‧封裝
PLT‧‧‧晶片搭載部
PLT1‧‧‧晶片搭載部
PLT2‧‧‧晶片搭載部
PR‧‧‧本體區域
Q1‧‧‧接合FET
Q1a‧‧‧接合FET
Q1b‧‧‧接合FET
Q2‧‧‧MOSFET
Q2a‧‧‧MOSFET
Q2b‧‧‧MOSFET
S‧‧‧源極
S1‧‧‧源極
S2‧‧‧源極
SE‧‧‧源極電極
Se‧‧‧中間節點
Sj‧‧‧源極
Sj1‧‧‧源極
Sj2‧‧‧源極
SL‧‧‧源極引線
Sm‧‧‧源極
Sm1‧‧‧源極
Sm2‧‧‧源極
SPj‧‧‧源極焊墊
SPm‧‧‧源極焊墊
SPST‧‧‧源極引線接線柱部
SR‧‧‧源極區域
SUBj‧‧‧半導體基板
SUBm‧‧‧半導體基板
TMj‧‧‧終端區域
TMm‧‧‧終端區域
TR‧‧‧溝槽
Vak‧‧‧電壓
Vdsu‧‧‧電壓
Vdsmu‧‧‧電壓
Vdsmd‧‧‧電壓
Wds‧‧‧導線
Wgj‧‧‧導線
Wgm‧‧‧導線
Wsm‧‧‧導線
圖1係顯示採用串疊連接方式之開關元件之電路構成之圖。
圖2(a)係顯示將串疊連接之接合FET與MOSFET作為開關元件利用之變換器之電路圖。(b)係顯示將構成上機械臂之開關元件接通之情形之波形圖，(c)係顯示將構成上機械臂之開關元件關斷之情形之波形圖。
圖3係顯示本發明之實施形態1之半導體裝置之安裝構成圖。
圖4係顯示實施形態1之其他半導體裝置之安裝構成圖。
圖5係顯示變化例1之半導體裝置之安裝構成圖。
圖6係顯示變化例1之其他半導體裝置之安裝構成圖。
圖7係顯示變化例1之其他半導體裝置之安裝構成圖。
圖8係顯示圖7之一剖面之剖面圖。
圖9係顯示變化例1之其他半導體裝置之安裝構成圖。
圖10係顯示圖9之一剖面之剖面圖。
圖11係顯示變化例1之其他半導體裝置之安裝構成圖。
圖12(a)係顯示先前技術之開關元件及寄生電感之存在位置之電路圖，(b)係顯示實施形態1之開關元件及寄生電感之存在位置之電路圖。另，(c)係顯示本變化例1之開關元件及寄生電感之存在位置之電路圖
圖13係顯示變化例2之半導體裝置之安裝構成圖。
圖14係顯示圖13之一剖面之剖面圖。
圖15係顯示變化例2之其他半導體裝置之安裝構成圖。
圖16係顯示圖15之一剖面之剖面圖。
圖17係顯示變化例3之半導體裝置之安裝構成圖。
圖18係顯示圖17之一剖面之剖面圖。
圖19係顯示變化例3之其他半導體裝置之安裝構成圖。
圖20係顯示圖19之一剖面之剖面圖。
圖21係顯示變化例4之半導體裝置之安裝構成圖。
圖22係顯示圖21之一剖面之剖面圖。
圖23係顯示變化例4之其他半導體裝置之安裝構成圖。
圖24係顯示圖23之一剖面之剖面圖。
圖25係顯示實施形態2之疊層半導體晶片之構成圖。
圖26係顯示實施形態2之疊層半導體晶片之其他構成圖。
圖27係以圖25及圖26之A-A線切斷之剖面圖。
圖28係顯示變化例之疊層半導體晶片之構成圖。
圖29係顯示變化例之疊層半導體晶片之其他構成圖。
圖30係以圖28及圖29之A-A線切斷之剖面圖。
圖31係顯示實施形態2之MOSFET之裝置構造之剖面圖。
圖32係顯示串疊連接之開關元件之電流路徑圖。(a)係顯示導通時之電流路徑圖，(b)係顯示斷開時流動之洩漏電流之電流路徑圖。
圖33係顯示實施形態2之接合FET之裝置構造之剖面圖。
圖34係顯示實施形態2之接合FET之其他裝置構造之剖面圖。
CHP1‧‧‧半導體晶片
CHP2‧‧‧半導體晶片
DL‧‧‧汲極引線
GL‧‧‧閘極引線
GPj‧‧‧閘極焊墊
GPm‧‧‧閘極焊墊
GPST‧‧‧閘極引線接線柱部
PKG1‧‧‧封裝
PLT1‧‧‧晶片搭載部
PLT2‧‧‧晶片搭載部
SL‧‧‧源極引線
SPj‧‧‧源極焊墊
SPm‧‧‧源極焊墊
SPST‧‧‧源極引線接線柱部
Wds‧‧‧導線
Wgj‧‧‧導線
Wgm‧‧‧導線
Wsm‧‧‧導線

Claims (26)

  1. 一種半導體裝置，其特徵在於具備：常開型接合FET，其係以能帶隙比矽更大之物質為材料，且包含第1閘極電極、第1源極、與第1汲極；及常關型MOSFET，其係以矽為材料，且包含第2閘極電極、第2源極、與第2汲極；且該半導體裝置係將上述接合FET之上述第1源極與上述MOSFET之上述第2汲極電性連接，且將上述接合FET之上述第1閘極電極與上述MOSFET之上述第2源極電性連接之串疊連接者，且包括：(a)第1半導體晶片，其具備：形成有與上述接合FET之上述第1源極電性連接之第1源極焊墊、及與上述接合FET之上述第1閘極電極電性連接之第1閘極焊墊之第1表面；及與上述接合FET之上述第1汲極電性連接，且與上述第1表面相反側之上述第1背面；(b)第2半導體晶片，其具備：形成有與上述MOSFET之上述第2源極電性連接之第2源極焊墊、及與上述MOSFET之上述第2閘極電極電性連接之第2閘極焊墊之第2表面；及與上述MOSFET之上述第2汲極電性連接，且與上述第2表面相反側之上述第2背面；(c)第1晶片搭載部，其具備介隔第1導電性接著材料而搭載有上述第1半導體晶片之第1上表面；(d)汲極引線，其係連結於上述第1晶片搭載部；(e)源極引線，其係與上述汲極引線電性絕緣； (f)閘極引線，其係與上述汲極引線及上述源極引線電性絕緣；(g)第1金屬導體，其係將上述第1半導體晶片之上述第1閘極焊墊與上述源極引線電性連接；及(h)密封體，其係密封上述第1半導體晶片、上述第2半導體晶片、上述第1晶片搭載部之一部分、上述汲極引線之一部分、上述源極引線之一部分、上述閘極引線之一部分、及上述第1金屬導體；且上述第1半導體晶片之上述第1源極焊墊、與上述第2半導體晶片之上述第2背面電性連接；上述第2半導體晶片之上述第2閘極焊墊、與上述閘極引線電性連接；上述第2半導體晶片之上述第2源極焊墊與上述源極引線電性連接；上述第1半導體晶片之上述第1閘極焊墊係以比其他引線更靠近上述源極引線之方式配置。
  2. 如請求項1之半導體裝置，其中上述第2半導體晶片之上述第2閘極焊墊與上述閘極引線係藉由第2金屬導體電性連接；且上述第2半導體晶片之上述第2閘極焊墊係以比上述第2源極焊墊更靠近上述閘極引線之方式配置。
  3. 如請求項2之半導體體裝置，其中上述第1金屬導體之導體寬度係比上述第2金屬導體之導體寬度更寬。
  4. 如請求項2之半導體裝置，其中以使上述第2半導體晶片 之上述第2背面、與上述第1半導體晶片之上述第1源極焊墊對向之方式，於上述第1半導體晶片之上述第1源極焊墊上介隔第2導電性接著材料而搭載有上述第2半導體晶片。
  5. 如請求項4之半導體裝置，其中上述第1半導體晶片係以比其他引線更靠近上述源極引線之方式配置於上述第1晶片搭載部上。
  6. 如請求項4之半導體裝置，其中上述第2半導體晶片之上述第2源極焊墊與上述源極引線藉由第3金屬導體電性連接。
  7. 如請求項6之半導體裝置，其中上述第1金屬導體、上述第2金屬導體、及上述第3金屬導體分別為接合導線。
  8. 如請求項7之半導體裝置，其中上述第3金屬導體之上述接合導線存在複數條。
  9. 如請求項4之半導體裝置，其中上述第1導電性接著材料、及上述第2導電性接著材料係銀漿或焊錫之任一者。
  10. 如請求項6之半導體裝置，其中上述源極引線具備源極引線接線柱部；上述閘極引線具備閘極引線接線柱部；上述第1金屬導體、及上述第3金屬導體連接於上述源極引線接線柱部；且上述第2金屬導體連接於上述閘極引線接線柱部。
  11. 如請求項10之半導體裝置，其中上述源極引線接線柱部 之連接有上述第1金屬導體及上述第3金屬導體之區域、與上述閘極引線接線柱部之連接有上述第2金屬導體之區域，位於比上述第1晶片搭載部之上述第1上表面更高之位置。
  12. 如請求項1之半導體裝置，其中上述密封體具備第1側面及與上述第1側面對向之第2側面；且上述汲極引線、上述閘極引線、及上述源極引線係從上述密封體之上述第1側面突出。
  13. 如請求項12之半導體裝置，其中上述汲極引線配置於上述閘極引線與上述源極引線之間。
  14. 如請求項1之半導體裝置，其中進而包含第2晶片搭載部，其具備搭載有上述第2半導體晶片之第2上表面，且與上述第1晶片搭載部而電性絕緣；且上述第2半導體晶片之上述第2背面與上述第2晶片搭載部之上述第2上表面係經由第3導電性接著材料而電性連接；上述第1半導體晶片之上述第1源極焊墊與上述第2晶片搭載部之上述第2上表面係藉由第4金屬導體電性連接。
  15. 如請求項14之半導體裝置，其中上述第4金屬導體係接合導線。
  16. 如請求項14之半導體裝置，其中上述第1晶片搭載部與 上述第2晶片搭載部之間配置有上述密封體之一部分。
  17. 如請求項1之半導體裝置，其中上述第1晶片搭載部進而具備與上述第1上表面相反側之第1下表面；且上述第1晶片搭載部之上述第1下表面係從上述密封體露出。
  18. 如請求項1之半導體裝置，其中上述密封體具備第1側面及與上述第1側面對向之第2側面；上述閘極引線、及上述源極引線從上述密封體之上述第1側面突出；且上述汲極引線從上述密封體之上述第2側面突出。
  19. 如請求項1之半導體裝置，其中上述第1金屬導體亦電性連接於上述第2半導體晶片之上述第2源極焊墊；且上述第1金屬導體係金屬板。
  20. 如請求項19之半導體裝置，其中上述金屬板係包含銅材料而構成。
  21. 如請求項1之半導體裝置，其中上述接合FET係以碳化矽為材料。
  22. 如請求項1之半導體裝置，其中上述接合FET包含：半導體基板，其成為上述第1汲極；漂移層，其係形成於上述半導體基板之主面上； 複數個溝槽，其係形成於上述漂移層中；上述第1閘極電極，其係形成於上述複數個溝槽之各個側面及底面；通道形成區域，其係包夾於形成於鄰接之溝槽之側面及底面上之閘極電極間；及上述第1源極，其係形成於上述通道形成區域上；且上述通道形成區域之長度係1 μm以上。
  23. 如請求項1之半導體裝置，其中上述接合電晶體包含：半導體基板，其成為上述第1汲極；漂移層，其係形成於上述半導體基板之主面上；複數個溝槽，其係形成於上述漂移層中；上述第1閘極電極，其係形成於上述複數個溝槽之各個側面及底面；通道形成區域，其係包夾於形成於鄰接之上述溝槽之側面及底面上之閘極電極間；及上述第1源極，其係形成於上述通道形成區域上；且上述第1源極之底部、與上述第1閘極電極之底部之間之距離係1 μm以上。
  24. 如請求項1之半導體裝置，其中上述接合電晶體包含：半導體基板，其成為上述第1汲極；漂移層，其係形成於上述半導體基板之主面上；複數個上述第1閘極電極，其係於上述漂移層上相互 分離而形成；及上述第1源極，其係形成於分離形成之上述第1閘極電極之間之上述漂移層之表面上；且上述第1源極之底部、與上述第1閘極電極之底部之間之距離係1 μm以上。
  25. 一種半導體裝置，其特徵在於具備：常開型接合FET，其係以能帶隙比矽更大之物質為材料，且包含第1閘極電極、第1源極、及第1汲極；及常關型MOSFET，其係以矽為材料，且包含第2閘極電極、第2源極、及第2汲極；且該半導體裝置係將上述接合FET之上述第1源極與上述MOSFET之上述第2汲極電性連接，且將上述接合FET之上述第1閘極電極與上述MOSFET之上述第2源極電性連接之串疊連接者，且包括：(a)第1半導體晶片，其具備：形成有與上述接合FET之上述第1源極電性連接之第1源極焊墊、及與上述接合FET之上述第1閘極電極電性連接之第1閘極焊墊之第1表面；及與上述接合FET之上述第1汲極電性連接，且與上述第1表面相反側之上述第1背面；(b)第2半導體晶片，其具備：形成有與上述MOSFET之上述第2源極電性連接之第2源極焊墊、及與上述MOSFET之上述第2閘極電極電性連接之第2閘極焊墊之第2表面；及與上述MOSFET之上述第2汲極電性連接，且與上述第2表面相反側之上述第2背面； (c)第1晶片搭載部，其具備介隔第1導電性接著材料而搭載有上述第1半導體晶片之第1上表面；(d)汲極引線，其係連結於上述第1晶片搭載部；(e)源極引線，其係與上述汲極引線電性絕緣；(f)閘極引線，其係與上述汲極引線及上述源極引線電性絕緣；(g)第1金屬導體，其係將上述第1半導體晶片之上述第1閘極焊墊與上述源極引線電性連接；(h)第2金屬導體，其係將上述第2半導體晶片之上述第2閘極焊墊與上述閘極引線電性連接；(i)第3金屬導體，其係將上述第2半導體晶片之上述第2源極焊墊與上述源極引線電性連接；(j)密封體，其係密封上述第1半導體晶片、上述第2半導體晶片、上述第1晶片搭載部之一部分、上述汲極引線之一部分、上述源極引線之一部分、上述閘極引線之一部分、以及上述第1金屬導體、上述第2金屬導體、及上述第3金屬導體；且以使上述第2半導體晶片之上述第2背面、與上述第1半導體晶片之上述第1源極焊墊對向之方式，於上述第1半導體晶片之上述第1源極焊墊上介隔第2導電性接著材料而搭載有上述第2半導體晶片；上述第1半導體晶片之上述第1閘極焊墊係以比其他引線更靠近上述源極引線之方式配置。
  26. 一種半導體裝置，其特徵在於具備： 常開型接合FET，其係以能帶隙比矽更大之物質為材料，且包含第1閘極電極、第1源極、及第1汲極；及常關型MOSFET，其係以矽為材料，且包含第2閘極電極、第2源極、及第2汲極；且該半導體裝置係將上述接合FET之上述第1源極與上述MOSFET之上述第2汲極電性連接，且將上述接合FET之上述第1閘極電極與上述MOSFET之上述第2源極電性連接之串疊連接者，且包括：(a)第1半導體晶片，其具備：形成有與上述接合FET之上述第1源極電性連接之第1源極焊墊、及與上述接合FET之上述第1閘極電極電性連接之第1閘極焊墊之第1表面；及與上述接合FET之上述第1汲極電性連接，且與上述第1表面相反側之上述第1背面；(b)第2半導體晶片，其具備：形成有與上述MOSFET之上述第2源極電性連接之第2源極焊墊、及與上述MOSFET之上述第2閘極電極電性連接之第2閘極焊墊之第2表面；及與上述MOSFET之上述第2汲極電性連接，且與上述第2表面相反側之上述第2背面；(c)第1晶片搭載部，其具備介隔第1導電性接著材料而搭載有上述第1半導體晶片之第1上表面；(d)第2晶片搭載部，其具備介隔第2導電性接著材料而搭載有上述第2半導體晶片之第2上表面，且與上述第1晶片搭載部電性絕緣；(e)汲極引線，其係連結於上述第1晶片搭載部； (f)源極引線，其係與上述汲極引線電性絕緣；(g)閘極引線，其係與上述汲極引線及上述源極引線電性絕緣；(h)第1金屬導體，其係將上述第1半導體晶片之上述第1閘極焊墊與上述源極引線電性連接；(i)第2金屬導體，其係將上述第2半導體晶片之上述第2閘極焊墊與上述閘極引線電性連接；(j)第3金屬導體，其係將上述第2半導體晶片之上述第2源極焊墊與上述源極引線電性連接；(k)第4金屬導體，其係將上述第1半導體晶片之上述第1源極焊墊與上述第2晶片搭載部之上述第2上表面電性連接；(l)密封體，其係密封上述第1半導體晶片、上述第2半導體晶片、上述第1晶片搭載部之一部分、上述第2晶片搭載部之一部分、上述汲極引線之一部分、上述源極引線之一部分、上述閘極引線之一部分、以及上述第1金屬導體、上述第2金屬導體、上述第3金屬導體、及上述第4金屬導體；且上述第1半導體晶片之上述第1閘極焊墊係以比其他引線更靠近上述源極引線之方式配置。
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