JPWO2013046439A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JPWO2013046439A1 JPWO2013046439A1 JP2013535780A JP2013535780A JPWO2013046439A1 JP WO2013046439 A1 JPWO2013046439 A1 JP WO2013046439A1 JP 2013535780 A JP2013535780 A JP 2013535780A JP 2013535780 A JP2013535780 A JP 2013535780A JP WO2013046439 A1 JPWO2013046439 A1 JP WO2013046439A1
- Authority
- JP
- Japan
- Prior art keywords
- source
- lead
- semiconductor chip
- gate
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 459
- 229910052751 metal Inorganic materials 0.000 claims description 42
- 239000002184 metal Substances 0.000 claims description 42
- 239000004020 conductor Substances 0.000 claims description 35
- 238000007789 sealing Methods 0.000 claims description 35
- 239000000853 adhesive Substances 0.000 claims description 30
- 230000001070 adhesive effect Effects 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 30
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- JPKJQBJPBRLVTM-OSLIGDBKSA-N (2s)-2-amino-n-[(2s,3r)-3-hydroxy-1-[[(2s)-1-[[(2s)-1-[[(2s)-1-[[(2r)-1-(1h-indol-3-yl)-3-oxopropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxobutan-2-yl]-6-iminohexanamide Chemical compound C([C@H](NC(=O)[C@@H](NC(=O)[C@@H](N)CCCC=N)[C@H](O)C)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@H](CC=1C2=CC=CC=C2NC=1)C=O)C1=CC=CC=C1 JPKJQBJPBRLVTM-OSLIGDBKSA-N 0.000 abstract description 133
- 102100031277 Calcineurin B homologous protein 1 Human genes 0.000 abstract description 133
- 241000839426 Chlamydia virus Chp1 Species 0.000 abstract description 133
- 101000777252 Homo sapiens Calcineurin B homologous protein 1 Proteins 0.000 abstract description 133
- 101000943802 Homo sapiens Cysteine and histidine-rich domain-containing protein 1 Proteins 0.000 abstract description 133
- 230000003071 parasitic effect Effects 0.000 abstract description 120
- 238000005516 engineering process Methods 0.000 abstract description 3
- 102100031272 Calcineurin B homologous protein 2 Human genes 0.000 description 115
- 241001510512 Chlamydia phage 2 Species 0.000 description 115
- 101000777239 Homo sapiens Calcineurin B homologous protein 2 Proteins 0.000 description 115
- 230000004048 modification Effects 0.000 description 112
- 238000012986 modification Methods 0.000 description 112
- 238000010586 diagram Methods 0.000 description 46
- 230000015556 catabolic process Effects 0.000 description 41
- 101150095879 PLT2 gene Proteins 0.000 description 36
- 101100494367 Mus musculus C1galt1 gene Proteins 0.000 description 32
- 101150035415 PLT1 gene Proteins 0.000 description 32
- 230000007246 mechanism Effects 0.000 description 31
- 101001046426 Homo sapiens cGMP-dependent protein kinase 1 Proteins 0.000 description 30
- 102100022422 cGMP-dependent protein kinase 1 Human genes 0.000 description 30
- 238000000034 method Methods 0.000 description 22
- 230000008901 benefit Effects 0.000 description 14
- 230000008859 change Effects 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 238000013461 design Methods 0.000 description 10
- 101001046427 Homo sapiens cGMP-dependent protein kinase 2 Proteins 0.000 description 9
- 102100022421 cGMP-dependent protein kinase 2 Human genes 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- 238000013459 approach Methods 0.000 description 7
- 230000009467 reduction Effects 0.000 description 7
- 210000000746 body region Anatomy 0.000 description 6
- 230000006378 damage Effects 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 230000006872 improvement Effects 0.000 description 6
- 101150019736 LGI1 gene Proteins 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 238000005421 electrostatic potential Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 230000009365 direct transmission Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000010338 mechanical breakdown Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/64—Manufacture or treatment of solid state devices other than semiconductor devices, or of parts thereof, not peculiar to a single device provided for in groups H01L31/00 - H10K99/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8083—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04034—Bonding areas specifically adapted for strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/3701—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/3702—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40105—Connecting bonding areas at different heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/40247—Connecting the strap to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73263—Layer and strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10272—Silicon Carbide [SiC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Power Conversion In General (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electronic Switches (AREA)
- Wire Bonding (AREA)
- Inverter Devices (AREA)
Abstract
Description
<本発明者が見出した課題の詳細>
地球環境保全という大きな社会潮流の中で、環境負荷を低減するエレクトロニクス事業の重要性が増している。中でもパワーデバイス(パワー半導体装置)は、鉄道車両、ハイブリッド自動車、電気自動車のインバータやエアコンのインバータ、パソコンなどの民生機器の電源に用いられており、パワーデバイスの性能改善は、インフラシステムや民生機器の電力効率改善に大きく寄与する。電力効率を改善するということは、システムの稼働に必要なエネルギー資源を削減できるということであり、言い換えれば、二酸化炭素の排出量削減、すなわち、環境負荷を低減できる。このため、パワーデバイスの性能改善に向けた研究開発が各社で盛んに行われている。
図2(a)は、カスコード接続した接合FETとMOSFETとをスイッチング素子として利用したインバータを示す回路図である。図2(a)に示すインバータは、電源VCCに直列接続された上アームと下アームとを有している。上アームは、ドレインD1とソースS1との間に接続されたスイッチング素子から構成されている。上アームを構成するスイッチング素子は、カスコード接続された接合FETQ1aとMOSFETQ2aから構成されている。具体的には、接合FETQ1aのドレインDj1がスイッチング素子のドレインD1と接続され、接合FETQ1aのソースSj1がMOSFETQ2aのドレインDm1と接続されている。そして、MOSFETQ2aのソースSm1がスイッチング素子のソースS1と接続されている。また、接合FETQ1aのゲート電極Gj1は、スイッチング素子のソースS1と接続され、MOSFETQ2aのゲート電極Gm1と、スイッチング素子のソースS1との間にはゲート駆動回路(G/D)が接続されている。
図3は、本実施の形態1におけるパッケージ(半導体装置)PKG1の実装構成を示す図である。図3に示すように、本実施の形態1におけるパッケージPKG1は、互いに電気的に絶縁された2つのチップ搭載部PLT1とチップ搭載部PLT2を有している。図3において、右側に配置されている金属プレートがチップ搭載部PLT1を構成し、左側に配置されている金属プレートがチップ搭載部PLT2を構成している。チップ搭載部PLT1は、ドレインリードDLと連結されるように一体的に形成されており、チップ搭載部PLT1とドレインリードDLとは電気的に接続されている。そして、このドレインリードDLを離間して挟むように、ソースリードSLとゲートリードGLが配置されている。具体的には、図3に示すように、ドレインリードDLの右側にソースリードSLが配置され、ドレインリードDLの左側にゲートリードGLが配置されている。これらのドレインリードDL、ソースリードSL、および、ゲートリードGLは、互いに電気的に絶縁されている。そして、ソースリードSLの先端部には、幅広領域からなるソースリードポスト部SPSTが形成され、ゲートリードGLの先端部には、幅広領域からなるゲートリードポスト部GPSTが形成されている。
次に、本変形例1におけるパッケージPKG3の実装構成について説明する。本変形例1では、接合FETを形成した半導体チップと、MOSFETを形成した半導体チップとを積層する構成について説明する。
次に、本変形例2におけるパッケージPKG8の実装構成について説明する。図13は、本変形例2におけるパッケージPKG8の実装構成を示す図である。図13に示すパッケージPKG8の構成は、図3に示すパッケージPKG1の構成とほぼ同様である。異なる点は、パッケージの外形形状である。このように本発明の技術的思想は、図3に示すパッケージPKG1に適用できるだけでなく、図13に示すようなパッケージPKG8にも適用することができる。つまり、スイッチング素子を実装構成するパッケージには、様々な種類の汎用パッケージがあり、本発明の技術的思想は、例えば、図3に示すパッケージPKG1や図13に示すパッケージPKG8に代表される多様な汎用パッケージを改良して実現することができる。具体的に、図13に示すパッケージPKG8においても、例えば、ゲートパッドGPjとソースリードSLとの間の距離を短くすることができるため、ゲートパッドGPjとソースリードSLとを接続するワイヤWgjの長さを短くすることができる。このことから、図13に示すパッケージPKG8においても、ワイヤWgjに存在する寄生インダクタンスを充分に低減できる。このことから、MOSFETへの絶縁耐圧以上の電圧印加を抑制することができ、これによって、カスコード接続されたMOSFETのアバランシェ破壊を効果的に抑制することができる。この結果、図13に示すパッケージPKG8においても、半導体装置の信頼性向上を図ることができる。
次に、本変形例3におけるパッケージPKG10の実装構成について説明する。図17は、本変形例3におけるパッケージPKG10の実装構成を示す図である。図17に示すパッケージPKG10の構成は、図3に示すパッケージPKG1の構成とほぼ同様である。異なる点は、パッケージの外形形状である。このように本発明の技術的思想は、図3に示すパッケージPKG1に適用できるだけでなく、図17に示すようなパッケージPKG10にも適用することができる。つまり、スイッチング素子を実装構成するパッケージには、様々な種類の汎用パッケージがあり、本発明の技術的思想は、例えば、図3に示すパッケージPKG1や図17に示すパッケージPKG10に代表される多様な汎用パッケージを改良して実現することができる。具体的に、図17に示すパッケージPKG10においても、例えば、ゲートパッドGPjとソースリードSLとの間の距離を短くすることができるため、ゲートパッドGPjとソースリードSLとを接続するワイヤWgjの長さを短くすることができる。このことから、図17に示すパッケージPKG10においても、ワイヤWgjに存在する寄生インダクタンスを充分に低減できる。このことから、MOSFETへの絶縁耐圧以上の電圧印加を抑制することができ、これによって、カスコード接続されたMOSFETのアバランシェ破壊を効果的に抑制することができる。この結果、図17に示すパッケージPKG10においても、半導体装置の信頼性向上を図ることができる。
次に、本変形例4におけるパッケージPKG12の実装構成について説明する。図21は、本変形例4におけるパッケージPKG12の実装構成を示す図である。図21に示すパッケージPKG12の構成は、図3に示すパッケージPKG1の構成とほぼ同様である。異なる点は、パッケージの外形形状である。具体的に、本変形例4におけるパッケージPKG12のパッケージ形態は、SOP(Small Outline Package)となっている。このように本発明の技術的思想は、図3に示すパッケージPKG1に適用できるだけでなく、図21に示すようなパッケージPKG12にも適用することができる。つまり、スイッチング素子を実装構成するパッケージには、様々な種類の汎用パッケージがあり、本発明の技術的思想は、例えば、図3に示すパッケージPKG1や図21に示すパッケージPKG12に代表される多様な汎用パッケージを改良して実現することができる。具体的に、図21に示すパッケージPKG12においても、例えば、ゲートパッドGPjとソースリードSLとの間の距離を短くすることができるため、ゲートパッドGPjとソースリードSLとを接続するワイヤWgjの長さを短くすることができる。このことから、図21に示すパッケージPKG12においても、ワイヤWgjに存在する寄生インダクタンスを充分に低減できる。このことから、MOSFETへの絶縁耐圧以上の電圧印加を抑制することができ、これによって、カスコード接続されたMOSFETのアバランシェ破壊を効果的に抑制することができる。この結果、図21に示すパッケージPKG12においても、半導体装置の信頼性向上を図ることができる。
前記実施の形態1では、パッケージ構造に関する工夫点について説明したが、本実施の形態2では、デバイス構造に関する工夫点について説明する。
図25は、本実施の形態2における半導体チップのレイアウト構成を示す図である。以下に示す半導体チップのレイアウト構成は、例えば、シリコンカーバイド(Si)に代表されるシリコン(Si)よりもバンドギャップの大きな物質を材料とする接合FETを形成した半導体チップCHP1上に、シリコン(Si)を材料とするMOSFETを形成した半導体チップCHP2を積層して搭載する例を示している。図25において、半導体チップCHP1は矩形形状をしており、この矩形形状をした半導体チップCHP1の外周領域にターミネーション領域TMjが形成されている。このターミネーション領域TMjは、耐圧を確保するために設けられている領域である。そして、ターミネーション領域TMjの内側領域がアクティブ領域ACTjとなっている。このアクティブ領域ACTjに複数の接合FETが形成されている。
続いて、本実施の形態2における積層半導体チップの他のレイアウト構成について説明する。図28は、本変形例における積層半導体チップのレイアウト構成を示す図である。図28に示すように、半導体チップCHP1は矩形形状をしており、この矩形形状をした半導体チップCHP1の外周領域にターミネーション領域TMjが形成されている。そして、ターミネーション領域TMjの内側領域に、アクティブ領域ACTj、ゲートパッドGPj、および、ソースパッドSPjが形成されている。ここで、本変形例の特徴は、アクティブ領域ACTj、ゲートパッドGPj、および、ソースパッドSPjが平面的に重ならないように配置されている点である。つまり、図28に示すように、接合FETが形成されるアクティブ領域ACTjは、ゲートパッドGPjやソースパッドSPjを避けるように配置されている。そして、ソースパッドSPj上に半導体チップCHP2が搭載されている。
次に、半導体チップCHP2に形成されているMOSFETのデバイス構造の一例について説明する。図31は、本実施の形態2におけるMOSFETのデバイス構造の一例を示す断面図である。図31に示すように、例えば、n型不純物を導入したシリコンからなる半導体基板SUBmの裏面には、例えば、金膜からなるドレイン電極DEmが形成されている一方、半導体基板SUBmの主面側には、n型半導体領域からなるドリフト層DFTmが形成されている。ドリフト層DFTmには、p型半導体領域からなるボディ領域PRが形成されており、このボディ領域PRに内包されるように、n型半導体領域からなるソース領域SRが形成されている。このソース領域SRとドリフト層DFTmで挟まれた、ボディ領域PRの表面領域がチャネル形成領域として機能する。そして、ソース領域SRとボディ領域PRの両方に電気的に接続するようにソース電極SEが形成されている。さらに、チャネル形成領域上を含むドリフト層DFTmの表面には、例えば、酸化シリコン膜からなるゲート絶縁膜GOXが形成されており、このゲート絶縁膜GOX上にゲート電極Gが形成されている。
次に、本発明者が見出した新たな課題について説明する。図32は、カスコード接続されたスイッチング素子における電流経路を示す図である。図32(a)は、オン時の電流経路を示す図であり、図32(b)は、オフ時に流れるリーク電流の電流経路を示す図である。図32(a)に示すように、オン時においては、定格電流Idが接合FETQ1のドレインからMOSFETQ2のソースへ流れる。すなわち、カスコード接続されたスイッチング素子のドレインDからソースSに向って定格電流Idが流れる。このとき、MOSFETQ2がカットオフされる前のMOSFETQ2のドレイン電圧(中間ノードSeの電圧)は、MOSFETQ2のオン抵抗と定格電流Idの積から求めることができる。例えば、オン抵抗が10mΩで、定格電流Idが40Aであれば、中間ノードSeの電圧は0.4Vである。この中間ノードSeの電圧は、MOSFETQ2のドレイン電圧であるとともに、接合FETQ1のソース電圧でもあるため、接合FETQ1のソース電圧を基準とした接合FETQ1のゲート電圧である電圧Vgsは、−0.4Vである。
図33は、本実施の形態2における接合FETのデバイス構造を示す断面図である。図33に示すように、本実施の形態2における接合FETは、半導体基板SUBjを有し、この半導体基板SUBjの裏面にドレイン電極DEjが形成されている。一方、半導体基板SUBjの裏面とは反対側の主面側には、ドリフト層DFTjが形成されており、このドリフト層DFTjには、複数のトレンチTRが形成されている。そして、複数のトレンチTRのそれぞれの側面および底面には、ゲート電極GE(ゲート領域ともいう)が形成されており、隣り合うトレンチTRの側面および底面に形成されたゲート電極GEに挟まれるようにチャネル形成領域が形成されている。このチャネル形成領域の上部にはソース領域SRが形成されている。このように構成されている接合FETでは、ゲート電極GEに印加する電圧を制御することにより、ゲート電極GEからの空乏層の延びを制御する。これにより、互いに隣り合うゲート電極GEから延びる空乏層が繋がるとチャネル形成領域が消失してオフ状態が実現される一方、互いに隣り合うゲート電極GEから延びる空乏層が繋がらない場合には、チャネル形成領域が形成されてオン状態が実現される。
ACTm アクティブ領域
CHP1 半導体チップ
CHP2 半導体チップ
CL チャネル長
CLP クリップ
D ドレイン
D1 ドレイン
D2 ドレイン
DEj ドレイン電極
DEm ドレイン電極
DFTj ドリフト層
DFTm ドリフト層
Dj1 ドレイン
Dj2 ドレイン
DL ドレインリード
Dm ドレイン
Dm1 ドレイン
Dm2 ドレイン
G ゲート電極
GE ゲート電極
Gj ゲート電極
Gj1 ゲート電極
Gj2 ゲート電極
GL ゲートリード
Gm ゲート電極
Gm1 ゲート電極
Gm2 ゲート電極
GOX ゲート絶縁膜
GPj ゲートパッド
GPm ゲートパッド
GPST ゲートリードポスト部
Id 定格電流
Idl リーク電流
IL1 絶縁膜
IL2 絶縁膜
Lgi1 寄生インダクタンス
Lgi2 寄生インダクタンス
LL 負荷インダクタンス
Ls 寄生インダクタンス
Lse1 寄生インダクタンス
Lse2 寄生インダクタンス
MR 封止体
PKG1 パッケージ
PKG2 パッケージ
PKG3 パッケージ
PKG4 パッケージ
PKG5 パッケージ
PKG6 パッケージ
PKG7 パッケージ
PKG8 パッケージ
PKG9 パッケージ
PKG10 パッケージ
PKG11 パッケージ
PKG12 パッケージ
PKG13 パッケージ
PLT チップ搭載部
PLT1 チップ搭載部
PLT2 チップ搭載部
PR ボディ領域
Q1 接合FET
Q1a 接合FET
Q1b 接合FET
Q2 MOSFET
Q2a MOSFET
Q2b MOSFET
S ソース
S1 ソース
S2 ソース
SE ソース電極
Se 中間ノード
Sj ソース
Sj1 ソース
Sj2 ソース
SL ソースリード
Sm ソース
Sm1 ソース
Sm2 ソース
SPj ソースパッド
SPm ソースパッド
SPST ソースリードポスト部
SR ソース領域
SUBj 半導体基板
SUBm 半導体基板
TMj ターミネーション領域
TMm ターミネーション領域
TR トレンチ
Vak 電圧
Vdsu 電圧
Vdsmu 電圧
Vdsmd 電圧
Wds ワイヤ
Wgj ワイヤ
Wgm ワイヤ
Wsm ワイヤ
Claims (26)
- シリコンよりもバンドギャップの大きな物質を材料とし、第1ゲート電極と、第1ソースと、第1ドレインと、を有するノーマリオン型の接合FETと、
シリコンを材料とし、第2ゲート電極と、第2ソースと、第2ドレインと、を有するノーマリオフ型のMOSFETと、を備え、
前記接合FETの前記第1ソースと、前記MOSFETの前記第2ドレインとを電気的に接続し、かつ、前記接合FETの前記第1ゲート電極と、前記MOSFETの前記第2ソースとを電気的に接続するカスコード接続された半導体装置であって、
(a)前記接合FETの前記第1ソースと電気的に接続された第1ソースパッド、および、前記接合FETの前記第1ゲート電極と電気的に接続された第1ゲートパッドが形成された第1表面と、前記接合FETの前記第1ドレインと電気的に接続され、前記第1表面とは反対側の前記第1裏面と、を有する第1半導体チップと、
(b)前記MOSFETの前記第2ソースと電気的に接続された第2ソースパッド、および、前記MOSFETの前記第2ゲート電極と電気的に接続された第2ゲートパッドが形成された第2表面と、前記MOSFETの前記第2ドレインと電気的に接続され、前記第2表面とは反対側の前記第2裏面と、を有する第2半導体チップと、
(c)前記第1半導体チップが第1導電性接着材を介して搭載された第1上面を有する第1チップ搭載部と、
(d)前記第1チップ搭載部に連結されたドレインリードと、
(e)前記ドレインリードとは電気的に絶縁されたソースリードと、
(f)前記ドレインリード、および、前記ソースリードと電気的に絶縁されたゲートリードと、
(g)前記第1半導体チップの前記第1ゲートパッドと前記ソースリードとを電気的に接続する第1金属導体と、
(h)前記第1半導体チップ、前記第2半導体チップ、前記第1チップ搭載部の一部、前記ドレインリードの一部、前記ソースリードの一部、前記ゲートリードの一部、および前記第1金属導体を封止する封止体と、を有し、
前記第1半導体チップの前記第1ソースパッドと、前記第2半導体チップの前記第2裏面とは電気的に接続されており、
前記第2半導体チップの前記第2ゲートパッドと、前記ゲートリードとは電気的に接続されており、
前記第2半導体チップの前記第2ソースパッドと前記ソースリードとは電気的に接続されており、
前記第1半導体チップの前記第1ゲートパッドは、他のリードよりも前記ソースリードに近くなるように配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第2半導体チップの前記第2ゲートパッドと前記ゲートリードとは、第2金属導体により電気的に接続されており、
前記第2半導体チップの前記第2ゲートパッドは、前記第2ソースパッドよりも前記ゲートリードに近くなるように配置されていることを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第1金属導体の導体幅は、第2金属導体の導体幅よりも広いことを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第2半導体チップの前記第2裏面と、前記第1半導体チップの前記第1ソースパッドとが対向するように、前記第1半導体チップの前記第1ソースパッド上に前記第2半導体チップが第2導電性接着材を介して搭載されていることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記第1半導体チップは、他のリードよりも前記ソースリードに近くなるように前記第1チップ搭載部上に配置されていることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において
前記第2半導体チップの前記第2ソースパッドと前記ソースリードとは第3金属導体により電気的に接続されていることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記第1金属導体、前記第2金属導体、および、前記第3金属導体は、それぞれ、ボンディングワイヤであることを特徴とする半導体装置。 - 請求項7に記載の半導体装置において、
前記第3金属導体の前記ボンディングワイヤは、複数本存在することを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記第1導電性接着材、および、前記第2導電性接着材は、銀ペーストもしくは半田のいずれかであることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記ソースリードは、ソースリードポスト部を有し、
前記ゲートリードは、ゲートリードポスト部を有し、
前記第1金属導体、および、前記第3金属導体は、前記ソースリードポスト部に接続されており、
前記第2金属導体は、前記ゲートリードポスト部に接続されていることを特徴とする半導体装置。 - 請求項10に記載の半導体装置において、
前記ソースリードポスト部の前記第1金属体および前記第3金属体が接続されている領域と、前記ゲートリードポスト部の前記第2金属導体が接続されている領域は、前記第1チップ搭載部の前記第1上面よりも高い位置に位置することを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記封止体は、第1側面と前記第1側面と対向する第2側面とを有し、
前記ドレインリード、前記ゲートリード、および、前記ソースリードは、前記封止体の前記第1側面から突出していることを特徴とする半導体装置。 - 請求項12に記載の半導体装置において、
前記ドレインリードは、前記ゲートリードと前記ソースリードとの間に配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第2半導体チップが搭載された第2上面を有し、前記第1チップ搭載部とは電気的に絶縁された第2チップ搭載部をさらに備え、
前記第2半導体チップの前記第2裏面と前記第2チップ搭載部の前記第2上面とは第3導電性接着材を介して電気的に接続されており、
前記第1半導体チップの前記第1ソースパッドと前記第2チップ搭載部の前記第2上面とは第4金属導体により電気的に接続されていることを特徴とする半導体装置。 - 請求項14に記載の半導体装置において、
前記第4金属導体はボンディングワイヤであることを特徴とする半導体装置。 - 請求項14に記載の半導体装置において、
前記第1チップ搭載部と前記第2チップ搭載部との間には、前記封止体の一部が配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1チップ搭載部は前記第1上面とは反対側の第1下面をさらに有し、
前記第1チップ搭載部の前記第1下面は、前記封止体から露出していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記封止体は、第1側面と前記第1側面と対向する第2側面とを有し、
前記ゲートリード、および、前記ソースリードは、前記封止体の前記第1側面から突出し、
前記ドレインリードは、前記封止体の前記第2側面から突出していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1金属導体は、前記第2半導体チップの前記第2ソースパッドにも電気的に接続されており、
前記第1金属導体は、金属板であることを特徴とする半導体装置。 - 請求項19に記載の半導体装置において、
前記金属板は銅材から構成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記接合FETは、シリコンカーバイドを材料としていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記接合トランジスタは、
前記第1ドレインとなる半導体基板と、
前記半導体基板の主面に形成されたドリフト層と、
前記ドリフト層に形成された複数のトレンチと、
前記複数のトレンチのそれぞれの側面および底面に形成された前記第1ゲート電極と、
隣り合うトレンチの側面および底面に形成されたゲート電極に挟まれたチャネル形成領域と、
前記チャネル形成領域上に形成された前記第1ソースと、を有し、
前記チャネル形成領域の長さは、1μm以上であることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記接合トランジスタは、
前記第1ドレインとなる半導体基板と、
前記半導体基板の主面に形成されたドリフト層と、
前記ドリフト層に形成された複数のトレンチと、
前記複数のトレンチのそれぞれの側面および底面に形成された前記第1ゲート電極と、
隣り合う前記トレンチの側面および底面に形成されたゲート電極に挟まれたチャネル形成領域と、
前記チャネル形成領域上に形成された前記第1ソースと、を有し、
前記第1ソースの底部と、前記第1ゲート電極の底部との間の距離は、1μm以上であることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記接合トランジスタは、
前記第1ドレインとなる半導体基板と、
前記半導体基板の主面に形成されたドリフト層と、
前記ドリフト層に互いに離間して形成された複数の前記第1ゲート電極と、
離間して形成された前記第1ゲート電極の間の前記ドリフト層の表面に形成された前記第1ソースと、を有し、
前記第1ソースの底部と、前記第1ゲート電極の底部との間の距離は、1μm以上であることを特徴とする半導体装置。 - シリコンよりもバンドギャップの大きな物質を材料とし、第1ゲート電極と、第1ソースと、第1ドレインと、を有するノーマリオン型の接合FETと、
シリコンを材料とし、第2ゲート電極と、第2ソースと、第2ドレインと、を有するノーマリオフ型のMOSFETと、を備え、
前記接合FETの前記第1ソースと、前記MOSFETの前記第2ドレインとを電気的に接続し、かつ、前記接合FETの前記第1ゲート電極と、前記MOSFETの前記第2ソースとを電気的に接続するカスコード接続された半導体装置であって、
(a)前記接合FETの前記第1ソースと電気的に接続された第1ソースパッド、および、前記接合FETの前記第1ゲート電極と電気的に接続された第1ゲートパッドが形成された第1表面と、前記接合FETの前記第1ドレインと電気的に接続され、前記第1表面とは反対側の前記第1裏面と、を有する第1半導体チップと、
(b)前記MOSFETの前記第2ソースと電気的に接続された第2ソースパッド、および、前記MOSFETの前記第2ゲート電極と電気的に接続された第2ゲートパッドが形成された第2表面と、前記MOSFETの前記第2ドレインと電気的に接続され、前記第2表面とは反対側の前記第2裏面と、を有する第2半導体チップと、
(c)前記第1半導体チップが第1導電性接着材を介して搭載された第1上面を有する第1チップ搭載部と、
(d)前記第1チップ搭載部に連結されたドレインリードと、
(e)前記ドレインリードとは電気的に絶縁されたソースリードと、
(f)前記ドレインリード、および、前記ソースリードと電気的に絶縁されたゲートリードと、
(g)前記第1半導体チップの前記第1ゲートパッドと前記ソースリードとを電気的に接続する第1金属導体と、
(h)前記第2半導体チップの前記第2ゲートパッドと前記ゲートリードとを電気的に接続する第2金属導体と、
(i)前記第2半導体チップの前記第2ソースパッドと前記ソースリードとを電気的に接続する第3金属導体と、
(j)前記第1半導体チップ、前記第2半導体チップ、前記第1チップ搭載部の一部、前記ドレインリードの一部、前記ソースリードの一部、前記ゲートリードの一部、および前記第1金属導体、前記第2金属導体、および、前記第3金属導体を封止する封止体と、を有し、
前記第2半導体チップの前記第2裏面と、前記第1半導体チップの前記第1ソースパッドとが対向するように、前記第1半導体チップの前記第1ソースパッド上に前記第2半導体チップが第2導電性接着材を介して搭載されており、
前記第1半導体チップの前記第1ゲートパッドは、他のリードよりも前記ソースリードに近くなるように配置されていることを特徴とする半導体装置。 - シリコンよりもバンドギャップの大きな物質を材料とし、第1ゲート電極と、第1ソースと、第1ドレインと、を有するノーマリオン型の接合FETと、
シリコンを材料とし、第2ゲート電極と、第2ソースと、第2ドレインと、を有するノーマリオフ型のMOSFETと、を備え、
前記接合FETの前記第1ソースと、前記MOSFETの前記第2ドレインとを電気的に接続し、かつ、前記接合FETの前記第1ゲート電極と、前記MOSFETの前記第2ソースとを電気的に接続するカスコード接続された半導体装置であって、
(a)前記接合FETの前記第1ソースと電気的に接続された第1ソースパッド、および、前記接合FETの前記第1ゲート電極と電気的に接続された第1ゲートパッドが形成された第1表面と、前記接合FETの前記第1ドレインと電気的に接続され、前記第1表面とは反対側の前記第1裏面と、を有する第1半導体チップと、
(b)前記MOSFETの前記第2ソースと電気的に接続された第2ソースパッド、および、前記MOSFETの前記第2ゲート電極と電気的に接続された第2ゲートパッドが形成された第2表面と、前記MOSFETの前記第2ドレインと電気的に接続され、前記第2表面とは反対側の前記第2裏面と、を有する第2半導体チップと、
(c)前記第1半導体チップが第1導電性接着材を介して搭載された第1上面を有する第1チップ搭載部と、
(d)前記第2半導体チップが第2導電性接着材を介して搭載された第2上面を有し、前記第1チップ搭載部とは電気的に絶縁された第2チップ搭載部と、
(e)前記第1チップ搭載部に連結されたドレインリードと、
(f)前記ドレインリードとは電気的に絶縁されたソースリードと、
(g)前記ドレインリード、および、前記ソースリードと電気的に絶縁されたゲートリードと、
(h)前記第1半導体チップの前記第1ゲートパッドと前記ソースリードとを電気的に接続する第1金属導体と、
(i)前記第2半導体チップの前記第2ゲートパッドと前記ゲートリードとを電気的に接続する第2金属導体と、
(j)前記第2半導体チップの前記第2ソースパッドと前記ソースリードとを電気的に接続する第3金属導体と、
(k)前記第1半導体チップの前記第1ソースパッドと前記第2チップ搭載部の前記第2上面とを電気的に接続する第4金属導体と、
(l)前記第1半導体チップ、前記第2半導体チップ、前記第1チップ搭載部の一部、前記第2チップ搭載部の一部、前記ドレインリードの一部、前記ソースリードの一部、前記ゲートリードの一部、および前記第1金属導体、前記第2金属導体、前記第3金属導体、および、前記第4金属導体を封止する封止体と、を有し、
前記第1半導体チップの前記第1ゲートパッドは、他のリードよりも前記ソースリードに近くなるように配置されていることを特徴とする半導体装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2011/072584 WO2013046439A1 (ja) | 2011-09-30 | 2011-09-30 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014262313A Division JP5824135B2 (ja) | 2014-12-25 | 2014-12-25 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP5676771B2 JP5676771B2 (ja) | 2015-02-25 |
JPWO2013046439A1 true JPWO2013046439A1 (ja) | 2015-03-26 |
Family
ID=47994544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013535780A Active JP5676771B2 (ja) | 2011-09-30 | 2011-09-30 | 半導体装置 |
Country Status (7)
Country | Link |
---|---|
US (2) | US9263435B2 (ja) |
EP (2) | EP3460832A1 (ja) |
JP (1) | JP5676771B2 (ja) |
KR (2) | KR101672605B1 (ja) |
CN (2) | CN107104057B (ja) |
TW (2) | TWI538161B (ja) |
WO (1) | WO2013046439A1 (ja) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9735238B2 (en) * | 2014-01-15 | 2017-08-15 | Virginia Tech Intellectual Properties, Inc. | Avoiding internal switching loss in soft switching cascode structure device |
US10043738B2 (en) | 2014-01-24 | 2018-08-07 | Silergy Semiconductor Technology (Hangzhou) Ltd | Integrated package assembly for switching regulator |
WO2015114728A1 (ja) * | 2014-01-28 | 2015-08-06 | 株式会社日立製作所 | パワーモジュール、電力変換装置、および鉄道車両 |
JP6374225B2 (ja) * | 2014-06-02 | 2018-08-15 | ルネサスエレクトロニクス株式会社 | 半導体装置および電子装置 |
JP6223918B2 (ja) * | 2014-07-07 | 2017-11-01 | 株式会社東芝 | 半導体装置 |
US10290566B2 (en) * | 2014-09-23 | 2019-05-14 | Infineon Technologies Austria Ag | Electronic component |
CN105529939B (zh) * | 2014-09-30 | 2018-01-23 | 万国半导体股份有限公司 | 单独封装同步整流器 |
JP2016139997A (ja) | 2015-01-28 | 2016-08-04 | 株式会社東芝 | 半導体装置 |
JP2016213327A (ja) * | 2015-05-08 | 2016-12-15 | シャープ株式会社 | 半導体装置 |
WO2017043611A1 (ja) * | 2015-09-10 | 2017-03-16 | 古河電気工業株式会社 | パワーデバイス |
JP6631114B2 (ja) * | 2015-09-17 | 2020-01-15 | 富士電機株式会社 | 半導体装置及び半導体装置の計測方法 |
FR3059155B1 (fr) * | 2016-11-23 | 2018-11-16 | Exagan | Circuit integre forme d'un empilement de deux puces connectees en serie |
CN106951586B (zh) * | 2017-02-15 | 2020-05-15 | 上海集成电路研发中心有限公司 | 一种考虑温度效应的射频mos器件的建模方法 |
CN109429529B (zh) * | 2017-06-19 | 2022-06-21 | 新电元工业株式会社 | 半导体装置 |
JP6769458B2 (ja) * | 2017-07-26 | 2020-10-14 | 株式会社デンソー | 半導体装置 |
JP6822939B2 (ja) | 2017-11-30 | 2021-01-27 | 株式会社東芝 | 半導体装置 |
US10886201B2 (en) * | 2018-02-15 | 2021-01-05 | Epistar Corporation | Power device having a substrate with metal layers exposed at surfaces of an insulation layer and manufacturing method thereof |
DE102018115110B3 (de) * | 2018-06-22 | 2019-09-26 | Infineon Technologies Ag | Siliziumcarbid-halbleitervorrichtung |
JP2018195838A (ja) * | 2018-07-19 | 2018-12-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP7024688B2 (ja) | 2018-11-07 | 2022-02-24 | 株式会社デンソー | 半導体装置 |
CN111199958A (zh) * | 2018-11-16 | 2020-05-26 | 苏州东微半导体有限公司 | 半导体功率器件 |
EP3809458A1 (en) * | 2019-10-15 | 2021-04-21 | Nexperia B.V. | Half-bridge semiconductor device |
JP2022146340A (ja) * | 2021-03-22 | 2022-10-05 | 株式会社東芝 | 半導体装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003318344A (ja) * | 2002-04-22 | 2003-11-07 | Sanyo Electric Co Ltd | 半導体装置 |
US20040130021A1 (en) * | 2002-10-31 | 2004-07-08 | International Rectifier Corporation | High power silicon carbide and silicon semiconductor device package |
JP2006114674A (ja) * | 2004-10-14 | 2006-04-27 | Toshiba Corp | 半導体装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19610135C1 (de) | 1996-03-14 | 1997-06-19 | Siemens Ag | Elektronische Einrichtung, insbesondere zum Schalten elektrischer Ströme, für hohe Sperrspannungen und mit geringen Durchlaßverlusten |
JP3046017B1 (ja) | 1999-02-25 | 2000-05-29 | インターナショナル・レクチファイヤー・コーポレーション | コパッケ―ジmos―ゲ―トデバイスおよび制御ic |
JP2002208673A (ja) | 2001-01-10 | 2002-07-26 | Mitsubishi Electric Corp | 半導体装置およびパワーモジュール |
JP5358882B2 (ja) | 2007-02-09 | 2013-12-04 | サンケン電気株式会社 | 整流素子を含む複合半導体装置 |
JP2009071059A (ja) * | 2007-09-13 | 2009-04-02 | Sanyo Electric Co Ltd | 半導体装置 |
JP2009231805A (ja) | 2008-02-29 | 2009-10-08 | Renesas Technology Corp | 半導体装置 |
JP5844956B2 (ja) | 2009-03-05 | 2016-01-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
DE102009046258B3 (de) * | 2009-10-30 | 2011-07-07 | Infineon Technologies AG, 85579 | Leistungshalbleitermodul und Verfahren zum Betrieb eines Leistungshalbleitermoduls |
US8575695B2 (en) * | 2009-11-30 | 2013-11-05 | Alpha And Omega Semiconductor Incorporated | Lateral super junction device with high substrate-drain breakdown and built-in avalanche clamp diode |
JP5012930B2 (ja) * | 2010-02-15 | 2012-08-29 | 株式会社デンソー | ハイブリッドパワーデバイス |
-
2011
- 2011-09-30 US US14/348,048 patent/US9263435B2/en active Active
- 2011-09-30 EP EP18203412.4A patent/EP3460832A1/en not_active Withdrawn
- 2011-09-30 EP EP11873214.8A patent/EP2763160B1/en active Active
- 2011-09-30 CN CN201710264506.7A patent/CN107104057B/zh active Active
- 2011-09-30 JP JP2013535780A patent/JP5676771B2/ja active Active
- 2011-09-30 KR KR1020147008420A patent/KR101672605B1/ko active Application Filing
- 2011-09-30 CN CN201180073865.5A patent/CN103843122B/zh active Active
- 2011-09-30 KR KR1020167029941A patent/KR101708162B1/ko active IP Right Grant
- 2011-09-30 WO PCT/JP2011/072584 patent/WO2013046439A1/ja active Application Filing
-
2012
- 2012-08-14 TW TW101129402A patent/TWI538161B/zh active
- 2012-08-14 TW TW105110663A patent/TWI614877B/zh active
-
2016
- 2016-02-07 US US15/017,666 patent/US9502388B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003318344A (ja) * | 2002-04-22 | 2003-11-07 | Sanyo Electric Co Ltd | 半導体装置 |
US20040130021A1 (en) * | 2002-10-31 | 2004-07-08 | International Rectifier Corporation | High power silicon carbide and silicon semiconductor device package |
JP2006114674A (ja) * | 2004-10-14 | 2006-04-27 | Toshiba Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
KR101708162B1 (ko) | 2017-02-17 |
EP2763160A4 (en) | 2016-01-13 |
CN107104057A (zh) | 2017-08-29 |
JP5676771B2 (ja) | 2015-02-25 |
EP2763160B1 (en) | 2018-12-12 |
KR20160127176A (ko) | 2016-11-02 |
US9502388B2 (en) | 2016-11-22 |
KR101672605B1 (ko) | 2016-11-03 |
US20140231829A1 (en) | 2014-08-21 |
TW201628161A (zh) | 2016-08-01 |
EP3460832A1 (en) | 2019-03-27 |
TW201314866A (zh) | 2013-04-01 |
US9263435B2 (en) | 2016-02-16 |
CN107104057B (zh) | 2019-08-13 |
WO2013046439A1 (ja) | 2013-04-04 |
TWI614877B (zh) | 2018-02-11 |
EP2763160A1 (en) | 2014-08-06 |
CN103843122B (zh) | 2017-04-05 |
US20160155726A1 (en) | 2016-06-02 |
KR20140082679A (ko) | 2014-07-02 |
TWI538161B (zh) | 2016-06-11 |
CN103843122A (zh) | 2014-06-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5676771B2 (ja) | 半導体装置 | |
US10607978B2 (en) | Semiconductor device and electronic apparatus | |
US11037847B2 (en) | Method of manufacturing semiconductor module and semiconductor module | |
US9048119B2 (en) | Semiconductor device with normally off and normally on transistors | |
US20180138828A1 (en) | Semiconductor module | |
US10049968B2 (en) | Semiconductor device | |
JP5824135B2 (ja) | 半導体装置 | |
US10217765B2 (en) | Semiconductor integrated circuit | |
US10727228B2 (en) | Stacked integrated circuit | |
JP2018195838A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141202 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141225 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5676771 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R157 | Certificate of patent or utility model (correction) |
Free format text: JAPANESE INTERMEDIATE CODE: R157 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |