TW201248808A - Semiconductor device and manufacturing method thereof, and semiconductor module using the same - Google Patents

Semiconductor device and manufacturing method thereof, and semiconductor module using the same Download PDF

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Publication number
TW201248808A
TW201248808A TW101104374A TW101104374A TW201248808A TW 201248808 A TW201248808 A TW 201248808A TW 101104374 A TW101104374 A TW 101104374A TW 101104374 A TW101104374 A TW 101104374A TW 201248808 A TW201248808 A TW 201248808A
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TW
Taiwan
Prior art keywords
semiconductor
semiconductor device
electrode
resin layer
wiring
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TW101104374A
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English (en)
Inventor
Takeshi Watanabe
Takashi Imoto
Naoto Takebe
Yuuki Kuro
Yusuke Doumae
Katunori Shibuya
Yoshimune Kodama
Yuji Karakane
Masatoshi Kawato
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Toshiba Kk
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Publication of TW201248808A publication Critical patent/TW201248808A/zh

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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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Description

201248808 六、發明說明： 本發明主張JP2011-106875 C申請日：2011年5月12 曰）之優先權，內容亦引用其全部內容。 【發明所屬之技術領域】 揭示之實施形態通常關於半導體裝置及其製造方法’ 以及使用其之半導體模組。 【先前技術】 爲實現半導體裝置之小型化或高密度安裝化，在1個 封裝內積層複數個半導體晶片而成的樹脂密封之堆疊型多 晶片封裝被實用化。爲求多晶片封裝之更進一步高集積化 或高機能化，而於配線基板上將複數個半導體晶片安裝、 實施樹脂密封而成半導體封裝，將該半導體封裝積層爲立 體構造，亦即具有POP ( Package on Package)構造的半 導體模組之實用化被進展著。 於具有POP構造的半導體模組，在複數個半導體封 裝間之連接，係使用設於配線基板上的錫球構成之突起電 極（凸塊電極）或設於密封樹脂層內的貫通電極。突起電 極和貫通電極相比，因爲形成容易，有助於降低POP構 造之半導體模組之製造成本。藉由突起電極連接複數個半 導體封裝間時，突起電極係配置於對半導體晶片實施密封 的密封樹脂層周圍，其高度需要設爲下段側之半導體封裝 之密封樹脂層之高度以上。因此，突起電極（錫球）之直 -5- 201248808 徑或形成間距有變大之傾向。此成爲妨礙半導體模組小型 化、或不利於輸出入數之增大、半導體封裝中之半導體晶 片之積層數增加之對策的主要原因。 【發明內容】 [發明所欲解決之課題] 本發明之實施形態目的在於提供，不妨礙半導體模組 之小型化或輸出入數之增多、或半導體晶片之積層數之增 加等，可以低成本連接POP構造中之上下之裝置間的半 導體裝置及其之製造方法，以及使用該半導體裝置的半導 體模組。 [解決課題的手段] 依據1個實施形態提供的半導體裝置，係具備：具有 第1面及第2面的配線基板，該第1面係具備晶片搭載區 域及第1配線層，該第2面係具備電連接於第1配線層的 第2配線層：半導體晶片，被搭載於配線基板之上述第1 面，具有電極焊墊；連接構件，用於電連接第1配線層與 電極焊墊；第1突起電極，被設於配線基板之第1面，被 電連接於第1配線層：第2突起電極，被設於配線基板之 第2面，被電連接於第2配線層；及密封樹脂層，以將半 導體晶片連同連接構件及第1突起電極予以密封的方式， 被設於配線基板之第1面上，而且具有使第1突起電極之 一部分露出的凹部。 201248808 依據本發明之實施形態，可以提供在不妨礙半導體模 組之小型化或輸出入數之增多、或半導體晶片之積層數之 增加等之情況下，能以低成本連接POP構造中之上下之 裝置間的半導體裝置及其之製造方法，以及使用該半導體 裝置的半導體模組。 【實施方式】 參照圖面說明實施形態之半導體裝置及其製造方法、 以及使用其之半導體模組。圖1係表示第1實施形態之半 導體裝置之斷面圖。圖2係表示第2實施形態之半導體裝 置之斷面圖。彼等圖所示半導體裝置1，係具備配線基板 2 °配線基板2，係具有成爲晶片搭載面的第1面（上面 )2a，及成爲外部連接面的第2面（下面）2b。配線基板 2之第1面2a，係具有設於中央附近的晶片搭載區域。 於配線基板2之第1面2a設置第1配線層3。於配 線基板2第2面2b設置第2配線層4。必要時可於配線 基板2內部設置配線層。第1配線層3與第2配線層4， 係經由設於配線基板2內的通孔5被電連接。第1配線層 3,係具有配置於晶片搭載區域之周圍的第1連接焊墊3a ’及較第1連接焊墊3 a更朝外周側配置的第2連接焊墊 3b。第2配線層4，係具有以和第2連接焊墊3b成對應 方式配置的第3連接焊墊4a。第1連接焊墊3a，係作爲 對搭載於配線基板2上之半導體晶片之連接部的機能。第 2及第3連接焊墊3b、4a，係作爲後述突起電極之形成部 201248808 之機能者，被設於除去晶片搭載區域及其所對應的區域以 外的外周區域》 於配線基板2之晶片搭載區域搭載著半導體晶片6。 半導體晶片6對配線基板2之搭載數未特別限定，可爲1 個或2個以上之任一。圖1及圖2係表示在配線基板2晶 片搭載區域積層、搭載複數個半導體晶片6、6…的半導 體裝置1。半導體晶片6之具體例可爲例如NAND型快閃 記憶體等之半導體記憶體晶片，但不限定於此。複數個半 導體晶片6、6…，分別具有沿著1個外形邊配列而成的 電極焊墊6 a。 複數個半導體晶片6，係以電極焊墊6a露出的方式 被積層爲階梯狀。於圖1及圖2所示半導體裝置1，複數 個半導體晶片6係區分爲第1晶片群7與第2晶片群8。 第1及第2晶片群7、8，係分別由4個之半導體晶片6 構成。構成第1晶片群7的4個之半導體晶片6，係於配 線基板2之晶片搭載區域上依序被積層爲階梯狀。構成第 2晶片群8的4個之半導體晶片6，係於第1晶片群7上 依序被積層爲階梯狀。第2晶片群8之階梯方向，係設爲 第1晶片群8之階梯方向之逆向。第1晶片群7與第2晶 片群8之焊墊配列邊之方向被設爲逆向。 半導體晶片6之積層形狀，不限定於上述階梯形狀， 亦可將複數個半導體晶片6僅朝一方向積層爲階梯狀，或 可使焊墊配列邊相互成爲逆向而將複數個半導體晶片6予 以積層等之積層形狀。複數個半導體晶片6，亦可使外形 • 8 - 201248808 邊對齊予以積層。此情況下，作爲後述連接構件的金屬導 線’係被埋入用以接著複數個半導體晶片6間的接著劑層 內。利用半導體晶片6內所設置的貫通電極，藉由微細的 焊錫凸塊實施半導體晶片6間之連接、積層亦可。半導體 晶片6之積層形狀或積層數未特別限定。 構成第1晶片群7的複數個半導體晶片6之電極焊墊 6 a，係經由金屬導線（Au導線等）9電連接於位於其附近 的第1連接焊墊3a。同樣，構成第2晶片群8的複數個 半導體晶片6之電極焊墊6a，係經由金屬導線9電連接 於位於其附近的第1連接焊墊3a。在構成第1及第2晶 片群7、8的半導體晶片6，電氣特性或信號特性相等的 電極焊墊6a可以藉由金屬導線9依序連接。用於實施半 導體晶片6之電極焊墊6a與第1連接焊墊3a之電連接的 連接構件，不限定於金屬導線9，亦可爲藉由噴墨印刷等 形成的配線層（導體層），某些之情況下可爲上述微細的 焊錫凸塊。 於第1配線層3之第2連接焊墊3 b上，作爲第1外 部連接端子而形成有第1突起電極10。於第2配線層4 之第3連接焊墊4a上，作爲第2外部連接端子而形成有 第2突起電極11。作爲第1及第2突起電極10、11係適 用例如錫球。第2及第3連接焊墊上分別載置錫球，藉由 回流而形成由錫球（焊錫凸塊）構成之第1及第2突起電 極10、11。突起電極10、11不限定於錫球，亦可適用金 屬鍍膜之積層體等。但是，在考慮以低成本製作具有某種 -9 - 201248808 程度之高度之突起電極10、π時，較好是適用由錫球構 成的突起電極10、11。 於配線基板2第1面2a上，形成將半導體晶片6連 同金屬導線9或第1突起電極1〇予以密封的樹脂密封層 12。半導體晶片6或金屬導線9係被樹脂密封層12完全 密封，但爲使第1突起電極10作爲外部連接端子之機能 ’而使其之一部分由樹脂密封層12露出。樹脂密封層12 係具有使第1突起電極10之一部分露出之凹部13。換言 之，第1突起電極10乃大部分被埋設於樹脂密封層12內 ，而一部分露出於由樹脂密封層12表面朝第1突起電極 1 〇被形成的凹部1 3內。 如後述說明，凹部1 3係針對樹脂密封層1 2之相當於 第〗突起電極10之部分實施切削或溶融，或者在樹脂密 封用之模具設置和凹部13對應的凸部而被形成。對樹脂 密封層12 —部分實施切削或溶融而形成凹部13時，係對 樹脂密封層12連同第1突起電極10之一部分進行切削或 溶融，而使第1突起電極10之一部分由樹脂密封層12之 凹部13內露出。使用凸部模具時，係將凸部之高度調整 成爲接觸於第1突起電極10而形成露出面的高度，而使 第1突起電極10之一部分由模具之凸部所形成之凹部13 內露出。 圖1所示半導體裝置1之凹部13，係具有樹脂密封 層1 2之端面側之側面呈開放之形狀。亦即，圖1所示凹 部13係以至樹脂密封層12之端面爲止被除去的方式予以 -10- 201248808 形成，如此則，一方之側面被開放。凹部1 3之形狀，不 限定於圖1所示形狀。圖2所示半導體裝置1之凹部13 ，係具有全側面被設爲壁面之溝狀之形狀。凹部1 3，只 要不妨礙半導體晶片6或金屬導線9之樹脂密封狀態，由 樹脂密封層12表面朝深度方向，而至第1突起電極1〇之 一部分呈露出之位置爲止被形成即可。 第1及第2突起電極10、11之高度，如後述說明， 係設爲在積層複數個半導體裝置1時，可以達成上下之半 導體裝置1間之電連接的高度。將複數個半導體裝置1予 以積層而成爲POP構造之半導體模組時，係將下段側之 半導體裝置1之第1突起電極10與上段側之半導體裝置 1之第2突起電極11連接，而使上下之半導體裝置丨間 被電連接。因此’第1突起電極10與第2突起電極11之 合計高度（連接高度），係設爲半導體裝置1之樹脂密封 層12之厚度（除去凹部13以外之部分之高度）以上。例 如，第1及第2突起電極10、π之高度，係設爲樹脂密 封層12之厚度之約1/2。第1及第2突起電極10、11之 禹度，未必同一。 使用如上述說明之第1突起電極10與第2突起電極 11’藉由將POP構造中之上下之半導體裝置1間予以電 連接，則可以減少突起電極10' 11之高度，其引起的寬 度（例如錫球之時爲直徑）或形成間距。和上下之半導體 裝置間僅藉由上段側之半導體裝置所設置的突起電極進行 連接時比較’各突起電極10、11之大小可設爲約1/2，另 -11 - 201248808 外，形成間距亦可減少。因此，不會妨礙半導體模組之小 型化，亦可應付輸出入數之增大或半導體晶片之積層數之 增加。 P OP構造之半導體模組之構成時，下段側之半導體裝 置1之凹部1 3之寬度，係設爲其中可以配置上段側之半 導體裝置1之第2突起電極11。例如，第1突起電極10 與第2突起電極11之大小設爲大略同一時，凹部13之寬 度較好是設爲突起電極1 〇、Π之大小（例如錫球時爲直 徑）之1 · 2倍以上。如此則，下段側之半導體裝置1之第 1突起電極10與上段側之半導體裝置1之第2突起電極 11，可以實施穏定之電連接。凹部13之寬度之上限並未 特別限定。但是，凹部13之寬度太寬將導致半導體裝置 1之形狀變爲大型化，因此凹部13之寬度較好是設爲突 起電極1 0、1 1之大小之3倍以下。 上述實施形態之半導體裝置1，例如係如以下被作製 。參照圖3A至圖3G、圖4、圖5及圖6說明半導體裝置 1之製造工程。如圖3A所示，準備設有第1配線層3的 第1面2a與設有第2配線層4的第2面2b以及配線基板 2。配線基板2係具有複數個和半導體裝置1對應的裝置 形成區域X。以下之各工程係對複數個裝置形成區域X實 施。在配線基板2之第1面2 a所設置的第1配線層3之 第2連接焊墊上，形成第1突起電極1〇。使用錫球作爲 第1突起電極10時，係於第2連接焊墊上載置錫球後實 施回流。 -12- 201248808 接著，如圖3B及圖3C所示，於配線基板2第1面 2a所設置的晶片搭載區域，將半導體晶片6予以搭載。 半導體晶片6之搭載工程，係對應於半導體晶片6之積層 數或積層形狀而適宜實施。圖3B係表示將相當於第1晶 片群7的複數個半導體晶片6積層爲階梯狀後，使彼等半 導體晶片6之電極焊墊與第1配線層3之第1連接焊墊與 ，藉由Au導線等之金屬導線9實施電連接之狀態。圖3C 係表示於第1晶片群7上，將相當於第2晶片群8的複數 個半導體晶片6，朝第1晶片群7之逆向積層爲階梯狀後 ，使彼等半導體晶片6之電極焊墊與第1配線層3之第1 連接焊墊與，藉由Au導線等之金屬導線9實施電連接之 狀態。 接著，如圖3D所示，於配線基板2之第1面2a上， 藉由例如模鑄成型而形成將半導體晶片6連同金屬導線9 或第1突起電極10予以密封的密封樹脂層12。圖3D係 表示半導體晶片6以密封樹脂層1 2覆蓋後，形成凹部1 3 之情況。此情況下，密封樹脂層1 2係以可覆蓋半導體晶 片6之厚度、一樣而且平坦地被形成。密封樹脂層1 2係 形成於包含裝置形成區域X間之切斷區域全體之。和密 封樹脂層12之形成同時而形成凹部13時，密封樹脂層 1 2之形狀，於模鑄成型後係成爲圖3 E所示形狀。 接著，如圖3 E所示，於密封樹脂層1 2形成使第1突 起電極10之一部分露出的凹部13。凹部13之形成工程 ，係如圖4所示，針對密封樹脂層1 2之第1突起電極1〇 -13- 201248808 之形成位置（形成區域）所對應的部分，由密封樹脂層 1 2表面側藉由刀刃1 4實施切削加工。此時，凹部1 3之 深度係以第1突起電極10之一部分被切削的方式予以設 定，如此而使第1突起電極10之一部分由凹部13內露出 。藉由密封樹脂層12之切削加工來形成凹部13之形成工 程，亦可取代刀刃加工，改由切割機（router )加工等來 實施。 凹部〗3之形成工程，如圖5所示，係針對密封樹脂 層1 2之第1突起電極1 0之形成位置（形成區域）所對應 的部分，藉由例如雷射1 5進行溶融加工而實施。此時， 藉由溶融除去密封樹脂層12直至第1突起電極10之一部 分呈露出之深度爲止，如此而形成使第1突起電極10之 一部分露出的凹部13。亦即，第1突起電極10之一部分 可由凹部13內露出。密封樹脂層12之溶融加工，亦可使 用雷射1 5以外之局部加熱。 贲施密封樹脂層1 2之切削加工或溶融加工時，亦可 針對鄰接之裝置形成區域X之密封樹脂層12之加工區域 統合ΪΪ施切削或溶融。此情況下，分割爲裝置形成區域X 之後，形成圖1所示凹部1 3。藉由僅對1處之裝置形成 區域X之加工區域進行切削或溶融，分割爲裝置形成區 域X後，形成圖2所示凹部1 3。凹部1 3之形狀可爲圖1 及圖2之任一》但是，欲降低凹部13之形成成本時，較 好是針對鄰接之裝置形成區域X之密封樹脂層12之加工 區域統合進行切削或溶融。
-14- 201248808 凹部1 3之形成工程，如圖6所示，可以使用具有和 凹部13對應的凸部16之模具17來形成密封樹脂層I]而 加以進行。此情況下’和密封樹脂層1 2之形成同時而形 成凹部1 3。亦即，在密封樹脂之模鑄成型所使用的上模 (模具1 7 ) ’事先形成凹部1 3所對應的凸部1 6。使用此 種上模（模具1 7 )，對密封樹脂層1 2實施模鑄成型，而 可以獲得具有凹部13的密封樹脂層12。以和第1突起電 極1〇呈特定之面積接觸的方式來調整凸部16之高度，則 可使第1突起電極10之一部分由凸部16所形成凹部13 內露出。 之後，如圖3F所示，在配線基板2之第2面2b所設 置的第2配線層4之第4連接焊墊上，形成第2突起電極 Π。第2突起電極11係和第1突起電極10同樣被形成。 如圖3G所示，藉由刀刃時序等沿著裝置形成區域32切 斷配線基板2，可製作個片化之半導體裝置1。圖3A至 圖3G係表示圖1所示半導體裝置1之製造工程。圖2所 示半導體裝置1，除凹部13之形狀不同以外，均和圖1 所示半導體裝置1同樣而予以製作。凹部1 3之形狀，係 藉由凹部13之形成用的刀刃14之形狀、雷射15之加工 形狀、模具1 7之凸部1 6之形狀等加以調整。 接著，參照圖7至圖1 1說明使用上述實施形態之半 導體裝置1的半導體模組。如彼等圖所示，實施形態之半 導體模組係具備複數個上述說明之實施形態之半導體裝置 1。半導體模組具有將複數個半導體裝置1積層而構成的 -15- 201248808 POP構造。圖7係表示第1實施形態之半導體模組20。 半導體模組20，係具備第1至第4半導體封裝1 A〜1D。 4個之半導體封裝1A〜1D均使用實施形態之半導體裝置 1。半導體裝置1之積層數不限定此4個，可爲其以下或 以上。 於第1半導體封裝1A上積層著第2半導體封裝1B。 第2半導體封裝1B之第2突起電極11，係配置於第1半 導體封裝1A之凹部13內，於其之上被電連接第1半導 體封裝1A之第1突起電極10。第2半導體封裝1B之第 2突起電極11，係和由第1半導體封裝1A之第1突起電 極10之凹部13內露出之部分，換言之和由第1突起電極 10之密封樹脂層12露出之部分呈電連接。第1及第2突 起電極1 〇、Π由錫球構成時，係藉由回流工程等對錫球 彼此進行電氣及機械連接。 於第2半導體封裝1B上積層著第3半導體封裝1C» 於第3半導體封裝1C上積層著第4半導體封裝1D。第2 半導體封裝1B與第3半導體封裝1C之間，及第3半導 體封裝1C與第4半導體封裝1D之間，同樣被實施電氣 及機械連接。亦即，上段側之半導體封裝（1C，1D)之 第2突起電極1 1，係配置於下段側之半導體封裝（1 B， 1C)之凹部13內，而且被電連接於第1突起電極10之露 出部分。
如上述說明，藉由使用上段側之半導體封裝（1 B， 1C，1D)之第2突起電極1與下段側之半導體封裝（1A
-16- 201248808 ，IB，1C)之第1突起電極10’進行POP構造中之上下 之半導體裝置1間之電連接。如此則可減少突起電極10 、Η之高度，減少其引起的寬度（例如錫球時爲直徑） 或形成間距。和上下之半導體封裝間僅藉由設於上段側之 半導體裝置的突起電極實施連接時比較’突起電極10、 1 1之大小可以設爲約1 /2，能更進一步減少形成間距。 上下之半導體裝置1間之連接用的突起電極10、11 之大小或形成間距可以被減少，因此可以增加突起電極 10、π之設置數。半導體模組20之形狀設爲同一時，可 應付多端子化（輸出入數之增大）。在實現同一之輸出入 數時，可達成半導體模組20之小型化。另外，欲增加1 個半導體裝置1中之半導體晶片6之積層數時，換言之對 應於與半導體晶片6之積層數而使密封樹脂層12之高度 變高時’亦可抑制突起電極1 〇、11之大小或形成間距之 增大。因此，不會妨礙半導體模組20之小型化或多端子 化’可以應付半導體晶片6之積層數之增加。 於該實施形態中之POP構造之半導體模組20，係將 同一構造之半導體裝置丨予以積層而構成，半導體裝置1 之多段化變爲容易。因此，半導體模組2 〇中之半導體晶 片ό之積層數（例如半導體晶片6爲記憶體晶片時爲其之 記憶容量）容易增大。藉由使用同—構造之半導體裝置1 ’各構成材料（配線基板1等）或成型構件（模具等）僅 需1種類’可減輕半導體模組20之製造成本。另外，可 以調整半導體裝置1間之變形方向，可提升半導體模組 -17- 201248808 20之製造性或可靠性。 成爲下段側之半導體裝置1之連接端子的第1突起電 極10，係除了露出部分以外均被埋入密封樹脂層12內， 因此，和連接露出之突起電極彼此時比較，第1突起電極 10與上段側之半導體裝置1之連接端子、亦即第2突起 電極1 1間之連接性或連接後之強度可以提升。另外上段 側之半導體裝置1之連接端子、亦即第2突起電極11， 係配置於下段側之半導體裝置1之凹部1 3內，因此對於 第1突起電極10之位置精度容易提升。因此，可以提升 上下之半導體裝置1間之連接精度。 構成半導體模組20的半導體裝置1之構成，可爲各 種變形。第1及第2突起電極10、11，不限定於在半導 體晶片6之周圍設置1列，可於半導體晶片6之周圍設置 2列以上。圖8係表示將半導體裝置1Α〜1D積層而成的 半等體模組20，半導體裝置1Α〜1D分別具有被形成爲2 列的第1及第2突起電極10Α、10Β、11Α、11Β。位於最 上段之半導體封裝1D，其上未被積層半導體封裝，因此 如圖9所示可省略第1突起電極10與凹部13。亦可僅省 略凹部13。 圖I 〇係表示第2贲施形態之半導體模組3 0。圖1 0 所示半導體模組30,係具備第1半導體封裝1Α，積層於 其上的第2半導體封裝1Β。第1及第2半導體封裝1Α、 1 Β，係具有和第1實施形態之半導體模組20同樣之構成 ，而且半導體封裝ΙΑ，1Β間係和第1實施形態之半導體
-18- 201248808 模組20同樣被連接。半導體裝置！之積層數只要是 以上即可，未特別限定’第1實施形態同樣可爲4個 上。 第2實施形態之半導體模組30，係於最下段配 有突起電極31的配線基板32，該突起電極31係使 錫凸塊等作爲外部連接端子。第1半導體封裝1Α與 段用配線基板3 2間之電連接，係藉由將第1半導體 1Α之第2突起電極11接合於配線基板32之上面側 線層3 3來進行。配線基板3 2之突起電極31，係和 體模組1中之第2突起電極11以不同的圖案被配列t 半導體模組3 0之第2突起電極1 1，僅被配置於 基板2之外周區域，因此其之配列形狀不受限制。針 點，藉由使用最下段用配線基板32，可以提高作爲 連接端子的突起電極31之配列形狀之自由度。例如 使突起電極3 1之配列形狀對應於既存之配線圖案， 高半導體模組3 0之泛用性。 圖Π係表示第3實施形態之半導體模組40。丨 所示半導體模組40，係和第2實施形態之半導體模) 同樣，具備第1半導體封裝1A與第2半導體封裝1E 導體封裝ΙΑ，1B之構成、積層數、連接形態等，係 2實施形態同樣。第3實施形態之半導體模組40，係 下段配置専用之半導體封裝41。最下段専用之半導 裝41係具備配線基板43，該配線基板43係和第2 形態中之配線基板3 2同樣具備作爲外部連接端子的 2個 或以 置具 用焊 最下 封裝 之配 半導 配線 對此 外部 ，可 而提 Ell I 30 。半 和第 於最 體封 實施 突起 -19- 201248808 電極42，該突起電極42係由和半導體裝置1中之第2突 起電極11不同的圖案配列而成。 藉由使用最下段専用之半導體封裝41，可提高半導 體模組40之泛用性。使用最下段専用之半導體封裝41時 ，可於半導體封裝41內將和半導體晶片6不同的半導體 晶片44，例如半導體晶片6爲記憶體晶片時可將控制晶 片44予以配置》另外，於最下段専用之半導體封裝41， 亦可配置被動元件等之晶片元件45。藉由使用此種最下 段専用之半導體封裝4 1，可實現半導體模組40之高機能 化。最下段専用之半導體封裝41，係和第1及第2半導 體封裝ΙΑ、1B同樣，具備第1突起電極10、密封樹脂層 I2及使第1突起電極10露出的凹部13等。 以上說明本發明之幾個實施形態，但是彼等實施形態 僅爲一例，並非用來限定本發明。彼等新規之實施形態可 以其他各種形態η施，在不脫離發明要旨之範圍內可進行 各種省略、取代或變更。彼等實施形態或其變形亦包含於 發明之範圍或要旨之同時，亦包含於申請專利範圍記載之 發明及其之等效範圍。 【圖式簡單說明】 圖1係表示第1實施形態之半導體裝置之斷面圖。 圖2係表示第2實施形態之半導體裝置之斷面圖。 圖3Α至圖3G係表示實施形態之半導體裝置之製造 工程之斷面圖。
-20- 201248808 圖4係表示圖3A至圖3G所示半導體裝置之製造工 程中之密封樹脂層之形成工程之第1例。 圖5圖係表示3A至圖3G所示半導體裝置之製造工 程中之密封樹脂層之形成工程之第2例。 圖6圖係表示3A至圖3G所示半導體裝置之製造工 程中之密封樹脂層之形成工程之第3例。 圖7係表示第1實施形態之半導體模組之斷面圖。 圖8係表示第1實施形態之半導體模組之變形例之斷 面圖。 圖9係表示第1實施形態之半導體模組之另一變形例 之斷面圖。 圖1 〇係表示第2實施形態之半導體模組之斷面圖。 圖11係表示第3實施形態之半導體模組之斷面圖。 【主要元件符號說明】 1 :半導體裝置 2 :配線基板 2a :第1面（上面） 2b :第2面（下面） 3 :第1配線層 4 :第2配線層 5 :通孔 3a :第1連接焊墊 3b :第2連接焊墊 -21 - 201248808 4a :第3連接焊墊 6 :半導體晶片 6a :電極焊墊 7 :第1晶片群 8 :第2晶片群 9 :金屬導線 1 〇 :第1突起電極 1 1 :第2突起電極 1 2 :樹脂密封層 13 :凹部
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Claims (1)

  1. 201248808 七、申請專利範圍： 1. 一種半導體裝置，係具備： 具有第1面及第2面的配線基板，該第1面係具備晶 片搭載區域及第1配線層，該第2面係具備電連接於上述 第1配線層的第2配線層； 半導體晶片，被搭載於上述配線基板之上述第1面， 具有電極焊墊： 連接構件，用於電連接上述第1配線層與上述電極焊 墊； 第1突起電極，被設於上述配線基板之上述第1面， 被電連接於上述第1配線層； 第2突起電極，被設於上述配線基板之上述第2面， 被電連接於上述第2配線層；及 密封樹脂層，以將上述半導體晶片連同上述連接構件 及上述第1突起電極予以密封的方式，被設於上述配線基 板之上述第1面上，而且具有使上述第1突起電極之一部 分露出的凹部。 2. 如申請專利範圍第1項之半導體裝置，其中， 上述第1及第2突起電極係具備錫球。 3. 如申請專利範圍第1項之半導體裝置，其中， 上述凹部，係具有使上述密封樹脂層之端面側之側面 被開放的形狀。 4. 如申請專利範圍第1項之半導體裝置，其中， 上述第1突起電極與上述第2突起電極之合計高度爲 -23- 201248808 上述密封樹脂層之厚度以上。 5 .如申請專利範圍第1項之半導體裝置，其中， 上述第1及第2突起電極，係具有上述樹脂密封層之 厚度之大略1/2高度。 6 如申請專利範圍第1項之半導體裝置，其中， 上述凹部，係具有上述第1及第2突起電極之大小之 1 ·2倍以上3倍以下之範圍之寬度。 7. 如申請專利範圍第1項之半導體裝置，其中， 於上述配線基板之上述第1面，積層著複數個上述半 導體晶片。 8. 如申請專利範圍第7項之半導體裝置，其中， 於上述複數個半導體晶片中之最下段之上述半導體晶 片之上述電極焊墊與上述第1配線層之間，及上述複數個 半導體晶片之上述電極焊墊間，係藉由作爲上述連接構件 之金屬導線依序予以連接。 9. —種半導體裝置之製造方法，係具備 在設於配線基板之第1面的晶片搭載區域，將具有電 極焊墊的半導體晶片予以搭載的工程； 使設於上述配線基板之上述第1面的第1配線層與上 述電極焊墊經由連接構件進行電連接的工程； 在上述配線基板之上述第1面上，形成電連接於上述 第1配線層之第1突起電極的工程： 在上述配線基板之上述第1面上，針對上述半導體晶 片連同上述連接構件及上述第1突起電極進行密封之同時 -24- 201248808 ，形成具有使上述第1突起電極之一部分露出之凹部的密 封樹脂層的工程；及 在具備和上述第1配線層呈電連接的第2配線層之上 述配線基板之第2面上，形成電連接於上述第2配線層之 第2突起電極的工程。 10. 如申請專利範圍第9項之半導體裝置之製造方法 ，其中， 上述密封樹脂層之形成工程，係具備在上述配線基板 之上述第1面上平坦地形成用來密封上述半導體晶片、上 述連接構件及上述第1突起電極之樹脂層的工程：及針對 上述樹脂層之和上述第1突起電極之形成位置呈對應之部 分，以使上述第1突起電極之一部分被削去的方式實施切 削而形成上述凹部的工程。 11. 如申請專利範圍第9項之半導體裝置之製造方法 ，其中 上述密封樹脂層之形成工程，係具備：在上述配線基 板之第1面上平坦地形成樹脂層的工程，該樹脂層用於密 封上述半導體晶片、上述連接構件及上述第1突起電極： 及針對上述樹脂層之和上述第1突起電極之形成位置呈對 應的部分，以使上述第1突起電極之一部分露出的方式實 施溶融而形成上述凹部的工程。 12. 如申請專利範圍第9項之半導體裝置之製造方法 ，其中， 上述密封樹脂層之形成工程，係具備：使用具有和上 -25- 201248808 述凹部對應的凸部之模具，來形成具有上述凹部之密封樹 脂層的工程。 13. 如申請專利範圍第9項之半導體裝置之製造方法 ’其中， 上述第〗及第2突起電極係具備錫球。 14. 如申請專利範圍第9項之半導體裝置之製造方法 ，其中， 於上述配線基板之第1面將複數個上述半導體晶片予 以積層。 1 5 —種半導體模組，係具備： 第1半導體封裝，其具備申請專利範圍第1項之半導 體裝置；及 第2半導體封裝，其具備申請專利範圍第1項之半導 體裝置，被積層於上述第1半導體封裝上； 上述第2半導體封裝中之上述第2突起電極，係配置 於上述第1半導體封裝中之上述凹部內，而且電連接於由 上述第1突起電極之上述密封樹脂層露出之部分。 16. 如申請專利範圍第1 5項之半導體模組，其中， 上述第1及第2突起電極係具備錫球。 17. 如申請專利範圍第15項之半導體裝置，其中， 上述第1半導體封裝中之上述第1突起電極與上述第 2半導體封裝中之上述第2突起電極之連接高度，係在上 述第1半導體封裝中之上述密封樹脂層之厚度以上。 18. 如申請專利範圍第1 5項之半導體模組，其中， -26- 201248808 上述第1半導體封裝與上述第2半導體封裝，係具備 同一構造之上述半導體裝置。 1 9 ·如申請專利範圍第1 5項之半導體模組，其中， 另外具備配置於上述第1半導體封裝之下側的最下段 用配線基板； 上述最下段用配線基板，係具有藉由和上述第1半導 體封裝之上述第2突起電極不同的圖案配列而成的外部連 接端子，而且被電連接於上述第1半導體封裝中之上述第 2突起電極。 20-如申請專利範圍第1 5項之半導體模組，其中， 另外具備配置於上述第1半導體封裝之下側的最下段 専用之半導體裝置； 上述最下段専用之半導體裝置，係具備：設於配線基 板之第1面的第1突起電極；及設於上述配線基板之第2 面，藉由和上述第1半導體封裝之上述第2突起電極不同 的圖案配列而成的外部連接端子； 上述最下段専用之半導體裝置之上述第1突起電極， 係電連接於上述第1半導體封裝中之上述第2突起電極。 -27-
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